CN809J [CONSONANCE]
Ultra Low Power Microprocessor Reset IC;型号: | CN809J |
厂家: | Shanghai Consonance Electronics Incorporated |
描述: | Ultra Low Power Microprocessor Reset IC |
文件: | 总7页 (文件大小:144K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CONSONANCE
Ultra Low Power Microprocessor Reset IC
CN803/809/CN810
General Description
Features
The CN803/809/810 series are micro- processor
(µP) supervisory circuits used to monitor the
power supplies in µP and digital systems. They
provide excellent circuit reliability and low cost
by eliminating external components.
Precise Reset Threshold: ±2.5%
CMOS Output(CN809/810) and Open Drain
Output(CN803)
140ms min Reset Pulse Width
3.2µA Supply Current @VCC=3V
Guaranteed Reset Valid to VCC = +1.15V
Power Supply Transient Immunity
Operating Temperature Range
-40°C to +85°C
These circuits perform a single function: they
assert a reset signal whenever the VCC supply
voltage declines below a preset threshold, keeping
it asserted for at least 140ms after VCC has risen
above the reset threshold.
Available in SOT23-3
The CN809/810 have CMOS outputs, the CN803
has open drain output. The CN803/809 have an
Pin Assignment
active-low
output, while the CN810 has
an active-high RESET output. The reset
1
GND
comparator is designed to ignore fast transients on
CN803
CN809
CN810
VCC, and the outputs are guaranteed to be in the
3
VCC
correct logic state for VCC down to 1.15V over the
temperature range.
RESET
(RESET)
2
The device is available in 3 pin SOT23 package.
SOT23-3
( ) is for CN810 only
Applications
Computers
Portable/Battery-Powered Equipment
Intelligent Instruments
Controllers
www.consonance-elec.com
Rev 1.2
1
Device Function Reference Table:
Reset
threshold
4.63V
4.63V
4.38V
4.38V
4.00V
3.08V
2.93V
2.93V
2.93V
2.63V
2.63V
Reset active
Part No.
Output Type
Marking
Low or High
Low
CN809L
CN810L
CN809M
CN810M
CN809J
CN809T
CN803S
CN809S
CN810S
CN803R
CN809R
CMOS
CMOS
AAAA
AGAA
ABAA
AHAA
CWAA
ACAA
ABC
High
Low
CMOS
High
Low
CMOS
CMOS
Low
CMOS
Low
Open Drain
CMOS
Low
ADAA
AKAA
ABD
High
Low
CMOS
Open Drain
CMOS
Low
AFAA
Block Diagram
VCC
OSC
VCC
RESET
(RESET)
Delay
Generator
+
COMP
1.25V
-
GND
Fig.1 Block Diagram For CMOS Output
Rev 1.2
2
Pin Description
Pin No.
Description
Symbol
1
GND
Ground terminal
CMOS Output. This output remains low if VCC drops
below VRES, and for at least 140ms after VCC rises above
(CN809)
VRES + VHYST .
CMOS Output. This output remains high if VCC drops
RESET
2
3
below VRES, and for at least 140ms after VCC rises above
(CN810)
VRES + VHYST.
Open Drain Output. This output remains low if VCC
drops below VRES, and for at least 140ms after VCC rises
(CN803)
VCC
above VRES + VHYST
.
Analog Input. This pin is both the power supply to
internal circuit and the voltage to be monitored.
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (With respect to GND)
Thermal Resistance…………………..300°C/W
Operating Temperature.…..……...-40 to +85°C
Storage Temperature.....…….......-65 to +150°C
Maximum Junction Temperature... +150°C
Lead Temperature (soldering, 10s) .......+300°C
ESD Rating(HBM)……….……….………4KV
VCC.............…...…......-0.3V to +6.0V
, RESET …....-0.3V to +6.0V
Input/Output Current
CC .........................................20mA
, RESET ..…….….....20mA
V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Rev 1.2
3
Electrical Characteristics (VCC=3V, TA= -40℃ to 85℃, Typical values are at TA=25℃,
unless otherwise noted.)
Parameters
Symbol
Test Conditions
Min
Typ
Max
Unit
Maximum
input
5.5
V
VCCMAX
voltage
Minimum
voltage
input
1.15
V
VCCMIN
2.8
3.2
5.5
6
VCC=2.0V
Supply current
uA
IVCC
VCC=3.0V
VCC=5.0V
CN8__L
CN8__M
CN8__J
4.0
7.5
4.51
4.25
3.89
3.0
4.63
4.38
4.00
3.08
2.93
2.63
2.32
4.75
4.5
4.11
3.15
3.0
Reset Threshold
V
CN8__T
CN8__S
CN8__R
CN8__Z
VRES
2.86
2.56
2.26
2.7
2.38
Reset
Threshold
V
VHYST
0.013VRES
hysteresis
VCC
transitions
from
from
VCC to
20
us
Delay(CN803/809)
VRES+0.1V to VRES-0.1V
VCC
transitions
VCC to RESET
Delay(CN810)
20
us
V
VRES+0.1V to VRES-0.1V
0.3
0.3
0.3
VRES>VCC=2V,ISINK=1.5mA
VRES>VCC=3V,ISINK=3.2mA
Output
Voltage Low
(CN803/809)
VOL
V
RES>VCC=4V,ISINK=5mA
VRES<VCC=3V,ISRC=1.2mA VCC-0.4
VRES<VCC=4V,ISRC=2mA VCC-0.4
RES<VCC=5V,ISRC=2.5mA VCC-0.4
Output
Voltage High
(CN809)
V
V
VOH
V
0.3
0.3
0.3
RESET
Output
VRES<VCC=3V,ISINK=3.2mA
VRES<VCC=4V,ISINK=5mA
Voltage Low
(CN810)
VOL
VRES<VCC=5V,ISINK=6mA
RESET
Output
VRES>VCC=2V,ISRC=600uA VCC-0.4
VRES>VCC=3V, ISRC=1.2mA VCC-0.4
Voltage High
(CN810)
V
VOH
VRES>VCC=4V, ISRC=2mA
VCC-0.4
140
Reset Pulse Width
240
400
ms
TRES
Note : Parts are 100% production tested at 25oC. Specifications over full temperature range are
guaranteed by design
Rev 1.2
4
Detailed Description
A microprocessor’s (µP’s) reset input starts the µP in a known state. The CN803/809/810 series assert reset
to prevent code-execution errors during power-up, power-down, or brownout conditions. The device
consists of a comparator, a low current high precision voltage reference, voltage divider, output delay
circuit and output driver. They assert a reset signal whenever the VCC supply voltage declines below a
preset threshold, keeping it asserted for at least 140ms after VCC has risen above the reset threshold.
The CN809/810 have a CMOS output stage, the CN803 has an open drain output stage. The CN803/809
have an active-low
output, while the CN810 has an active-high RESET output. The reset
comparator is designed to ignore fast transients on VCC, and the outputs are guaranteed to be in the correct
logic state for VCC down to 1.15V over the temperature range.
The operation of the device can be best understood by referring to figure 3.
VCC
VRES + VHYST
VRES
VCCMIN
VCCMIN
RESET
TRES
Fig.2 Timing waveform
Applications Information
Negative-Going VCC Transients
In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, the
CN803/809/810 series are relatively immune to short-duration negative-going VCC transients (glitches). As
the magnitude of the transient increases (goes farther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts 10µs
or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the VCC pin
provides additional transient immunity.
Ensuring a Valid Reset Output Down to VCC = 0
When VCC falls below 1.15V, the CN809
circuit. Therefore, high-impedance CMOS logic inputs connected to
voltages. This presents no problem in most applications, since most µP and other circuitry is inoperative
output no longer sinks current—it becomes an open
can drift to undetermined
with VCC below 1.15V. However, in applications where
resistor is needed from
must be valid down to 0V, a pull-down
output will be held at
pin to GND as shown in Figure 4, then
low state. The resistor’s value is not critical, it should be about 100KΩ, large enough not to load
,
Rev 1.2
5
small enough to pull
to ground.
A 100KΩ pull-up resistor to VCC is also recommended for the CN810 if active high RESET is
required to remain valid for VCC < 1.15V.
CN809
RESET
Fig.3 RESET Valid to Ground Circuit
Rev 1.2
6
Package Information
Consonance Electronics does not assume any responsibility for use of any circuitry described. Consonance
reserves the right to change the circuitry and specifications without notice at any time.
Rev 1.2
7
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