CBM708T [COREBAI]
OPERATION INSTRUCTION;
| 型号： | CBM708T |
| 厂家： | 
Corebai |
| 描述： | OPERATION INSTRUCTION |
| 文件： | 总19页 (文件大小：2421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CBM706P/706R/706S/706T/708R/708S/708T
OPERATION INSTRUCTION
FEATURES
GENERAL DESCRIPTION
Precision supply voltage monitor
2.63 V (CBM706P, CBM706R, CBM708R)
The CBM706P/ CBM706R/ CBM706S/
CBM706T and the CBM708R/ CBM708S /
CBM708T microprocessor supervisory circuits
are suitable for monitoring either 3V or 3.3V
power supplies.
2.93 V (CBM706S, CBM708S)
3.08 V (CBM706T, CBM708T)
100µA quiescent current
200ms reset pulse width
The CBM706P/ CBM706R/ CBM706S/
CBM706T provide power supply monitoring
circuitry that generate a reset output during
power-up, power-down, and brownout
conditions. The reset output remains
operational with VCC as low as 1V.
ꢀꢀꢀꢀ
Debounced manual reset input (MR)
Independent watchdog timer
1.6 sec timeout (CBM706P, CBM706R,
CBM706S, CBM706T)
Independent
watchdog
monitoring
Voltage monitor for power fail or low
battery warning
circuitry is also provided. This activates if the
watchdog input does not toggle within 1.6
sec.
ꢀꢀꢀꢀꢀꢀꢀ
Guaranteed RESET valid with VCC = 1 V
Superior upgrade for ADM706P/R/S/T,
ADM708R/S/T
In addition, there is a 1.25V threshold
detector for a power fail warning, low battery
detection, or to monitor an additional power
APPLICATIONS
ꢀꢀꢀꢀ
supply. An active low debounced MR input is
also included.
Microprocessor systems
Computers
The CBM706R, CBM706S, and CBM706T
are identical except for the reset threshold
monitor levels, which are 2.63V, 2.93V, and
3.08V, respectively. The CBM706P is identical
to the CBM706R in that the reset threshold is
2.63V. It differs only in that it has an active
high reset output.
Controllers
Intelligent instruments
Critical microprocessor monitoring
Battery operated systems
Portable instruments
The CBM708R/ CBM708S/ CBM708T
provide
similar
functio-nality
as
the
CBM706R/CBM706S/CBM706T and only differ
in that a watchdog timer function is not
available. Instead, an active high reset output
(RESET) is provided in addition to the active
ꢀꢀꢀꢀꢀꢀꢀ
low (RESET) output.
All devices are available in narrow 8-lead
PDIP and 8-lead SOIC packages.
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CBM706P/706R/706S/706T/708R/708S/708T
OPERATION INSTRUCTION
FUNCTIONAL BLOCK DIAGRAMS
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
Figure 1. CBM706P/CBM706R/CBM706S/CBM706T
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
Figure 2. CBM708R/CBM708S/CBM708T
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OPERATION INSTRUCTION
SPECIFICATIONS
VCC = 2.70 V to 5.5 V (CBM706P/CBM706R/CBM708R), VCC = 3.00 V to 5.5 V (CBM70XS), VCC
=
3.15 V to 5.5 V (CBM70XT), TA = TMIN to TMAX unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY
Min
Typ
Max
Unit
Test Conditions/Comments
VCC Operating Voltage Range
Supply Current
1.0
5.5
200
150
V
100
μA
μA
VCC < 3.6 V
VCC < 5.5 V
LOGIC OUTPUT
Reset Threshold(VRST
)
2.55
2.85
3.00
2.63
2.93
3.08
20
2.70
3.00
3.15
V
V
CBM706P/CBM706R/CBM708R
CBM706S/CBM708S
V
CBM706T/CBM708T
Reset Threshold Hysteresis
RESET PULSE WIDTH
mV
CBM706P/CBM706R/CBM708R,
VCC=3V
160
200
280
ms
VCC = 3.3 V
200
ms
VCC = 5.0 V
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RESET OUTPUT VOLTAGE (CBM706R/CBM708R/CBM706S/CBM708S/CBM706T/CBM708T)
VOH
0.8 × VCC
V
V
V
V
V
VRST(max)<VCC<3.6V, ISOURCE=500μA
VRST(max)<VCC<3.6V, ISINK = 1.2mA
4.5V<VCC<5.5V, ISOURCE = 800μA
4.5V<VCC<5.5V, ISINK = 3.2 mA
VCC=1V, ISINK = 100μA
VOL
0.3
VOH
VCC−1.5V
VOL
0.4
0.3
VOL
RESET OUTPUT VOLTAGE (CBM706P)
VOH
VOL
VOH
VOL
VCC−0.6 V
V
V
V
V
VRST(max)<VCC<3.6V, ISOURCE=215μA
VRST(max)<VCC<3.6V, ISINK=1.2mA
4.5V<VCC<5.5V, ISOURCE=800μA
4.5V<VCC<5.5V, ISINK=3.2mA
0.3
0.4
VCC−1.5V
RESET OUTPUT VOLTAGE (CBM708R/CBM708S/CBM708T)
VOH
VOL
VOH
VOL
0.8 × VCC
V
V
V
V
VRST(max)<VCC<3.6V, ISOURCE=500μA
VRST(max)<VCC<3.6V, ISINK=500μA
4.5V<VCC<5.5V, ISOURCE=800μA
4.5V<VCC<5.5V, ISINK=1.2mA
0.3
0.4
VCC−1.5V
WATCHDOG INPUT (CBM706P/CBM706R/CBM706S/CBM706T)
Watchdog Timeout Period 1.00 1.60 2.25
sec
CBM706P/CBM706R: VCC=3V
CBM706S/CBM706T: VCC=3.3V
VIL=0.4V, VIH=VCC×0.8 V
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OPERATION INSTRUCTION
WDI Pulse Width
100
50
ns
ns
VRST(max)<VCC<3.6 V
4.5V<VCC<5.5 V
WDI Input Threshold
VIL
0.6
0.8
V
V
VRST(max)<VCC<3.6V
VRST(max)<VCC<3.6V
VCC=5.0V
VIH
0.7 × VCC
VIL
V
VIH
3.5
V
VCC=5.0V
WDI Input Current
-1.0
+0.02
+1.0
μA
WDI=0V or VCC
ꢀꢀꢀꢀꢀꢀꢀ
WDO OUTPUT VOLTAGE
VOH
0.8×VCC
V
V
V
V
VRST(max)<VCC<3.6V, ISOURCE=500μA
4.5V<VCC<5.5V, ISOURCE=800μA
VRST(max)<VCC<3.6V, ISINK=500μA
4.5V<VCC<5.5V, ISINK=1.2mA
VCC−1.5V
VOL
0.3
0.6
MANUAL RESET INPUT
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
MR Pull-Up Current (MR=0V)
25
70
250
600
μA
μA
ns
VRST(max)<VCC<3.6V
4.5V<VCC<5.5V
100
500
150
250
ꢀꢀꢀꢀ
MR Pulse Width
VRST(max)<VCC<3.6V
4.5V<VCC<5.5V
ns
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MR INPUT THRESHOLD
VIL
VIH
VIL
VIH
0.6
0.8
V
V
VRST(max)<VCC<3.6V
VRST(max)<VCC<3.6V
4.5V<VCC<5.5V
0.7×VCC
2.0
V
V
4.5V<VCC<5.5V
ꢀꢀꢀꢀ
MR TO RESET OUTPUT DELAY
750
250
ns
ns
VRST(max)<VCC<3.6V
4.5V<VCC<5.5V
POWER FAIL INPUT
PFI Input Threshold
1.2
1.25
1.3
V
CBM706P/CBM706R/CBM708R,
VCC=3V CBM706S/ CBM708S/
CBM706T/CBM708T,VCC=3.3V, PFI
falling
PFI Input Current
-25
+0.01
+25
nA
ꢀꢀꢀꢀꢀ
PFO
OUTPUT VOLTAGE
VOH
VOL
VOH
VOL
0.8×VCC
V
V
V
V
VRST(max)<VCC<3.6V, ISOURCE=500μA
VRST(max)<VCC<3.6V, ISINK=1.2mA
4.5V<VCC<5.5V, ISOURCE=800μA
4.5V<VCC<5.5V, ISINK=3.2mA
0.3
0.4
VCC−1.5V
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OPERATION INSTRUCTION
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Stresses at or above those listed under
Absolute Maximum Ratings may cause
permanent damage to the product. This is a
stress rating only; functional operation of the
product at these or any other conditions
above those indicated in the operational
section of this specification is not implied.
Parameter
Rating
VCC
−0.3V to +6V
−0.3V to
All Other Inputs
VCC+0.3V
Input Current
VCC
20mA
GND
20mA
Operation
beyond
the
maximum
Digital Output Current
Power Dissipation, N-8 PDIP
θJA Thermal Impedance
Power Dissipation, R-8 SOIC
θJA Thermal Impedance
Operating Temperature Range
Industrial (Version A)
Lead Temperature (Soldering,
10 sec)
20mA
operating conditions for extended periods
may affect product reliability.
727mW
135℃/W
470mW
110℃/W
-40℃ to +85℃
300℃
Vapor Phase (60 sec)
Infrared (15 sec)
215℃
220℃
Storage Temperature Range
ESD Rating
-65℃ to +150℃
>4.5kV
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OPERATION INSTRUCTION
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. CBM706P
Figure 4. CBM706R/CBM706S/CBM706T
Pin Function Descriptions
Table3. (CBM706P/CBM706R/CBM706S/CBM706T)
Pin No.
Mnemonic
Description
Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be
driven from TTL, CMOS logic, or from a manual reset switch because it is internally
debounced. An internal 70μA pull-up current holds the input high when floating.
Power Supply Input. Place a 0.1µF decoupling capacitor between the VCC and GND pins.
Ground. Ground reference for all signals (0V).
ꢀꢀꢀꢀ
1
MR
2
3
VCC
GND
Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is
less than 1.25V, PFO goes low. If unused, PFI connects to GND.
4
5
PFI
PFO
Power Fail Output. PFO is the output from the power fail comparator. It goes low when
PFI is less than 1.25V.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the watchdog output, WDO, goes low. The timer resets with each transition at the
WDI input. Either a high to low or a low to high transition clears the counter. The internal
timer is also cleared whenever reset is asserted.
6
7
WDI
RESET
Logic Output. RESET goes low for 200ms when triggered. It is triggered either by VCC
being below the reset threshold or by a low signal on the MR input. RESET remains low
whenever VCC is below the reset threshold. It remains low for 200ms after VCC goes above
the reset threshold or MR goes from low to high. A watchdog timeout does not trigger
RESET unless WDO is connected to MR.
(CBM706R/CBM706S/
CBM706T Only)
Logic Output. RESET is an active high output suitable for systems that use active high
reset logic. It is the inverse of RESET.
7 (CBM706P Only)
RESET
WDO
Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of
inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also
goes low during low line conditions. Whenever VCC is below the reset threshold, WDO
remains low. As soon as VCC goes above the reset threshold, WDO goes high
immediately.
8
6
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OPERATION INSTRUCTION
Figure 5. CBM708R/CBM708S/CBM708T
Table 4. (CBM708R/CBM708S/CBM708T)
Pin No.
Mnemonic
Description
MR
Manual Reset Input. When taken below 0.6V, a RESET/RESET is generated. MR can be
driven from TTL, CMOS logic, or from a manual reset switch because it is internally
debounced. An internal 70μA pull-up current holds the input high when floating.
Power Supply Input. Place a 0.1 µF decoupling capacitor between the VCC and GND pins.
Ground. Ground reference for all signals (0V).
1
2
3
VCC
GND
Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is
less than 1.25V, PFO goes low. If unused, PFI must connect to GND.
Power Fail Output. PFO is the output from the power fail comparator. It goes low when
PFI is less than 1.25V.
4
PFI
PFO
5
6
NC
No Connect.
RESET
Logic Output. RESET goes low for 200ms when triggered. It is triggered either by VCC
being below the reset threshold or by a low signal on the MR input. RESET remains low
whenever VCC is below the reset threshold. It remains low for 200ms after VCC goes above
the reset threshold or MR goes from low to high. A watchdog timeout does not trigger
RESET unless WDO is connected to MR.
7
8
Logic Output. RESET is an active high output suitable for systems that use active high
reset logic. It is the inverse of RESET.
RESET
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OPERATION INSTRUCTION
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. CBM706R/CBM706S/CBM706T and the
ꢀꢀꢀꢀꢀꢀꢀꢀ
Figure 8. PFI Assertion Response Time
RESET
CBM708R/CBM708S/CBM708T
Output
Voltage vs. Supply Voltage
Figure 7. RESET Output Voltage vs. Supply Voltage
Figure 9. PFI Deassertion Response Time
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OPERATION INSTRUCTION
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Figure 10. RESET, RESET Assertion
Figure 12. CBM706R/CBM706S/CBM706T and the
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CBM708R/CBM708S/CBM708T RESET Response
Time
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RESET
Figure 11.
, RESET Deassertion
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OPERATION INSTRUCTION
CIRCUIT INFORMATION
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
Figure 13. CBM706P/CBM706R/CBM706S/CBM706T Functional Block Diagram
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
Figure 14. CBM708R/CBM708S/CBM708T Functional Block Diagram
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OPERATION INSTRUCTION
POWER FAIL RESET OUTPUT
ꢀꢀꢀꢀꢀꢀꢀ
The reset output provides a reset (RESET or RESET ) output signal to the microprocessor
whenever the VCC input is below the reset threshold. The actual reset threshold voltage is
dependent on whether a P, R, S, or T suffix device is used. An internal timer holds the reset
output active for 200ms after the voltage on VCC rises above the threshold. This is intended as a
power-on reset signal for the microprocessor. It allows time for both the power supply and the
microprocessor to stabilize after power-up. If a power supply brownout or interruption occurs,
the reset line is similarly activated and remains active for 200ms after the supply recovers. If
another interruption occurs during an active reset period, the reset timeout period continues for
an additional 200ms.
The reset output is guaranteed to remain valid with VCC as low as 1V. This ensures that the
microprocessor is held in a stable shutdown condition as the power supply starts up.
The CBM706P provides an active high RESET signal; the CBM706R/CBM706S/CBM706T
ꢀꢀꢀꢀꢀꢀꢀ
provide an active low RESET signal; and the CBM708R/CBM706S/CBM706T provide both RESET
ꢀꢀꢀꢀꢀꢀꢀ
and RESET.
MANUAL RESET
ꢀꢀꢀꢀ
The MR input allows other reset sources, such as a manual reset switch, to generate a
processor reset. The input is effectively debounced by the timeout period (200 ms typical). The
ꢀꢀꢀꢀ
MR input is TTL-/CMOS-compatible; it can also be driven by any logic reset output. If unused,
ꢀꢀꢀꢀ
the MR input can be tied high or left floating.
NOTES
RESET = COMPLEMENT OF RESET
ꢀꢀꢀꢀꢀꢀꢀꢀ ꢀꢀꢀꢀ
Figure 15. RESET, MR, and WDO Timing
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OPERATION INSTRUCTION
WATCHDOG TIMER (CBM706P/CBM706R/ CBM706S/CBM706T)
The watchdog timer circuit monitors the activity of the microprocessor to check that it is not
stalled in an indefinite loop. An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the timeout period (1.6 sec), the watchdog
ꢀꢀꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀꢀꢀ
output (WDO) is driven low. The WDO output is connected to a nonmaskable interrupt (NMI)
on the processor. Therefore, if the watchdog timer times out, an interrupt is generated. The
interrupt service routine is used to rectify the problem.
The watchdog timer is cleared either by a high to low or by a low to high transition on WDI.
ꢀꢀꢀꢀꢀꢀꢀ
Pulses as narrow as 50 ns are detected. The timer is also cleared by RESET/RESET going active.
Therefore, the watchdog timeout period begins after reset goes inactive.
ꢀꢀꢀꢀꢀꢀꢀ
When VCC falls below the reset threshold, WDO is forced low whether or not the watchdog
ꢀꢀꢀꢀꢀꢀꢀ
timer has timed out. Normally, this generates an interrupt, but it is overridden by RESET/RESET
going active.
Figure 16. Watchdog Timing
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OPERATION INSTRUCTION
POWER FAIL COMPARATOR
The power fail comparator is an independent comparator that monitors the input power
supply. The inverting input of the comparator internally connects to a 1.25 V reference voltage.
The noninverting input is available at the PFI input. This input monitors the input power supply
via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the
ꢀꢀꢀꢀꢀ
comparator output (PFO) goes low, indicating a power failure. For early warning of power failure,
the comparator monitors the preregulator input by choosing an appropriate resistive divider
ꢀꢀꢀꢀꢀ
network. The PFO output interrupts the processor to implement a shutdown procedure before
the power is lost.
As the voltage on the PFI pin is limited to VCC + 0.3 V, it is recommended to connect the PFI
ꢀꢀꢀꢀꢀꢀꢀ
pin with a Schottky diode to the RESET pin, as shown in Figure 17. This helps with clamping the
PFI pin voltage during device power up and operation.
Figure 17. Power Fail Comparator
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OPERATION INSTRUCTION
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis can be added to the power fail comparator.
Because the comparator circuit is non-inverting, hysteresis is added simply by connecting a
ꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀ
resistor between the PFO output and the PFI input as shown in Figure 18. When PFO is low,
ꢀꢀꢀꢀꢀ
Resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, Resistor
R3 sources current into the PFI summing junction. This results in differing trip levels for the
comparator. Further noise immunity is achieved by connecting a capacitor between PFI and
GND.
Figure 18. Adding Hysteresis to the Power Fail Comparator
R2+R3
VH = 1.25 1 +
VL = 1.25 + R1
R1]
R2×R3
1.25
V −1.25
CC
−
R2
R3
R1+R2
VMID = 1.25
R2
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OPERATION INSTRUCTION
ꢀꢀꢀꢀꢀꢀꢀꢀ
VALID RESET BELOW 1 V VCC
The CBM706R/CBM706S/CBM706T, CBM708R/CBM708S/ CBM708T are guaranteed to
provide a valid reset level with VCC as low as 1 V. Refer to the Typical Performance Characteristics
section. As VCC drops below 1 V, the internal transistor does not have sufficient drive to hold it on
ꢀꢀꢀꢀꢀꢀꢀ
so the voltage on RESET is no longer held at 0 V. A pull-down resistor, as shown in Figure 19,
can connect externally to hold the line low if it is required.
ꢀꢀꢀꢀꢀꢀꢀꢀ
Figure 19. RESET. Valid Below 1V
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OPERATION INSTRUCTION
APPLICATIONS INFORMATION
A typical operating circuit is shown in Figure 20. The unregulated dc input supply is
monitored using the PFI input via the resistive divider network. Resistor R1 and Resistor R2 are to
be selected so that when the supply voltage drops below the desired level (for example, 5V), the
voltage on PFI drops below the 1.25V threshold, thereby generating an interrupt to the
microprocessor. Monitoring the preregulator input gives additional time to execute an orderly
shutdown procedure before power is lost.
Figure 20. Typical Application Circuit
Microprocessor activity is monitored using the WDI input. This is driven using an output line
from the processor. The software routines toggle this line at least once every 1.6 sec. If a problem
ꢀꢀꢀꢀꢀꢀꢀ
occurs and this line is not toggled, WDO goes low and a nonmask-able interrupt is generated.
This interrupt routine is to be used to clear the problem.
ꢀꢀꢀꢀꢀꢀꢀ
If, in the event of inactivity on the WDI line, a system reset is required, the WDO output is to
be connected to the input as shown in Figure 21.
Figure 21. RESET From WDO
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OPERATION INSTRUCTION
MONITORING ADDITIONAL SUPPLY LEVELS
It is possible to use the power fail comparator to monitor a second supply as shown in Figure
22. The two sensing resistors, R1 and R2, are selected such that the voltage on PFI drops below
ꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀ
1.25 V at the minimum acceptable input supply. The PFO output can connect to the MR input
so a reset generates when the supply drops out of tolerance. In this case, if either supply drops
out of tolerance, a reset is generated.
Figure 22. Monitoring 3 V/3.3 V and an Additional Supply, VX
ꢀꢀꢀꢀꢀꢀꢀꢀ
MICROPROCESSOR WITH BIDIRECTIONAL RESET
To prevent contention for microprocessors with a bidirectional reset line, a current limiting
resistor is to be inserted between the CBM706R/CBM706S/CBM706T, CBM708R/CBM708S/
ꢀꢀꢀꢀꢀꢀꢀ
CBM708T RESET output pin and the microprocessor reset pin. This limits the current to a safe
level if there are conflicting output reset levels. A suitable resistor value is 4.7kΩ. If the reset
output is required for other uses, it must be buffered as shown in Figure 23.
ꢀꢀꢀꢀꢀꢀꢀꢀ
RESET
Figure 23. Bidirectional Input/Output
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OPERATION INSTRUCTION
OUTLINE DIMENSIONS
SOIC-8(SOP8)
Dimensions In Millimeters
Dimensions Inches
Min
Symbol
Min
Max
1.750
0.250
1.550
0.510
0.250
5.000
6.200
4.000
Max
0.069
0.010
0.061
0.020
0.010
0.197
0.244
0.157
A
A1
A2
b
1.350
0.100
1.350
0.330
0.170
4.800
5.800
3.800
0.053
0.004
0.053
0.013
0.007
0.189
0.228
0.150
c
D
E
E1
e
1.270 BSC
0.050 BSC
L
0.400
0°
1.270
8°
0.016
0°
0.050
8°
θ
18
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CBM706P/706R/706S/706T/708R/708S/708T
OPERATION INSTRUCTION
PACKAGE/ORDERING INFORMATION
ORDERING
NUMBER
PAKEAGE
MARKING
TRANSPOT
PRODUCT
TEMPRANGE
PACKAGE
MEDIA,QUANTILY
CBM706PAS8
CBM705PMS8
CBM706RAS8
CBM706RMS8
CBM706SA8
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
-40℃~125℃
SOIC-8(SOP8)
MSOP-8
CBM706P
706PM
Tape and Reel,2500
Tape and Reel,3000
Tape and Reel,2500
Tape and Reel,3000
Tape and Reel,2500
Tape and Reel,3000
Tape and Reel,2500
Tape and Reel,3000
Tape and Reel,2500
Tape and Reel,3000
Tape and Reel,2500
Tape and Reel,3000
CBM706P
SOIC-8(SOP8)
MSOP-8
CBM706R
706RM
CBM706R
CBM706S
CBM706T
CBM708R
CBM708T
SOIC-8(SOP8)
MSOP-8
CBM706S
706SM
CBM706SM8
CBM706TS8
SOIC-8(SOP8)
MSOP-8
CBM706T
706TM
CBM708TMS8
CBM708RAS8
CBM708RMS8
CBM708TAS8
CBM708TMS8
SOIC-8(SOP8)
MSOP-8
CBM708R
708RM
SOIC-8(SOP8)
MSOP-8
CBM708T
708TM
19
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