CMF20120D [CREE]
Silicon Carbide Power MOSFET; 碳化硅功率MOSFET
| 型号： | CMF20120D |
| 厂家： | 
CREE, INC |
| 描述： | Silicon Carbide Power MOSFET |
| 文件： | 总13页 (文件大小：2291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMF20120D-Silicon Carbide Power MOSFET
1200V 80 mΩ
Z-FET™ MOSFET
N-Channel Enhancement Mode
Subject to change without notice.
www.cree.com/power
1
CMF20120D-Silicon Carbide Power MOSFET
VDS
= 1200 V
™
Z-FET MOSFET
N-Channel Enhancement Mode
RDS(on)
= 80 mΩ
ID(MAX)@TC=25°C = 33 A
Features
Package
D
•ꢀ Industry Leading RDS(on)
•ꢀ High Speed Switching
•ꢀ Low Capacitances
•ꢀ Easy to Parallel
•ꢀ Simple to Drive
•ꢀ Pb-Free Lead Plating, ROHS Compliant,
Halogen Free
G
S
TO-247-3
Benefits
•ꢀ HigherꢀSystemꢀEfficiency
•ꢀ Reduced Cooling Requirements
•ꢀ Avalanche Ruggedness
Part Number
Package
•ꢀ Increased System Switching Frequency
CMF20120D
TO-247-3
Applications
•ꢀ Solar Inverters
•ꢀ High Voltage DC/DC Converters
•ꢀ Motor Drives
Maximum Ratings
Symbol
Parameter
Value
Unit
Test Conditions
VGS@20V, TC =ꢀ25˚C
Note
33
17
Continuous Drain Current
A
ID
VGS@20V, TC =ꢀ100˚C
Pulse width tP limited by Tjmax
Pulsed Drain Current
78
A
IDpulse
EAS
TC =ꢀ25˚C
ID = 20A, VDD = 50 V,
L = 9.5 mH
Single Pulse Avalanche Energy
Repetitive Avalanche Energy
2.2
1.5
J
J
EAR
tAR limited by Tjmax
ID = 20A, VDD = 50 V, L = 3 mH
tAR limited by Tjmax
Repetitive Avalanche Current
20
A
IAR
Gate Source Voltage
-5/+25
150
V
VGS
Ptot
Power Dissipation
W
TC=25˚C
-55 to
+125
Operating Junction and Storage Temperature
Solder Temperature
˚C
˚C
TJ , Tstg
TL
260
1.6mm (0.063”) from case for 10s
M3 or 6-32 screw
1
8.8
Nm
lbf-in
Mounting Torque
Md
2
CMF20120D Rev. -
Table of Contents
Features.................................................................................................................2
Benefits...........................................................................................................2
Applications.....................................................................................................2
Maximum Ratings...................................................................................................2
Table of Contents....................................................................................................3
Applications Information........................................................................................4
ESD Ratings............................................................................................................7
Electrical Characteristics........................................................................................8
Reverse Diode Characteristics.................................................................................8
Thermal Characteristics..........................................................................................8
Gate Charge Characteristics....................................................................................8
TypicalPerformance..............................................................................................................9
ClampedInductiveSwitchTestingFixture..............................................................11
Package Dimensions.............................................................................................12
Recommended Solder Pad Layout..........................................................................13
Notice..............................................................................................................14
3
CMF20120D Rev. -
Applications Information
The Cree SiC MOSFET has removed the upper voltage limit of silicon MOSFETs.
However, there are some differences in characteristics when compared to what is
usually expected with high voltage silicon MOSFETs. These differences need to be
carefullyꢀaddressedꢀtoꢀgetꢀmaximumꢀbenefitꢀfromꢀtheꢀSiCꢀMOSFET.ꢀInꢀgeneral,ꢀ
although the SiC MOSFET is a superior switch compared to its silicon counterparts,
it should not be considered as a direct drop-in replacement in existing applications.
There are two key characteristics that need to be kept in mind when applying the
SiC MOSFETs: modest transconductance requires that VGS needs to be 20 V to
optimize performance. This can be see in the Output and Transfer Characteristics
shown in Figures 1-3. The modest transconductance also affects the transition
where the device behaves as a voltage controlled resistance to where it behaves as
a voltage controlled current source as a funtion of VDS. The result is that the
transition occurs over higher values of VDS than are usually experienced with Si
MOSFETs and IGBTs.
This might affect the operation anti-desaturation circuits,
especially if the circuit takes advantage of the device entering the constant current
region at low values of forward voltage.
The modest transconductance needs to be carefully considered in the design of the
gateꢀdriveꢀcircuit.ꢀTheꢀfirstꢀobviousꢀrequirementꢀisꢀthatꢀtheꢀgateꢀbeꢀcapable
of a >22 V (+20 V to -2V) swing. The recommended on state VGS is +20 V and the
recommended off state VGS is between -2 V to -5 V. Please carefully note that
although the gate voltage swing is higher than the typical silicon MOSFETs and
IGBTs, the total gate charge of the SiC MOSFET is considerably lower. In fact, the
product of gate voltage swing and gate charge for the SiC MOSFET is lower than
comparable silicon devices. The gate voltage must have a fast dV/dt to achieve
fast switching times which indicates that a very low impedance driver is necessary.
Lastly,ꢀtheꢀfidelityꢀofꢀtheꢀgateꢀdriveꢀpulseꢀmustꢀbeꢀcarefullyꢀcontrolled.ꢀTheꢀnominal
threshold voltage is 2.5V and the device is not fully on (dVDS/dt≈0) until the VGS is
above 16V. This is a noticeably wider range than what is typically experienced with
silicon MOSFETs and IGBTs. The net result of this is that the SiC MOSFET has a
somewhat lower ‘noise margin’. Any excessive ringing that is present on the gate
drive signal could cause unintentional turn-on or partial turn-off of the device. The
gate resistance should be carefully selected to ensure that the gate drive pulse is
adequatelyꢀdampened.ꢀToꢀfirstꢀorder,ꢀtheꢀgateꢀcircuitꢀcanꢀbeꢀapproximatedꢀasꢀaꢀ
simple series RLC circuit driven by a voltage pulse as shown below.
4
CMF20120D Rev. -
RLOOP CGATE
ζ =
≥1
RLOOP
LLOOP
2
LLOOP
VPULSE
CGATE
LLOOP
CGATE
∴ RLOOP ≥ 2
minimizes the value of
As shown, minimizing L
RLOOP needed for critical
LOOP
dampening. Minimizing LLOOP also minimizes the rise/fall time. Therefore, it is
strongly recommended that the gate drive be located as close to the SiC MOSFET
MOSFET
as possible to minimize LLOOP. The internal gate resistance of the SiC
is 5ꢀΩ.ꢀ
Anꢀexternalꢀresistanceꢀofꢀ6.8ꢀΩꢀwasꢀusedꢀtoꢀcharacterizeꢀthisꢀdevice.
Lowerꢀvaluesꢀofꢀexternalꢀgateꢀresistanceꢀcanꢀbeꢀusedꢀsoꢀlongꢀasꢀtheꢀgateꢀfidelityꢀisꢀ
maintained. In the event that no external gate resistance is used, it is suggested
that the gate current be checked to indirectly verify that there is no ringing present
in the gate circuit. This can be accomplished with a very small current transformer.
A recommended setup is a two-stage current transformer as shown below:
IG SENSE
VCC
GATE DRIVER
T1
SiC DMOSFET
GATEDRIVEINPUT
+
-
VEE
5
CMF20120D Rev. -
Stray inductance on source lead causes load
di/dt to be fed back into gate drive which
causes the following:
ꢀꢀKelvinꢀgateꢀconnectionꢀwithꢀseparate
ꢀꢀsourceꢀreturnꢀisꢀhighlyꢀrecommended
•ꢀ Switchꢀdi/dtꢀisꢀlimited
•ꢀ Couldꢀcauseꢀoscillation
LOAD CURRENT
20V
20V
R GATE
SiC DMOS
R GATE
ꢀꢀDRIVE
SiC DMOS
ꢀꢀDRIVE
LOAD CURRENT
L STRAY
L STRAY
A schematic of the gate driver circuit used for characterization of the SiC MOSFET
is shown below:
THESE COMPONENTS ARE
THESE COMPONENTS ARE
C1
LOCATED ON THE GND
+VCC
LOCATED ON THE -VEE
+VCC
10u
C2
PLANE
-VEE
-VEE
-VEE
-VEE
-VEE
-VEE
PLANE
100n
C4
C3
10u
GND
100n
C5
+VCC
C6
R1
1
C7
100n
C8
10u
+VCC
10u
C9
U1
LM2931T-5.0
-VEE
PIN 1 SOURCE
100n
C12
-VEE
1
3
IN
OUT
100n
C13
C10
C11
100u
6.3V
R2
100n
100n
390
10n
PULSEGENINPUT
J1
BNC
D1
ISO1
-VEE
R3
R4
PIN 2 GATE
1
2
3
8
U2
TBD 1206
R7
1
2
3
4
8
7
6
5
330
VCC
VCC
OUT
OUT
GND
RB160M-60
R5
120
R6
120
7
6
IN
TBD 1206
R8
NC
GND
C14
100n
D2
6N137
IXDI414
TBD 1206
-VEE
-VEE
RB160M-60
-VEE
C15
J2
BNC
100n
C16
-VEE
-VEE
-VEE
-VEE
-VEE
-VEE
1
VGS MONITOR
100n
C17
100n
C18
100n
C19
100n
C20
10u
The gate driver is an IXYS IXDI414. This device has a 35 V ouput swing, output
resistanceꢀofꢀ0.6ꢀΩꢀtypical,ꢀandꢀaꢀpeakꢀcurrentꢀcapabilityꢀofꢀ14ꢀA.ꢀTheꢀexternalꢀ
gateꢀresistanceꢀusedꢀforꢀcharacterizationꢀofꢀtheꢀSiCꢀMOSFETꢀwasꢀ6.8ꢀΩ.ꢀCarefulꢀ
consideration needs to be given to the selection of the gate driver. The typical
application error is selection of a gate driver that has adequate swing, but output
6
CMF20120D Rev. -
resistance and current drive capability are not carefully considered. It is critical that
the gate driver possess high peak current capability and low output resistance along
with adequate voltage swing.
AꢀsignificantꢀbenefitꢀofꢀtheꢀSiCꢀMOSFETꢀisꢀtheꢀeliminationꢀofꢀtheꢀtailꢀcurrentꢀobservedꢀ
in silicon IGBTs. However, it is very important to note that the current tail does
provide a certain degree of parasitic dampening during turn-off. Additional ringing and
overshoot is typically observed when silicon IGBTs are replaced with SiC MOSFETs. The
additional voltage overshoot can be high enough to destroy the device. Therefore, it
is critical to manage the output interconnection parasitics (and snubbers) to keep the
ringing and overshoot from becoming problematic.
ESD RATINGS
ESD Test
Total Devices Sampled
Resulting Classification
ESD-HBM
ESD-MM
ESD-CDM
All Devices Passed 1000V
All Devices Passed 400V
All Devices Passed 1000V
2 (>2000V)
C (>400V)
IV (>1000V)
7
CMF20120D Rev. -
Electrical Characteristics
Symbol
Parameter
Min.
Typ.
Max. Unit
Test Conditions
Note
V(BR)DSS
Drain-Source Breakdown Voltage
1200
V
VGS = 0V, IDꢀ=ꢀ100μA
2.5
1.8
1
4
VDS = VGS, ID = 1mA, TJ = 25ºC
VDS = VGS, ID = 1mA, TJ = 125ºC
VDS = 1200V, VGS = 0V, TJ = 25ºC
VDS = 1200V, VGS = 0V, TJ = 125ºC
VGS = 20V, VDS = 0V
VGS(th)
Gate Threshold Voltage
1
V
100
μA
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate-Source Leakage Current
Drain-Source On-State Resistance
10
250
250
110
130
nA
80
95
VGS = 20V, ID = 20A, TJ = 25ºC
VGS = 20V, ID = 20A, TJ = 125ºC
VDS= 20V, IDS= 20A, TJ = 25ºC
VDS= 20V, IDS= 20A, TJ = 125ºC
RDS(on)
mΩ
7.3
6.8
1915
gfs
Transconductance
S
fig.ꢀ3
fig.ꢀ5
Ciss
Input Capacitance
Output Capacitance
VGS = 0V
Coss
120
VDS = 800V
pF
f = 1MHz
Crss
Reverse Transfer Capacitance
13
AC
V
= 25mV
td(on)i
tr
td(off)i
tfi
Turn-On Delay Time
Rise Time
17.2
13.6
62
VDD = 800V
VGS = -2/20V
ID = 20A
ns
Turn-Off Delay Time
Fall Time
fig.ꢀ12
35.6
RGꢀ=ꢀ6.8Ω
530
422
(25ºC)
EON
Turn-On Switching Loss
Turn-Off Switching Loss
μJ
L = 856μH
(
125ºC)
Per JEDEC24 Page 27
320
329
(25ºC)
EOff
μJ
Ω
(
125ºC)
,
VGS = 0V, f = 1MHz VAC = 25mV
RG
Internal Gate Resistance
5
NOTES: 1. The recommended on-state V
VGS is between -2V and -5V
is +20V and the recommended off-state
GS
Reverse Diode Characteristics
Symbol Parameter
Typ.
Max.
Unit
Test Conditions
Note
=
VGS = -5V, IF 10A, TJ = 25ºC
3.5
3.1
220
142
2.3
Vsd
Diode Forward Voltage
V
=
VGS = -2V, IF 10A, TJ = 25ºC
trr
Reverse Recovery Time
ns
nC
A
=
VGS = -5V, IF 20A, TJ = 25ºC
VR = 800V,
diF/dt=ꢀ100A/μs
Qrr
Irrm
Reverse Recovery Charge
Peak Reverse Recovery Current
fig.ꢀ13,14
Thermal Characteristics
Symbol Parameter
Typ.
Max.
Unit
Test Conditions
Note
RθJC
RθCS
Thermal Resistance from Junction to Case
Case to Sink, w/ Thermal Compound
0.58
0.25
0.7
°C/W
fig.ꢀ6
RθJA
Thermal Resistance From Junction to Ambient
40
Gate Charge Characteristics
Symbol Parameter
Typ.
Max.
Unit
Test Conditions
Note
Qgs
Qgd
Qg
Gate to Source Charge
Gate to Drain Charge
Gate Charge Total
23.8
43.1
90.8
VDD = 800V
ID =20A
VGS = -2/20V
fig.9
nC
Per JEDEC24-2
8
CMF20120D Rev. -
Typical Performance
40
40
=10V
V
VGS=10V
Fig 1. Typical Output Characteristics TJ = 25ºC
Fig 2. Typical Output Characteristics TJ = 125ºC
T= 125°C
VGS=20V
T= 25°C
Figure 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
VGS = 0 V
f = 1 MHz
VGS = 0 V
f = 1 MHz
Ciss
Ciss
Coss
Coss
Crss
Crss
DS
DS
Fig 5A and 5B. Typical Capacitance vs. Drain – Source Voltage
9
CMF20120D Rev. -
Typical Performance
Fig 6. Transient Thermal Impedence, Junction - Case
VGS= -2/20V
RG= 11.8ΩꢀTotal
VDD= 800V
ID= 20A
VGS= -2/20V
RG= 11.8ΩꢀTotal
VDD= 800V
ID= 20A
Fig 8. Inductive Switching Energy(Turn-off) vs. T
Fig 7. Inductive Switching Energy(Turn-on) vs. T
VDS
IDS
ID=20A
VDD=800V
EAS = 2.20 J
Fig 10. Typical Avalanche Waveform
Fig 9. Typical Gate Charge Characteristics @ 25°C
CMF20120D Rev. -
10
Clamped Inductive Switch Testing Fixture
t
w
pulse duration
V
GS(on)
90%
90%
Input (V )
i
50%
50%
10%
10%
V
GS(off)
C2D10120D
Input Pulse
Fall Time
Input Pulse
Rise Time
10A, 1200V
SiC Schottky
856μH
+
-
800V
42.3μf
t
t
t
t
fi
ri
d(off)i
d(on)i
i
D(on)
CMF20120D
D.U.T.
10%
10%
Output (i
)
D
90%
90%
i
D(off)
t
off(i)
t
on(i)
Fig 11. Switching Waveform Test Circuit
Fig 12. Switching Test Waveform Times
trr
id dt
tx
t
rr
Qrr=
∫
Ic
tx
10% Irr
856μH
CMF20120D
D.U.T.
V
cc
10% V
Irr
cc
Vpk
+
-
800V
42.3μf
Diode Recovery
Waveforms
CMF20120D
t2
id dt
t1
Erec=
Diode Reverse
Recovery Energy
∫
t1
t2
Fig 14. Body Diode Recovery Test
Fig 13. Body Diode Recovery Waveform
11
CMF20120D Rev. -
2
EA = 1/2L x ID
Fig 16. Theoretical Avalanche Waveform
Fig 15. Avalanche Test Circuit
Package Dimensions
Package TO-247-3
Inches
POS
Millimeters
Min
Min
.190
.090
.075
.042
.075
.075
.113
.113
.022
.819
.640
.037
.620
.516
.145
.039
.487
Max
.205
.100
.085
.052
.095
.085
.133
.123
.027
.831
.695
.049
.635
.557
.201
.075
.529
Max
5.21
2.54
2.16
1.33
2.41
2.16
3.38
3.13
0.68
21.10
17.65
1.25
16.13
14.15
5.10
1.90
13.43
A
A1
A2
b
4.83
2.29
1.91
1.07
1.91
1.91
2.87
2.87
0.55
20.80
16.25
0.95
15.75
13.10
3.68
1.00
12.38
b1
b2
b3
b4
c
D
D1
D2
E
E1
E2
E3
E4
e
.214 BSC
5.44 BSC
N
3
3
D
L
.780
.161
.138
.216
.238
.800
.173
.144
.236
.248
19.81
4.10
3.51
5.49
6.04
20.32
4.40
3.65
6.00
6.30
L1
ØP
Q
S
G
S
12
CMF20120D Rev. -
Recommended Solder Pad Layout
TO-247-3
Part Number
CMF20120D
Package
TO-247-3
“The levels of environmentally sensitive, persistent biologically toxic (PBT), persistent organic pollutants (POP), or otherwise restricted materials in this product are below the
maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive
2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS), as amended through April 21, 2006.
This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body
nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited
toꢀequipmentꢀusedꢀinꢀtheꢀoperationꢀofꢀnuclearꢀfacilities,ꢀlife-supportꢀmachines,ꢀcardiacꢀdefibrillatorsꢀorꢀsimilarꢀemergencyꢀmedicalꢀ
equipment,ꢀaircraftꢀnavigationꢀorꢀcommunicationꢀorꢀcontrolꢀsystems,ꢀairꢀtrafficꢀcontrolꢀsystems,ꢀorꢀweaponsꢀsystems.
Cree, Inc.
4600 Silicon Drive
Durham, NC 27703
USA Tel: +1.919.313.5300
Fax: +1.919.313.5451
www.cree.com/power
Copyright © 2010-2011 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree,
the Cree logo, Z-REC and Z-FET are registered trademarks of Cree, Inc.
13
CMF20120D Rev. -
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