CCLD-054X-20-622.080 [CRYSTEKMICROWAVE]
LVDS Clock Oscillator; LVDS时钟振荡器
| 型号： | CCLD-054X-20-622.080 |
| 厂家： | 
CRYSTEK CORPORATION |
| 描述： | LVDS Clock Oscillator |
| 文件： | 总3页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCLD-054X-20-622.080
LVDS Clock Oscillator
Model CCLD-054X is a 622.080Mhz LVDS Clock Oscillator
operating at 3.3Volts. Enable/Disable function used for
system testing is offered as a standard feature.
Operating Temperature is from -40 to +85C with +/-20PPM
Frequency Stability.
Applications:
5x7mm SMD
Digital Video
SONET/SDH/DWDM
Storage Area Networks
Broadband Access
Ethernet, Gigabit Ethernet
Rev.: B
Date: 10-10-07
CCLD-054X-20-622.080
LVDS Clock Oscillator
Performance Specification
Nominal Frequency:
Frequency Stability
Min.
Typ.
622.08
Max
Units
MHz
ppm
±20
Output Phase Noise
@1KHz Offset
-100
-125
-138
-140
-142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10KHz Offset
@100KHz Offset
@1MHz Offset
@10MHz Offset
dBc/Hz
pS,RMS
Jitter: 12KHz-20MHz
2
Differential Clock Rise Time
Differential Clock Fall Time
Output High Voltage, VOH
Output Low Voltage, VOL
Differential Output
0.2
0.5
0.5
0.7
0.7
1.60
nSec
nSec
V
0.2
1.40
1.10
330
0.90
247
V
454
50
VOD
mV
pSec
uA
Differential Output Error
Differential Output Skew
Output Leakage Current
200
±10
Output Load (differential)
Enable High Voltage, VIH
Disable Low Voltage, VIL
Output Enable/Disable Tiime
Duty Cycle @ 1.25V(LVDS)
Offset Voltage
100
Ohms
V
0.7*VCC
GND
VCC
0.3*VCC
400
V
nSec
%
45
1.125
0
50
1.2
3
55
1.375
25
V
Offset Error
V
Supply Voltage
3.15
3.3
3.45
80
V
Supply Current, Icc Enabled
Supply Current, Icc Disabled
Operating Temp.
mA
uA
°C
°C
10
-40
-45
+85
Storage Temp.
+90
Parameter
Conditions
MIL-STD-883, Method 2002
Mechanical Shock
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 2003
Resistance to Solvents MIL-STD-883, Method 2016
Rev.: B
Date: 10-10-07
CCLD-054X-20-622.080
LVDS Clock Oscillator
0.274 ±0.007
(6.96 ±0.18)
CCLD054X20
622.08M
DC Lot Code
0.193 ±0.007
(4.90 ±0.18)
0.045 ±0.008
Pad Connection
(1.14 ±0.20)
SUGGESTED PAD LAYOUT
1
2
3
4
5
6
Enable/Disable
N/C
Denotes pad 1
0.050
(1.27)
via to
ground
GND
0.055 Typ
(1.40 Typ)
0.01µF
Out
0.045 ±0.008
(1.14 ±0.20)
6
1
5
2
4
3
Comp. Out
VCC
#1
#6
#2
#5
#3
#4
0.154
(3.91)
0.071
(1.80)
0.100
(2.54)
0.100
(2.54)
0.200
(5.08)
0.200
(5.08)
LVDS Test Circuit
RECOMMENDED REFLOW SOLDERING PROFILE
Ramp-Up
Critical
OUT
3°C/Sec Max.
Temperature Zone
260°C
Ramp-Down
6°C/Sec.
217°C
50ȍ
200°C
150°C
VOD
VOS
50ȍ
Preheat
90 Secs. Max.
180 Secs. Max.
8 Minutes Max.
260°C for
OUT
10 Secs. Max.
NOTE: Reflow Profile with 240°C peak also acceptable.
Rev.: B
Date: 10-10-07
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