637E15365I3T [CTS]
LVPECL Output Clock Oscillator,;
| 型号： | 637E15365I3T |
| 厂家： | 
CTS |
| 描述： | LVPECL Output Clock Oscillator, 机械 输出元件 振荡器 |
| 文件： | 总8页 (文件大小：905K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Model 637
Very Low Jitter LVPECL or LVDS Clock
Features
. Ceramic Surface Mount Package
. Very Low Phase Jitter Performance, 500fs Maximum
. Fundamental or 3rd Overtone Crystal Design
. Frequency Range 10 – 320MHz *
. +2.5V or +3.3V Operation
Part Dimensions:
7.0 × 5.0 × 2.0mm • 178.462mg
. Output Enable Standard
. Tape and Reel Packaging, EIA‐418
Standard Frequencies
‐ 25.00MHz
‐ 50.00MHz
‐ 100.00MHz
‐ 125.00MHz
‐ 155.52MHz
‐ 156.25MHz
‐ 161.1328MHz
‐ 187.50MHz
‐ 200.00MHz
‐ 212.50MHz
‐ 250.00MHz
‐ 312.50MHz
Applications
. SerDes
. PON
. Storage Area Networking
. Broadband Access
. SONET/SDH/DWDM
. Ethernet/GbE/SyncE
. Fiber Channel
. Test and Measurement
* Check with factory for availability.
Description
CTS Model 637 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs.
Employing the latest IC technology, M637 has excellent stability and low jitter/phase noise performance.
Ordering Information
Frequency
Stability
3
Temperature
Supply
Voltage
3
Frequency Code
[MHz]
Output Type
Packaging
T
Model
Range
I
637
P
XXX or XXXX
Output
Stability
Voltage
+2.5Vdc
+3.3Vdc
Code
P
L
E
V
Code
Code
2
3
±20ppm 2
±25ppm
±50ppm
±100ppm
LVPECL ‐ Pin 1 Enable
LVDS ‐ Pin 1 Enable
LVPECL ‐ Pin 2 Enable
LVDS ‐ Pin 2 Enable
6
5
3
2
Frequency
Product Frequency Code 1
Temp. Range
‐10°C to +60°C
‐20°C to +70°C
‐40°C to +85°C
Packing
1k pcs./reel
Code
Code
Code
T
A
C
I
Notes:
1] Refer to document 016‐1454‐0, Frequency Code Tables. 3‐digits for frequencies <100MHz, 4‐digits for frequencies 100MHz or greater.
Consult factory for availability of 6I Stability/Temperature combination.
2]
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
DOC# 008‐0453‐0 Rev. B
Page 1 of 8
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 637
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
‐0.5
TYP
‐
MAX
5.0
UNIT
V
Maximum Supply Voltage
VCC
‐
2.375
3.135
2.5
3.3
2.625
3.465
Supply Voltage
VCC
±5%
V
Supply Current
LVPECL
ICC
Maximum Load
‐
55
45
88
66
mA
LVDS
‐
‐20
‐40
‐40
+70
+85
+125
Operating Temperature
Storage Temperature
TA
‐
‐
+25
°C
°C
TSTG
‐
Frequency Stability
PARAMETER
Frequency Range
LVPECL
SYMBOL
fO
CONDITIONS
MIN
TYP
MAX
UNIT
MHz
‐
10 ‐ 320
10 ‐ 320
LVDS
Frequency Stability
Δf/fO
‐
20, 25, 50 or 100
±ppm
ppm
[Note 1]
Aging
Δf/f25
First Year @ +25°C, nominal VCC
‐3
‐
3
1.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
Output Parameters
PARAMETER
Output Type
Output Load
SYMBOL
‐
CONDITIONS
MIN
TYP
MAX
UNIT
‐
LVPECL
‐
RL
Terminated to VCC ‐ 2.0V
‐
50
‐
Ohms
VOH
VCC ‐ 1.025
VCC ‐ 1.810
VCC ‐ 1.085
VCC ‐ 1.830
45
‐
VCC ‐ 0.880
VCC ‐ 1.620
VCC ‐ 0.880
VCC ‐ 1.555
55
PECL Load, ‐20°C to +70°C
PECL Load, ‐40°C to +85°C
V
V
VOL
‐
‐
Output Voltage Levels
VOH
VOL
‐
Output Duty Cycle
Rise and Fall Time
SYM
TR, TF
@ VCC ‐ 1.3V
‐
%
@ 20%/80% Levels, RL = 50 Ohms
‐
0.3
0.7
ns
LVDS
100
1.43
1.10
‐
Output Type
Output Load
‐
‐
‐
RL
Between Outputs
‐
‐
‐
1.60
‐
Ohms
VOH
VOL
Output Voltage Levels
LVDS Load
V
0.90
45
Output Duty Cycle
Differential Output Voltage
Offset Voltage
SYM
VOD
VOS
TR, TF
@ 1.25V
RL = 100 Ohms
55
%
mV
V
247
1.125
‐
330
1.25
0.4
454
1.375
0.7
LVDS Load
Rise and Fall Time
@ 20%/80% Levels, RL = 100 Ohms
ns
DOC# 008‐0453‐0 Rev. B
Page 2 of 8
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 637
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Output Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2
MAX
5
UNIT
ms
Start Up Time
TS
Application of VCC
‐
Enable Function [Standby]
Enable Input Voltage
Disable Input Voltage
Disable Time
VIH
VIL
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
Bandwidth 12 kHz ‐ 20 MHz
‐
0.7VCC
‐
‐
‐
V
V
‐
‐
‐
‐
‐
‐
0.3VCC
TPLZ
‐
200
ns
ms
fs
Enable Time
TPLZ
‐
2
Phase Jitter, RMS
Period Jitter, pk‐pk
Period Jitter, RMS
tjrms
pjpk‐pk
pjrms
300
2.6
25
500
‐
‐
ps
ps
‐
Enable Truth Table
Pin 1 or Pin 2
Logic ‘1’
Open
Pin 4 & Pin 5
Output
Output
Logic ‘0’
High Imp.
Test Circuit
LVPECL
LVDS
Output Waveform
LVPECL or LVDS
DOC# 008‐0453‐0 Rev. B
Page 3 of 8
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 637
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
25MHz, LVPECL, VCC = 3.3V, TA = +25°C
100MHz, LVPECL, VCC = 3.3V, TA = +25°C
DOC# 008‐0453‐0 Rev. B
Page 4 of 8
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 637
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
312.50MHz, LVPECL, VCC = 3.3V, TA = +25°C
155.52MHz, LVDS, VCC = 3.3V, TA = +25°C
DOC# 008‐0453‐0 Rev. B
Page 5 of 8
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 637
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Phase Noise Tabulated
Typical, VCC = 3.3V, TA = +25°C
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
LVPECL @ 25.00MHz
Phase Noise
LVPECL @ 100.00MHz
Phase Noise
Single Side Band
Single Side Band
@ 10Hz
‐75.14
‐112.50
‐142.15
‐155.01
‐159.99
‐161.83
‐161.61
@ 10Hz
‐65.65
‐100.19
‐131.02
‐145.49
‐150.36
‐151.37
‐152.11
@ 100Hz
@ 1kHz
@ 100Hz
@ 1kHz
‐
dBc/Hz
‐
dBc/Hz
@ 10kHz
@ 100kHz
@ 1MHz
@ 5MHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 5MHz
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 179.24
fs
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 132.20
fs
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
LVPECL @ 312.20MHz
Phase Noise
LVDS @ 155.52MHz
Phase Noise
Single Side Band
Single Side Band
@ 10Hz
‐65.93
‐95.92
@ 10Hz
‐69.89
‐103.42
‐130.99
‐142.69
‐144.46
‐144.49
‐145.13
@ 100Hz
@ 1kHz
@ 100Hz
@ 1kHz
‐128.25
‐130.51
‐142.82
‐142.84
‐143.80
‐
dBc/Hz
‐
dBc/Hz
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 20MHz
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 208.52
fs
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 383.70
fs
DOC# 008‐0453‐0 Rev. B
Page 6 of 8
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 637
Very Low Jitter LVPECL or LVDS Clock
Mechanical Specifications
Package Drawing
Marking Information
1. ** ‐ Manufacturing Site Code.
2. YYWW – Date Code; YY – year, WW – week.
3. O – Output Type; P or E = LVPECL, L or V = LVDS.
4. ST – Frequency Stability/Temperature Code.
[Refer to Ordering Information]
5. V – Voltage Code; 3 = 3.3V, 2 = 2.5V.
6. xxxx – Frequency Code.
CTS**YYWW
637OSTV
● xxxx
3‐digits, frequencies below 100MHz
4‐digits, frequencies 100MHz or greater
[See document 016‐1454‐0, Frequency Code Tables.]
Recommended Pad Layout
Notes
1. JEDEC termination code (e4). Barrier‐plating is
nickel [Ni] with gold [Au] flash plate.
2. Reflow conditions per JEDEC J‐STD‐020; +260°C
maximum, 20 seconds.
3. MSL = 1.
Pin Assignments
Pin
Symbol
EOH or N.C.
N.C. or EOH
GND
Function
1
Enable [std] or No Connect
No Connect or Enable [opt]
Circuit & Package Ground
RF Output
2
3
4
Output
5
Output
Complimentary RF Output
Supply Voltage
6
VCC
DOC# 008‐0453‐0 Rev. B
Page 7 of 8
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 637
Very Low Jitter LVPECL or LVDS Clock
Packaging ‐ Tape and Reel
Tape Drawing
Reel Drawing
Notes
1. Device quantity is 1k pieces maximum per 180mm reel.
2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels.
DOC# 008‐0453‐0 Rev. B
Page 8 of 8
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
相关型号：
©2020 ICPDF网 联系我们和版权申明