638L17005I3T [CTS]
LVDS Output Clock Oscillator;
| 型号： | 638L17005I3T |
| 厂家： | 
CTS |
| 描述： | LVDS Output Clock Oscillator 机械 输出元件 振荡器 |
| 文件： | 总7页 (文件大小：707K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Model 638
Ultra Low Jitter LVPECL or LVDS Clock
Features
. Ceramic Surface Mount Package
. Ultra Low Phase Jitter Performance, 100fs Typical
. Fundamental or 3rd Overtone Crystal Design
. Frequency Range 80 – 170MHz *
. +2.5V or +3.3V Operation
Part Dimensions:
7.0 × 5.0 × 2.0mm • 178.462mg
. Output Enable Standard
. Tape and Reel Packaging, EIA‐418
Standard Frequencies, 100fs Maximum
‐ 125.00MHz
‐ 155.52MHz
‐ 156.25MHz
‐ 161.1328MHz
Applications
. SerDes
. PON
. Ethernet/GbE/SyncE
. Fiber Channel
* Check with factory for availability.
. Storage Area Networking
. Broadband Access
. SONET/SDH/DWDM
. Test and Measurement
Description
CTS Model 638 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs.
Employing the latest IC technology, M638 has excellent stability and low jitter/phase noise performance.
Ordering Information
Frequency
Stability
3
Temperature
Supply
Voltage
3
Frequency Code
[MHz]
Output Type
Packaging
T
Model
Range
I
638
P
XXX or XXXX
Output
Stability
Voltage
+2.5Vdc
+3.3Vdc
Code
P
L
E
V
Code
Code
2
3
±20ppm 2
±25ppm
±50ppm
±100ppm
LVPECL ‐ Pin 1 Enable
LVDS ‐ Pin 1 Enable
LVPECL ‐ Pin 2 Enable
LVDS ‐ Pin 2 Enable
6
5
3
2
Frequency
Product Frequency Code 1
Temp. Range
‐10°C to +60°C
‐20°C to +70°C
‐40°C to +85°C
Packing
1k pcs./reel
Code
Code
Code
T
A
C
I
Notes:
1] Refer to document 016‐1454‐0, Frequency Code Tables. 3‐digits for frequencies <100MHz, 4‐digits for frequencies 100MHz or greater.
Consult factory for availability of 6I Stability/Temperature combination.
2]
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
DOC# 008‐0539‐0 Rev. A
Page 1 of 7
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 638
Ultra Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
‐0.5
TYP
‐
MAX
5.0
UNIT
V
Maximum Supply Voltage
VCC
‐
2.375
3.135
2.5
3.3
2.625
3.465
Supply Voltage
VCC
±5%
V
Supply Current
LVPECL
ICC
Maximum Load
‐
55
45
88
66
mA
LVDS
‐
‐20
‐40
‐40
+70
+85
+125
Operating Temperature
Storage Temperature
TA
‐
‐
+25
°C
°C
TSTG
‐
Frequency Stability
PARAMETER
Frequency Range
LVPECL
SYMBOL
fO
CONDITIONS
MIN
TYP
MAX
UNIT
MHz
‐
80 ‐ 170
80 ‐ 170
LVDS
Frequency Stability
Δf/fO
‐
20, 25, 50 or 100
±ppm
ppm
[Note 1]
Aging
Δf/f25
First Year @ +25°C, nominal VCC
‐3
‐
3
1.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
Output Parameters
PARAMETER
Output Type
Output Load
SYMBOL
‐
CONDITIONS
MIN
TYP
MAX
UNIT
‐
LVPECL
‐
RL
Terminated to VCC ‐ 2.0V
‐
50
‐
Ohms
VOH
VCC ‐ 1.025
VCC ‐ 1.810
VCC ‐ 1.085
VCC ‐ 1.830
45
‐
VCC ‐ 0.880
VCC ‐ 1.620
VCC ‐ 0.880
VCC ‐ 1.555
55
PECL Load, ‐20°C to +70°C
PECL Load, ‐40°C to +85°C
V
V
VOL
‐
Output Voltage Levels
VOH
‐
‐
VOL
Output Duty Cycle
Rise and Fall Time
SYM
TR, TF
@ VCC ‐ 1.3V
‐
%
@ 20%/80% Levels, RL = 50 Ohms
‐
0.3
0.7
ns
LVDS
100
1.43
1.10
‐
Output Type
Output Load
‐
‐
‐
RL
Between Outputs
‐
‐
‐
1.60
‐
Ohms
VOH
VOL
Output Voltage Levels
LVDS Load
V
0.90
45
Output Duty Cycle
Differential Output Voltage
Offset Voltage
SYM
VOD
VOS
TR, TF
@ 1.25V
RL = 100 Ohms
55
%
mV
V
247
1.125
‐
330
1.25
0.4
454
1.375
0.7
LVDS Load
Rise and Fall Time
@ 20%/80% Levels, RL = 100 Ohms
ns
DOC# 008‐0539‐0 Rev. A
Page 2 of 7
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 638
Ultra Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Output Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2
MAX
5
UNIT
ms
Start Up Time
TS
Application of VCC
‐
Enable Function [Standby]
Enable Input Voltage
Disable Input Voltage
Disable Time
VIH
VIL
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
80 ‐ 124.9MHz, Bandwidth 12 kHz ‐ 20 MHz
125 ‐ 170MHz, Bandwidth 12 kHz ‐ 20 MHz
‐
0.7VCC
‐
‐
‐
0.3VCC
200
2
V
V
‐
‐
‐
‐
TPLZ
TPLZ
‐
ns
ms
fs
Enable Time
‐
‐
200
100
‐
Phase Jitter, RMS
tjrms
‐
fs
Period Jitter, pk‐pk
pjpk‐pk
‐
‐
2.6
25
ps
ps
Period Jitter, RMS
pjrms
‐
‐
Enable Truth Table
Pin 1 or Pin 2
Logic ‘1’
Open
Pin 4 & Pin 5
Output
Output
Logic ‘0’
High Imp.
Test Circuit
LVPECL
LVDS
Output Waveform
LVPECL or LVDS
DOC# 008‐0539‐0 Rev. A
Page 3 of 7
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 638
Ultra Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
125.00MHz, LVPECL, VCC = 3.3V, TA = +25°C
156.25MHz, LVPECL, VCC = 3.3V, TA = +25°C
DOC# 008‐0539‐0 Rev. A
Page 4 of 7
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 638
Ultra Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
156.25MHz, LVDS, VCC = 3.3V, TA = +25°C
Phase Noise Tabulated
Typical, VCC = 3.3V, TA = +25°C
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
LVPECL @ 125.00MHz
Phase Noise
LVPECL @ 156.25MHz
Phase Noise
Single Side Band
Single Side Band
@ 10Hz
‐79.62
‐107.25
‐135.31
‐146.45
‐151.59
‐152.31
‐153.73
@ 10Hz
‐75.60
‐103.54
‐132.26
‐149.09
‐155.26
‐155.33
‐158.39
@ 100Hz
@ 1kHz
@ 100Hz
@ 1kHz
‐
dBc/Hz
‐
dBc/Hz
@ 10kHz
@ 100kHz
@ 1MHz
@ 5MHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 20MHz
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 89.77
fs
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 77.86
fs
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
LVDS @ 156.25MHz
Phase Noise
Single Side Band
@ 10Hz
‐71.41
‐103.93
‐128.68
‐145.73
‐155.28
‐154.78
‐157.92
@ 100Hz
@ 1kHz
‐
dBc/Hz
@ 10kHz
@ 100kHz
@ 1MHz
@ 20MHz
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 82.99
fs
DOC# 008‐0539‐0 Rev. A
Page 5 of 7
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 638
Ultra Low Jitter LVPECL or LVDS Clock
Mechanical Specifications
Package Drawing
Marking Information
1. ** ‐ Manufacturing Site Code.
2. YYWW – Date Code; YY – year, WW – week.
3. O – Output Type; P or E = LVPECL, L or V = LVDS.
4. ST – Frequency Stability/Temperature Code.
[Refer to Ordering Information]
5. V – Voltage Code; 3 = 3.3V, 2 = 2.5V.
6. xxxx – Frequency Code.
CTS**YYWW
638OSTV
● xxxx
3‐digits, frequencies below 100MHz
4‐digits, frequencies 100MHz or greater
[See document 016‐1454‐0, Frequency Code Tables.]
Recommended Pad Layout
Notes
1. JEDEC termination code (e4). Barrier‐plating is
nickel [Ni] with gold [Au] flash plate.
2. Reflow conditions per JEDEC J‐STD‐020; +260°C
maximum, 20 seconds.
3. MSL = 1.
Pin Assignments
Pin
Symbol
EOH or N.C.
N.C. or EOH
GND
Function
1
Enable [std] or No Connect
No Connect or Enable [opt]
Circuit & Package Ground
RF Output
2
3
4
Output
5
Output
Complimentary RF Output
Supply Voltage
6
VCC
DOC# 008‐0539‐0 Rev. A
Page 6 of 7
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 638
Ultra Low Jitter LVPECL or LVDS Clock
Packaging ‐ Tape and Reel
Tape Drawing
Reel Drawing
Notes
1. Device quantity is 1k pieces maximum per 180mm reel.
2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels.
DOC# 008‐0539‐0 Rev. A
Page 7 of 7
©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
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