DFVS8-MLECPI693.4828MHZ100B50 [CTS]
LVPECL 100K Output Clock Oscillator, 693.4828MHz Nom,;
| 型号： | DFVS8-MLECPI693.4828MHZ100B50 |
| 厂家： | 
CTS |
| 描述： | LVPECL 100K Output Clock Oscillator, 693.4828MHz Nom, |
| 文件： | 总1页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FREQUENCY CONTROL PRODUCTS
H I G H F R E Q U E N C Y S U R F A C E M O U N T V C X O
D F V S 8 - M L E C P I ( 3 . 3 V )
19.8±0.3
15.24
KEY FEATURES
622 to 800 MHz
Parametric frequency multiplication
0.4 ps RMS jitter over 50 kHz to 80 MHz B.W.
APPLICATIONS
1.27
18.4
2.54
OC-192/Sonet/SDH
H = 9.30 mm
Function
V control
E / D
DFV S8
15.24
1
6
14
1
9 8
6 7
PC board footprint
GND
7
Output 1
Output 2
Vcc
8
9
14
1.3
2.54
TYPE
DFV S8-MLECPI
Frequency Range
Standard Frequencies
622 to 800 MHz
622.0800; 644.5313; 666.5143; 669.3266; 693.4828; 777.6000 MHz
ELECTRICAL SPECIFICATIONS
supply voltage
3.3 V ± 5 %
supply current (no load)
≤ 60 mA
output load
LVPECL 100 K ( 50 Ω to 1.3 V )
45/55...55/45 %
duty cycle @ 50% level
rise/fall times ( 20 to 80% )
high/low levels
≤ 0.5 ns
≥ 2.22 V/ ≤ 1.7 V
jitter RMS ( 12 kHz to 5 MHz )
jitter RMS ( 12 kHz to 20 MHz )
jitter RMS ( 50 kHz to 80 MHz )
0.08 ps typ; ≤ 0.10 ps
0.12 ps typ; ≤ 0.15 ps
0.32 ps typ; ≤ 0.40 ps
enable / disable on pin 6
low or open = enable, high = disable
complementary output on pin 9
start up
180° phase shifted
≤ 10 ms @ 3.15 V
FREQUENCY STABILITY
detailed tolerances [ ppm ]
temperature model
type
stability versus:
@ 25°C Vcc
pulling range
control
voltage
range
code
temp.
≤ ± 20
≤ ± 25
≤ ± 50
≤ ± 30
load ageing positive function
100B20
100B25
100B50
0 to 70°C
DFV S8-MLECPI
remarks
≤ ± 10
≤ ± 3 ≤ ± 0.5 ≤ ± 2
≥ ± 100
1.65 V ± 1.35 V
-40 to 85°C 100E30
input impedance ≥ 10 kΩ,
modulation bandwidth ≥ 10 kHz @ -3dB
ageing is 1st year at 25°C
ORDERING CODE
type + option code + frequency + model code
Example
DFV S8-MLECPI 622.08 MHz 100B20
TYPE
DFV S8-MLECPI
REVISION
03
CHECKED
MYP
DATE
27.06.2002
PAGE
34
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