5962-8866204NA [CYPRESS]
Standard SRAM, 32KX8, 45ns, CMOS, CDIP28, 0.300 INCH, CERDIP-28;
| 型号： | 5962-8866204NA |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 32KX8, 45ns, CMOS, CDIP28, 0.300 INCH, CERDIP-28 CD 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
fax id: 1030
CY7C199
32K x 8 Static RAM
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power consump-
tion by 81% when deselected. The CY7C199 is in the standard
300-mil-wide DIP, SOJ, and LCC packages.
Features
• High speed
— 10 ns
• Fast t
DOE
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
• CMOS for optimum speed/power
• Low active power
are both LOW, data on the eight data input/output pins (I/O
0
— 467 mW (max, 12 ns “L” version)
• Low standby power
through I/O ) is written into the memory location addressed by
7
the address present on the address pins (A through A ).
0
14
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Functional Description
The CY7C199 is a high-performance CMOS static RAM orga-
nized as 32,768 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP / SOJ / SOIC
Top View
LCC
Top View
A
A
V
CC
28
27
26
5
1
2
3
4
5
6
WE
6
3
2 1 2827
26
A
A
A
4
7
4
A
4
A
A
8
9
8
A
3
25
24
5
6
7
8
25
24
23
22
21
20
19
18
A
3
A
9
A
2
A
A
10
2
A
10
A
11
23
22
A
1
A
11
A
1
A
12
OE
7
OE
A
9
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
A
A
I/O
I/O
I/O
A
21
20
19
18
17
16
15
12
13
14
A
0
0
1
2
3
4
5
6
0
8
9
10
11
12
13
A
10
11
12
14
INPUT BUFFER
CE
I/O
I/O
CE
I/O
I/O
I/O
I/O
I/O
0
7
6
7
1
A
0
0
1
2
6
5
4
1314151617
A
1
C199–3
A
2
I/O
I/O
A
3
GND
14
3
A
4
C199–2
1024 x 32 x 8
ARRAY
A
5
22
OE
A
A
A
0
21
6
23
24
1
A
20
CE
I/O
I/O
6
I/O
5
I/O
I/O
GND
7
A
A
A
2
3
4
A
19
18
17
16
8
A
7
25
26
27
28
1
9
TSOP I
Top View
(not to scale)
WE
4
3
CE
WE
V
CC
A
A
15
14
13
POWER
DOWN
COLUMN
DECODER
5
6
7
2
3
I/O
2
A
A
A
I/O
7
12
11
I/O
I/O
A
1
0
OE
4
5
8
9
C199–1
10
9
14
A
6
7
10
A
A
13
12
A
11
8
C199–4
Selection Guide
7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45
Maximum Access Time (ns)
Maximum Operating
8
10
110
90
12
160
90
15
155
90
20
150
90
25
150
80
35
140
70
45
120
140
Current (mA)
L
Maximum CMOS
0.5
0.5
10
10
10
10
10
10
Standby Current (mA)
L
0.05
0.05
0.05
0.05
0.05
0.05
Shaded area contains preliminary information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 1988 – Revised April 22, 1998
CY7C199
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
[2]
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)........................................... –0.5V to +7.0V
Range
Commercial
Industrial
Military
Ambient Temperature
0°C to +70°C
V
CC
5V ± 10%
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
[1]
–40°C to +85°C
–55°C to +125°C
in High Z State ....................................–0.5V to V + 0.5V
CC
[1]
DC Input Voltage .................................–0.5V to V + 0.5V
CC
[3]
Electrical Characteristics Over the Operating Range
7C199-8
7C199-10
7C199-12
7C199-15
Parameter
Description
Test Conditions
=Min., I =–4.0 mA
Min. Max. Min. Max. Min. Max. Min. Max. Unit
V
V
V
V
Output HIGH
Voltage
V
V
2.4
2.4
2.4
2.4
V
V
OH
OL
IH
CC
CC
OH
Output LOW
Voltage
=Min., I =8.0 mA
0.4
0.4
0.4
0.4
OL
Input HIGH
Voltage
2.2
–0.5
–5
V
+0.3V
2.2
–0.5
–5
V
+0.3V
2.2
–0.5
–5
V
+0.3V
2.2
–0.5
–5
V
+0.3V
V
CC
CC
CC
CC
Input LOW
Voltage
0.8
+5
0.8
+5
+5
0.8
+5
+5
0.8
+5
+5
V
IL
I
I
I
Input Load
Current
GND < V < V
CC
µA
µA
IX
I
Output Leakage GND < V < V
Current
,
–5
+5
–5
–5
–5
OZ
CC
O
CC
Output Disabled
V
Operating
V
I
f = f
= Max.,
= 0 mA,
Com’l
L
120
110
85
160
85
155
100
180
30
mA
mA
mA
mA
mA
CC
CC
Supply Current
OUT
= 1/t
MAX
RC
Mil
I
I
Automatic CE
Power-Down
Current— TTL
Inputs
Max. V , CE >
Com’l
L
5
5
5
30
5
SB1
SB2
CC
V ,
V
V
IH
5
> V or
IH
IN
IN
< V , f = f
IL
MAX
Automatic CE
Power-Down
Current— CMOS
Inputs
Max. V
CE > V – 0.3V
,
Com’l
L
0.5
0.5
10
10
0.05
15
mA
mA
mA
CC
CC
0.05
0.05
0.05
V
> V – 0.3V
IN
CC
Mil
or V < 0.3V, f = 0
IN
Shaded area contains preliminary information.
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
2
CY7C199
[3]
Electrical Characteristics Over the Operating Range (continued)
7C199-20
7C199-25
7C199-35
7C199-45
Parameter
Description
Test Conditions
=Min., I =–4.0 mA
Min. Max. Min. Max. Min. Max.
Min.
Max. Unit
V
V
V
V
Output HIGH
Voltage
V
V
2.4
2.4
2.4
2.4
V
OH
OL
IH
CC
CC
OH
Output LOW
Voltage
=Min., I =8.0 mA
0.4
0.4
0.4
0.4
V
V
OL
Input HIGH
Voltage
2.2
–0.5
–5
V
+0.3V
2.2
-0.5
–5
V
+0.3V
2.2
-0.5
–5
V
+0.3V
2.2
-0.5
–5
V
CC
CC
CC
CC
+0.3V
Input LOW
Voltage
0.8
+5
+5
0.8
+5
+5
0.8
+5
+5
0.8
+5
+5
V
IL
I
I
I
Input Load
Current
GND < V < V
CC
µA
µA
IX
I
Output Leakage GND < V < V ,
CC
Current
–5
–5
–5
–5
OZ
CC
I
Output Disabled
V
Operating
V
I
f = f
= Max.,
= 0 mA,
Com’l
L
150
90
170
30
5
150
80
140
70
140
70
mA
mA
mA
mA
mA
CC
CC
Supply Current
OUT
= 1/t
MAX
RC
Mil
150
30
150
25
150
25
I
I
Automatic CE
Power-Down
Current—
Max. V , CE > V , Com’l
SB1
SB2
CC
IH
V
> V
IN
IH
L
5
5
5
or V < V , f = f
IN
IL
MAX
TTL Inputs
Automatic CE
Power-Down
Current—
Max. V
,
Com’l
L
10
0.05
15
10
0.05
15
10
0.05
15
10
0.05
15
mA
µA
CC
CE > V – 0.3V
CC
V
> V – 0.3V or
IN
CC
CMOS Inputs
V
< 0.3V, f=0
Mil
mA
IN
]
Capacitance[4]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
Input Capacitance
Output Capacitance
8
8
IN
A
V
= 5.0V
CC
pF
OUT
3
CY7C199
AC Test Loads and Waveforms[5]
R1 481
R1 481
Ω
Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
10%
R2
255
R2
255
30 pF
5 pF
Ω
Ω
t
≤
t
≤
r
r
INCLUDING
JIGAND
INCLUDING
JIGAND
C199–5
SCOPE
SCOPE
C199–6
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
Data Retention Characteristics Over the Operating Range (L version only)
[6]
Parameter
Description
for Data Retention
CC
Conditions
Min.
Max.
Unit
V
V
V
2.0
DR
I
Data Retention Current
Com’l
V
= V = 2.0V,
µA
µA
ns
CCDR
CC
DR
CE > V – 0.3V,
CC
Com’l L
10
V
V
> V – 0.3V or
IN
IN
CC
< 0.3V
[4]
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
CDR
[5]
R
t
ns
RC
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
C199–7
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. R < 3 ns for the -12 and -15 speeds. tR < 5 ns for the -20 and slower speeds.
6. No input may exceed VCC + 0.5V.
t
4
CY7C199
[3, 7]
Switching Characteristics Over the Operating Range
7C199-8
7C199-10
Min. Max.
7C199-12
Min. Max.
7C199-15
Min. Max.
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
8
3
10
3
12
3
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
8
10
12
15
AA
Data Hold from Address Change
CE LOW to Data Valid
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
8
10
5
12
5
15
7
OE LOW to Data Valid
4.5
[8]
OE LOW to Low Z
0
3
0
0
3
0
0
3
0
0
3
0
[8, 9]
OE HIGH to High Z
5
4
8
5
5
5
5
7
7
[8]
CE LOW to Low Z
[8,9]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
15
PD
[10, 11]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
8
7
7
0
0
7
5
0
10
7
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
9
0
0
HA
0
0
0
SA
7
8
9
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
5
8
9
0
0
0
HD
[9]
WE LOW to High Z
5
6
7
7
HZWE
LZWE
[8]
WE HIGH to Low Z
3
3
3
3
Shaded area contains preliminary information.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WEcontrolled, OE LOW) is the sum of tHZWE and tSD
.
5
CY7C199
[3,7]
Switching Characteristics Over the Operating Range
(continued)
7C199-20 7C199-25
Min. Max.
7C199-35
7C199-45
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
Read Cycle Time
20
3
25
3
35
3
45
3
ns
ns
ns
RC
Address to Data Valid
20
25
35
45
AA
Data Hold from Address
Change
OHA
t
t
t
t
t
t
t
t
CE LOW to Data Valid
OE LOW to Data Valid
20
9
25
10
35
16
45
16
ns
ns
ns
ns
ns
ns
ns
ns
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
[8]
OE LOW to Low Z
0
3
0
0
3
0
0
3
0
0
3
0
[8,9]
OE HIGH to High Z
9
9
11
11
20
15
15
20
15
15
25
[8]
CE LOW to Low Z
[8,9]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
20
PD
[10,11]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
20
15
15
0
25
18
20
0
35
22
30
0
45
22
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
0
SA
15
10
0
18
10
0
22
15
0
22
15
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[9]
WE LOW to High Z
10
11
15
15
HZWE
LZWE
[8]
WE HIGH to Low Z
3
3
3
3
Switching Waveforms
[12, 13]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C199–8
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
6
CY7C199
Switching Waveforms (continued)
[13, 14]
Read Cycle No. 2
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
ICC
CC
SUPPLY
CURRENT
50%
50%
ISB
C199–9
[10, 15, 16]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
IN
DATA I/O
t
HZOE
C199–10
[10, 15, 16]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA
VALID
IN
C199–11
Notes:
14. Address valid prior to or coincident with CEtransition LOW.
15. Data I/O is high impedance if OE = VIH
.
16. If CEgoes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
7
CY7C199
Switching Waveforms (continued)
[11, 16]
Write Cycle No. 3 (WE Controlled OE LOW)
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
t
t
LZWE
HZWE
C199–12
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY
VOLTAGE
120
100
80
1.4
1.2
1.4
1.2
1.0
0.8
0.6
I
CC
I
CC
1.0
0.8
0.6
V
CC
=5.0V
60
T =25 C
°
A
V
IN
=5.0V
T =25 C
°
A
40
V
V
IN
=5.0V
=5.0V
0.4
CC
0.4
20
0
0.2
0.0
0.2
0.0
I
SB
I
SB
–55
25
125
0.0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE ( C)
°
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
100
80
1.2
1.0
1.1
1.0
60
T =25 C
°
A
V
CC
=5.0V
T =25 C
°
V
CC
=5.0V
A
40
0.8
20
0
0.9
0.8
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE ( C)
OUTPUT VOLTAGE (V)
°
SUPPLY VOLTAGE (V)
8
CY7C199
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT
vs.SUPPLY VOLTAGE
TYPICAL ACCESS TIMECHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs. CYCLETIME
CC
3.0
2.5
2.0
1.5
30.0
25.0
20.0
15.0
1.25
1.00
0.75
0.50
V
=5.0V
°
=0.5V
CC
T =25 C
A
V
IN
V
=4.5V
°
1.0
0.5
10.0
5.0
CC
T =25 C
A
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
0
200 400
600 800 1000
10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE WE OE Inputs/Outputs
Mode
Power
Standby (I )
SB
H
L
L
L
X
H
L
X
L
High Z
Deselect/Power-Down
Data Out
Data In
High Z
Read
Write
Active (I
Active (I
)
CC
X
H
)
CC
H
Deselect, Output Disabled Active (I
)
CC
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY7C199-8VC
Name
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
P21
V21
Z28
P21
V21
Z28
V21
Z28
V21
Z28
Package Type
28-Lead Molded SOJ
8
Commercial
Commercial
Industrial
CY7C199-8ZC
CY7C199L-8VC
CY7C199L-8ZC
CY7C199-10VC
CY7C199-10ZC
CY7C199L-10VC
CY7C199L-10ZC
CY7C199-10VI
CY7C199-10ZI
CY7C199L-10VI
CY7C199L-10ZI
CY7C199-12PC
CY7C199-12VC
CY7C199-12ZC
CY7C199L-12PC
CY7C199L-12VC
CY7C199L-12ZC
CY7C199-12VI
CY7C199-12ZI
CY7C199L-12VI
CY7C199L-12ZI
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
10
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
12
Commercial
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
Shaded area contains preliminary information. Contact your Cypress sales representative for availability
9
CY7C199
Ordering Information (continued)
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C199-15PC
CY7C199-15VC
CY7C199-15ZC
CY7C199L-15PC
CY7C199L-15VC
CY7C199L-15ZC
CY7C199-15VI
Name
P21
V21
Z28
P21
V21
Z28
V21
Z28
D22
L54
D22
L54
P21
V21
Z28
P21
V21
Z28
V21
Z28
D22
L54
D22
L54
P21
S21
V21
Z28
Z28
D22
L54
P21
S21
V21
Z28
D22
L54
D22
L54
Package Type
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
15
20
25
Commercial
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
Military
CY7C199-15ZI
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
CY7C199-15DMB
CY7C199-15LMB
CY7C199L-15DMB
CY7C199L-15LMB
CY7C199-20PC
CY7C199-20VC
CY7C199-20ZC
CY7C199L-20PC
CY7C199L-20VC
CY7C199L-20ZC
CY7C199-20VI
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
Commercial
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
Industrial
Military
CY7C199-20ZI
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
CY7C199-20DMB
CY7C199-20LMB
CY7C199L-20DMB
CY7C199L-20LMB
CY7C199-25PC
CY7C199-25SC
CY7C199-25VC
CY7C199-25ZC
CY7C199L-25ZI
CY7C199-25DMB
CY7C199-25LMB
CY7C199-35PC
CY7C199-35SC
CY7C199-35VC
CY7C199-35ZC
CY7C199-35DMB
CY7C199-35LMB
CY7C199-45DMB
CY7C199-45LMB
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
Commercial
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
Industrial
Military
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
35
45
Commercial
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
Military
Military
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
Shaded area contains preliminary information. Contact your Cypress sales representative for availability
10
CY7C199
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Parameter
Subgroups
V
READ CYCLE
OH
OL
IH
V
V
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
RC
AA
V Max.
IL
OHA
ACE
DOE
I
I
I
I
I
IX
OZ
CC
SB1
SB2
WRITE CYCLE
t
t
t
t
t
t
t
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WC
AA
AW
HA
SA
PWE
SD
HD
Document #: 38–00239–E
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL–STD–1835 D–15 Config.A
28-Pin Rectangular Leadless ChipCarrier L54
MIL–STD–1835 C–11A
11
CY7C199
Package Diagrams (continued)
28-Lead (300-Mil) Molded DIP P21
28-Lead (300-Mil) Molded SOIC S21
12
CY7C199
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ V21
28-Lead ThinSmall Outline Package Z28
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
©2020 ICPDF网 联系我们和版权申明