BCM20704UA2KFFB1G中文资料_数据手册_规格书

CYW20704

Single-Chip Bluetooth Transceiver

and Baseband Processor

The Cypress CYW20704 is a monolithic, single-chip, Bluetooth 4.1+ HS-compliant, stand-alone baseband processor with an

integrated 2.4 GHz transceiver. Manufactured using the industry's most advanced 40 nm CMOS low-power process, the CYW20704

employs the highest level of integration, eliminating all critical external components, and thereby minimizing the device’s footprint and

costs associated with the implementation of Bluetooth solutions.

The CYW20704 is the optimal solution for voice and data applications that require a Bluetooth SIG standard Host Controller Interface

(HCI) via USB, UART H4, and PCM audio interface support.

The CYW20704 transceiver’s enhanced radio performance meets the most stringent industrial temperature application requirements

for compact integration into mobile handset and portable devices. The CYW20704 provides full radio compatibility, enabling it to

operate simultaneously with GPS and cellular radios.

Cypress Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number

Cypress Part Number

BCM20704

CYW20704

BCM20704UA2KFFB1G

CYW20704UA2KFFB1G

Features

■ Complies with Bluetooth Core Specification Version 4.1+ HS

■ Ultra-low power consumption

with provisions for supporting future specifications

■ Supports serial flash interfaces

■ Bluetooth Class 1 or Class 2 transmitter operation

■ Supports mobile and PC applications without external memory

■ Available in a 49-ball FcBGA package

■ Supports extended synchronous connections (eSCO), for

enhanced voice quality by allowing for retransmission of

dropped packets

IoT Applications

■ Adaptive frequency hopping (AFH) for reducing radio

■ Remotes: TV/Entertainment

■ USB dongles

frequency interference

■ Interface support, host controller interface (HCI) using a USB

or high-speed UART interface and PCM for audio data

■ Wearables

■ USB2.0 full-speed with LPM support (12 Mbps)

■ Smart metering

■ Supports Cypress proprietary 2 Mbps low energy mode.

Cypress Semiconductor Corporation

Document Number: 002-14786 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Thursday, September 29, 2016

CYW20704

Figure 1. Functional Block Diagram

CYW20704

PCM/I²S

USB

UART

High-Speed

Peripheral Transport

Unit (PTU)

GPIO

SPI Master

BSC

Radio Transceiver

Microprocessor and

Memory Unit (µPU)

Bluetooth Baseband

Core (BBC)

IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your

design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of

information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software

updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://

community.cypress.com/).

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CYW20704

Contents

4.3 EEPROM ............................................................13

4.4 External Reset ....................................................13

4.5 One-Time Programmable Memory .....................14

1. Overview............................................................ 4

1.1 Overview ............................................................. 4

1.2 Major Features .................................................... 4

1.3 Block Diagram ..................................................... 5

1.2 Usage Model ....................................................... 6

5. Peripheral Transport Unit.............................. 15

5.1 PCM Interface ....................................................15

5.2 HCI Transport Detection Configuration ..............16

5.3 USB Interface .....................................................17

5.4 UART Interface ..................................................18

5.5 Simultaneous UART Transport and Bridging .....18

2. Integrated Radio Transceiver.......................... 7

2.1 Transmit .............................................................. 7

2.2 Receiver .............................................................. 7

2.3 Local Oscillator Generation ................................. 7

2.4 Calibration ........................................................... 7

2.5 Internal LDO ........................................................ 8

6. Frequency References................................... 19

6.1 Crystal Interface and Clock Generation .............20

6.2 Crystal Oscillator ................................................20

6.3 Frequency Selection ..........................................20

6.4 Frequency Trimming ..........................................20

3. Bluetooth Baseband Core ............................... 9

3.1 Bluetooth Low Energy ......................................... 9

3.2 Bluetooth 4.1 Features ........................................ 9

3.3 Bluetooth 4.0 Features ........................................ 9

3.4 Link Control Layer ............................................. 10

3.5 Test Mode Support ............................................ 10

3.6 Power Management Unit ................................... 10

3.7 Adaptive Frequency Hopping ............................ 11

3.8 Collaborative Coexistence ................................ 12

3.9 Global Coexistence Interface ............................ 12

7. Pin-out and Signal Descriptions................... 21

7.1 Pin Descriptions .................................................21

8. Ball Grid Arrays.............................................. 23

9. Electrical Characteristics .............................. 24

9.1 RF Specifications ...............................................27

9.2 Timing and AC Characteristics ...........................31

9.3 I²S Interface .......................................................39

3.10 Recommended BT Coexistence Interface

Assignments ...................................................... 12

10. Mechanical Information ................................. 45

4. Microprocessor Unit....................................... 13

4.1 Overview ........................................................... 13

4.2 NVRAM Configuration Data and Storage .......... 13

10.1 Tape, Reel, and Packing Specification ..............46

11. Ordering Information ..................................... 47

Document History........................................................... 48

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CYW20704

1. Overview

1.1 Overview

The Cypress CYW20704 complies with Bluetooth Core Specification, version 4.1+ HS and is designed for use in standard Host Con-

troller Interface (HCI) UART and HCI USB applications. The combination of the Bluetooth Baseband Core (BBC), a Peripheral

Transport Unit (PTU), and a Cortex-M3 based microprocessor with on-chip ROM provides a complete lower layer Bluetooth protocol

stack, including the Link Controller (LC), Link Manager (LM), and HCI.

1.2 Major Features

Major features of the CYW20704 include:

■ Bluetooth v4.1 + EDR with integrated Class 1 PA

■ BT host digital interface (can be used concurrently with below interfaces):

❐ USB 2.0 full-speed with LPM support (up to 12 Mbps)

❐ UART (up to 4 Mbps)42

■ Integrated RF section

❐ Single-ended, 50Ω RF interface

❐ Built-in TX/RX switch functionality

❐ TX Class 1 output power capability

❐ RX sensitivity basic rate of –93.5 dBm

❐ RX sensitivity for Low Energy of –96 dBm

■ GCI-enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receives

■ Supports maximum Bluetooth data rates over HCI and USB interfaces

■ I²S/PCM for BT audio

■ HCI high-speed UART (H4, H4+) transport support

■ Wideband speech support (16 bits linear data, MSB first, left-justified at 4K samples/s for transparent air coding, both through I²S

and PCM interface)

■ Bluetooth SmartAudio^®technology improves voice and music quality to headsets

■ Bluetooth low-power inquiry and page scan

■ Bluetooth low energy (BLE) support

■ Supports Cypress proprietary 2 Mbps low energy mode

■ Maximum of 127 LE Connections

■ Supports TBFC (Triggered Cypress [Bluetooth] Fast Connect)

■ Bluetooth packet loss concealment (PLC)

■ Bluetooth wide band speech (WBS)

■ High-speed HCI UART transport support

❐ H4 five-wire UART (four signal wires, one ground wire)

❐ Maximum UART baud rates of 4 Mbps

❐ Low-power out-of-band BT_WAKE and HOST_WAKE signaling

❐ VSC from host transport to UART

❐ Proprietary compression scheme (allows more than two simultaneous A2DP packets and up to five devices at a time)

■ HCI USB transport support

❐ USB version 2.0 full-speed compliant interface with LPM support

❐ UHE (proprietary method for emulating a human interface device (HID) at system boot up)

■ Standard Bluetooth test modes

■ Extended radio and production test mode features

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CYW20704

■ Full support for power savings modes:

❐ Bluetooth standard sniff

❐ Deep sleep modes and regulator shutdown

■ Built-in LPO clock

■ Larger patch RAM space to support future enhancements

■ Serial flash Interface with native support for devices from several manufacturers

■ One-Time Programmable (OTP) memory

1.3 Block Diagram

Figure 2 shows the interconnect of the major CYW20704 physical blocks and associated external interfaces.

Figure 2. Functional Block Diagram

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CYW20704

1.2 Usage Model

This section contains information on the PC Product Usage Model.

1.2.1 PC Product Usage Model

The CYW20704 can be directly interfaced using the HCI USB interface, providing full support for embedded USB applications like

laptop and PC motherboards. The CYW20704 also supports PC applications such as external USB dongle peripheral devices.

Figure 3 shows an example of a typical PC product usage model.

Figure 3. Typical PC Product Usage Model

3.3V

Host PC

USB

LINK_IND

CYW20704

20 MHz Crystal Oscillator

Flash Memory

Serial Interface

BT_GCI_SECI_IN

IEEE 802.11™

WLAN

BT_GCI_SECI_OUT

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CYW20704

2. Integrated Radio Transceiver

The CYW20704 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has

been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz

unlicensed ISM band. The CYW20704 is fully compliant with the Bluetooth Radio Specification and enhanced data rate (EDR) spec-

ification and meets or exceeds the requirements to provide the highest communication link quality of service.

2.1 Transmit

The CYW20704 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block

and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion,

output power amplifier, and RF filtering. The transmitter path also incorporates pi/4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to

support EDR. The transmitter section is compatible to the Bluetooth Low Energy specification. The transmitter PA bias can also be

adjusted to provide Bluetooth class 1 or class 2 operation.

2.1.1 Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK, pi/4 – DQPSK, and

8 – DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the trans-

mitted signal and is much more stable than direct VCO modulation schemes.

2.1.2 Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-syn-

chronization algorithm.

2.1.3 Power Amplifier

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides

greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, exter-

nal filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. The transmitter features a sophis-

ticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across

process, voltage, and temperature.

2.2 Receiver

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit syn-

chronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering

to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation enables the

CYW20704 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth

function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by

the cellular transmit signal.

2.2.1 Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit syn-

chronization algorithm.

2.2.2 Receiver Signal Strength Indicator

The radio portion of the CYW20704 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband, so that the control-

ler can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether

the transmitter should increase or decrease its output power.

2.3 Local Oscillator Generation

Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.

The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW20704 uses an

internal RF and IF loop filter.

2.4 Calibration

The CYW20704 radio transceiver features an automated calibration scheme that is fully self contained in the radio. No user interac-

tion is required during normal operation or during manufacturing to provide the optimal performance. Calibration optimizes the per-

formance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters,

matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Cali-

bration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations as

the device cools and heats during normal operation in its environment.

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CYW20704

2.5 Internal LDO

The CYW20704 uses two LDOs—one for 1.2V and the other for 2.5V. The 1.2V LDO is used to provide the power supply to the

baseband and the radio while the 2.5V LDO is used for the PA power supply.

Figure 4. LDO Functional Block

CYW20704 PMU

VDDC_IN

1.2V LDO (VDDC_LDO)

VDDC_OUT

VDD2P5_IN

2.5V LDO (BTLDO2P5)

AVSS_GND

VDD2P5_OUT

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CYW20704

3. Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation.

The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,

handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and pack-

ages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to

these functions, it independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/

RX data before sending over the air:

Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check

(CRC), data decryption, and data dewhitening in the receiver.

Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the trans-

mitter.

3.1 Bluetooth Low Energy

The CYW20704 supports dual-mode Bluetooth Low Energy (BT and BLE) operation.

3.2 Bluetooth 4.1 Features

The CYW20704 supports the new features expected in Bluetooth v4.1.

■ Secure connections (LE/BR/EDR)

■ Fast advertising interval

■ Piconet clock adjust

■ Clock nudging

■ Connectionless Broadcast

■ LE enhanced privacy

■ Low duty cycle directed advertising

■ LE dual mode topology

3.3 Bluetooth 4.0 Features

The CYW20704 supports all Bluetooth 4.0 features, with the following benefits:

■ Extended Inquiry Response (EIR)

■ Encryption Pause Resume (EPR)

■ Sniff Subrating (SSR)

■ Secure Simple Pairing (SSP)

■ Link Supervision Time Out (LSTO)

■ QoS enhancements

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CYW20704

3.4 Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit

(LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are acti-

vated or configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth

Link Controller.

■ Major states:

❐ Standby

❐ Connection

■ Substates:

❐ Page

❐ Page Scan

❐ Inquiry

❐ Inquiry Scan

❐ Sniff

3.5 Test Mode Support

The CYW20704 fully supports Bluetooth Test mode as described in Specification of the Bluetooth Core v4.1, which includes the

transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. In addition to the standard Bluetooth Test

Mode, the CYW20704 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing,

including:

■ Fixed frequency carrier wave (unmodulated) transmission

❐ Simplifies some type-approval measurements (Japan)

❐ Aids in transmitter performance analysis

■ Fixed frequency constant receiver mode

❐ Receiver output directed to I/O pin

❐ Allows for direct BER measurements using standard RF test equipment

❐ Facilitates spurious emissions testing for receive mode

■ Fixed frequency constant transmission

❐ 8-bit fixed pattern, PRBS-9, or PRBS-15

❐ Enables modulated signal measurements with standard RF test equipment

3.6 Power Management Unit

The Power Management Unit (PMU) provides power management features that can be invoked through power management regis-

ters or packet handling in the baseband core. This section contains descriptions of the PMU features.

3.6.1 RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-

ceiver. The transceiver then processes the power-down functions, accordingly.

3.6.2 Host Controller Power Management

The host can place the device in a sleep state, in which all nonessential blocks are powered off and all nonessential clocks are dis-

abled. Power to the digital core is maintained so that the state of the registers and RAM is not lost. In addition, the CYW20704 inter-

nal LPO clock is applied to the internal sleep controller so that the chip can wake automatically at a specified time or based on

signaling from the host. The goal is to limit the current consumption to a minimum, while maintaining the ability to wake up and

resume a connection with minimal latency.

If a scan or sniff session is enabled while the device is in Sleep mode, the device automatically will wake up for the scan/sniff event,

then go back to sleep when the event is done. In this case, the device uses its internal LPO-based timers to trigger the periodic wake

up. While in Sleep mode, the transports are idle. However, the host can signal the device to wake up at any time. If signaled to wake

up while a scan or sniff session is in progress, the session continues but the device will not sleep between scan/sniff events. Once

Sleep mode is enabled, the wake signaling mechanism can also be thought of as a sleep signaling mechanism, since removing the

wake status will often cause the device to sleep.

In addition to a Bluetooth device wake signaling mechanism, there is a host wake signaling mechanism. This feature provides a way

for the Bluetooth device to wake up a host that is in a reduced power state.

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CYW20704

There are two mechanisms for the device and the host to signal wake status to each other:

USB

When running in USB mode with LPM, the device supports the USB version 2.0

full-speed specification, suspend/resume signaling, as well as remote wake-up

signaling for power control.

Bluetooth device WAKE (BT_DEV_WAKE) and The BT_DEV_WAKE signal allows the host to wake the BT device, and

Host WAKE (and BT_HOST_WAKE) signaling

BT_HOST_WAKE is an output that allows the BT device to wake the host.

Table 2. Power Control Pin Summary

Direction

Description

BT_DEV_WAKE

(BT_GPIO_0)

Host output

BT input

Bluetooth device wake-up: Signal from the host to the Bluetooth device that the host

requires attention.

■Asserted = Bluetooth device must wake up or remain awake.

■Deasserted = Bluetooth device may sleep when sleep criteria are met.

The polarity of this signal is software configurable and can be asserted high or low. By

default, BT_DEV_WAKE is active-low (if BT-WAKE is low it requires the device to wake up

or remain awake).

For USB applications, this pin can be used to disable the BT radio, which puts the device

in Airport mode.

BT_HOST_WAKE

(BT_GPIO_1)

BT output

Host input

Host wake-up. Signal from the Bluetooth device to the host indicating that Bluetooth device

requires attention.

■Asserted = Host device must wake up or remain awake.

■Deasserted = Host device may sleep when sleep criteria are met.

The polarity of this signal is software configurable and can be asserted high or low.

BT_CLK_REQ

RST_N

BT output

BT input

Clock request

■Asserted = External clock reference required

■Deasserted = External clock reference may be powered down

Used to place the chip in reset. RST_N is active-low.

3.6.3 Bluetooth Baseband Core Power Management

The following are low-power operations for the Bluetooth Baseband Core (BBC):

■ Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.

■ Bluetooth-specified low-power connection modes: sniff, hold, and park. While in these modes, the CYW20704 runs on the low-power

oscillator and wakes up after a predefined time period.

3.7 Adaptive Frequency Hopping

The CYW20704 supports host channel classification and dynamic channel classification Adaptive Frequency Hopping (AFH)

schemes, as defined in the Bluetooth specification.

Host channel classification enables the host to set a predefined hopping map for the device to follow.

If dynamic channel classification is enabled, the device gathers link quality statistics on a channel-by-channel basis to facilitate chan-

nel assessment and channel map selection. To provide a more accurate frequency hop map, link quality is determined using both RF

and baseband signal processing.

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CYW20704

3.8 Collaborative Coexistence

The CYW20704 provides extensions and collaborative coexistence to the standard Bluetooth AFH for direct communication with

WLAN devices. Collaborative coexistence enables WLAN and Bluetooth to operate simultaneously in a single device. The device

supports industry-standard coexistence signaling, including 802.15.2, and supports Cypress and third-party WLAN solutions.

3.9 Global Coexistence Interface

The CYW20704 supports the proprietary Cypress Global Coexistence Interface (GCI) which is a 2-wire interface.

The following key features are associated with the interface:

■ Enhanced coexistence data can be exchanged over GCI_SECI_IN and GCI_SECI_OUT a two-wire interface, one serial input

(GCI_SECI_IN), and one serial output (GCI_SECI_OUT). The pad configuration registers must be programmed to choose the digital

I/O pins that serve the GCI_SECI_IN and GCI_SECI_OUT function.

■ It supports generic UART communication between WLAN and Bluetooth devices.

■ To conserve power, it is disabled when inactive.

■ It supports automatic resynchronizaton upon waking from sleep mode.

■ It supports a baud rate of up to 4 Mbps.

3.9.1 SECI I/O

The CYW20704 devices have dedicated GCI_SECI_IN and GCI_SECI_OUT pins. The two pin functions can be mapped to any of

the Cypress Global Co-existence Interface (GCI) GPIO. Pin function mapping is controlled by the configuration file that is stored in

either NVRAM or downloaded directly into on-chip RAM from the host.

3.10 Recommended BT Coexistence Interface Assignments

The following tables show the recommended BT coexistence interface assignments.

Table 3. BT GCI Two-Wire Coexistence

Coexistence Signal Name

BT_SECI_IN

BT_SECI_OUT

Signal Assignment

Pin Number

GPIO_6

GPIO_7

B6

C6

Table 4. BT GCI Three-Wire Coexistence

Coexistence Signal Name

BTCX_WL_ACTIVE

BTCX_BT_ACTIVE

BTCX_PRI_STATUS

PCM_IN

C7

C8

B7

PCM_SYNC

PCM_CLK

Table 5. BT GCI Four-Wire Coexistence

Coexistence Signal Name

Signal Assignment

Pin Number

BTCX_WL_ACTIVE

BTCX_BT_ACTIVE

BTCX_PRI_STATUS

BTCX_STATUS2

PCM_IN

C7

C8

B7

A8

PCM_SYNC

PCM_CLK

PCM_OUT

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CYW20704

4. Microprocessor Unit

4.1 Overview

The CYW20704 microprocessor unit runs software from the Link Control (LC) layer up to the Host Controller Interface (HCI). The

microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The

microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad,

and patch RAM code.

The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations,

including automatic host transport selection from UART and USB transports with or without external NVRAM. At power-up, the lower

layer protocol stack is executed from the internal ROM.

External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches

can be downloaded from the host to the device through the SPI interface or UART and USB transports, or using external NVRAM.

The device can also support the integration of user applications and profiles using an external serial flash memory.

4.2 NVRAM Configuration Data and Storage

4.2.1 Serial Interface

The CYW20704 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB

slave interface, transmit and receive FIFOs, and the SPI core PHY logic. Data is transferred to and from the module by the system

CPU. DMA operation is not supported.

4.3 EEPROM

The CYW20704 includes a Cypress Serial Control (BSC) master interface. The BSC interface supports low-speed and fast mode

devices and is compatible with I²C slave devices. Multiple I²C master devices and flexible wait state insertion by the master interface

or slave devices are not supported. The CYW20704 provides 400 kHz, full speed clock support.

The BSC interface is programmed by the CPU to generate the following BSC transfer types on the bus:

■ Read-only

■ Write-only

■ Combined read/write

■ Combined write-read

NVRAM may contain configuration information about the customer application, including the following:

■ Fractional-N information

■ BD_ADDR

■ UART baud rate

■ USB enumeration information

■ SDP service record

■ File system information used for code, code patches, or data

4.4 External Reset

The CYW20704 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action

can also be driven by an external reset signal, which can be used to externally control the device, forcing it into a power-on reset

state. The RST_N signal is an active-low signal, which is an input to the CYW20704 chip. The CYW20704 does not require an exter-

nal pull-up resistor on the RST_N input.

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CYW20704

4.5 One-Time Programmable Memory

The CYW20704 includes a One-Time Programmable (OTP) memory, allowing manufacturing customization and avoiding the need

for an on-board NVRAM.If customization is not required, then the OTP does not need to be programmed. Whether the OTP is pro-

grammed or not, it is disabled after the boot process completes to save power.

The OTP size is 2048 bytes.

The OTP is designed to store a minimal amount of information. Aside from OTP data, most user configuration information will be

downloaded into RAM after the CYW20704 boots up and is ready for host transport communication. The OTP contents are limited

to:

■ Parameters required prior to downloading user configuration to RAM.

■ Parameters unique to each part and each customer (i.e., the BD_ADDR, software license key, and USB PID/VID).

The OTP memory is particularly useful in a PC design with USB transport capability because:

■ Some customer-specific information must be configured before enumerating the part on the USB transport.

■ Partorcustomeruniqueinformation(BD_ADDR, softwarelicensekey, andUSBPID/VID)donotneed tobestoredonthehostsystem.

4.5.1 Contents

The following are typical parameters programmed into the OTP memory:

■ BD_ADDR

■ Software license key

■ USB PID/VID

■ USB bus/self-powered status

■ Output power calibration

■ Frequency trimming

■ Initial status LED drive configuration

The OTP contents also include a static error correction table to improve yield during the programming process as well as forward

error correction codes to eliminate any long-term reliability problems. The OTP contents associated with error correction are not vis-

ible by customers.

4.5.2 Programming

OTP memory programming takes place through a combination of Cypress software integrated with the manufacturing test software

and code embedded in CYW20704 firmware.

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CYW20704

5. Peripheral Transport Unit

This section discusses the PCM, USB, UART, I²S, and SPI peripheral interfaces. The CYW20704 has a 1040-byte transmit and

receive FIFO, which is large enough to hold the entire payload of the largest EDR BT packet (3-DH5).

5.1 PCM Interface

The CYW20704 supports two independent PCM interfaces that share the pins with the I2S interfaces. The PCM Interface on the

CYW20704 can connect to linear PCM Codec devices in master or slave mode. In master mode, the CYW20704 generates the

PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are

inputs to the CYW20704.

The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.

5.1.1 Slot Mapping

The CYW20704 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three

channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sam-

ple interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz,

or 1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM

data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to

allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the

PCM clock during the last bit of the slot.

5.1.2 Frame Synchronization

The CYW20704 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchroniza-

tion mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is

synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the

first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization sig-

nal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident

with the first bit of the first slot.

5.1.3 Data Formatting

The CYW20704 may be configured to generate and accept several different data formats. For conventional narrowband speech

mode, the CYW20704 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to sup-

port various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a

sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

5.1.4 Wideband Speech Support

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM

bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-

bit samples, resulting in a 64 Kbps bit rate. The CYW20704 also supports slave transparent mode using a proprietary rate-matching

scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 Kbps rate) is transferred over the PCM bus.

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CYW20704

5.1.5 Multiplexed Bluetooth Over PCM

Bluetooth supports multiple audio streams within the Bluetooth channel and both 16 kHz and 8 kHz streams can be multiplexed. This

mode of operation is only supported when the Bluetooth host is the master. Figure 5 shows the operation of the multiplexed trans-

port with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased.

To change between modes of operation, the transport must be halted and restarted in the new configuration.

Figure 5. Functional Multiplex Data Diagram

1 frame

BT SCO 1 Rx

BT SCO 1 Tx

BT SCO 2 Rx

BT SCO 2 Tx

BT SCO 3 Rx

BT SCO 3 Tx

PCM_OUT

PCM_IN

PCM_SYNC

PCM_CLK

CLK

16 bits per SCO frame

Each SCO channel duplicates the data 6 times. Each

WBS frame duplicates the data 3 times per frame

5.1.6 Burst PCM Mode

In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and

save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with

an HCI command from the host.

5.2 HCI Transport Detection Configuration

The CYW20704 supports the following interface types for the HCI transport from the host:

■ UART (H4)

■ USB

Only one host interface can be active at a time. The firmware performs a transport detect function at boot-time to determine which

host is the active transport. It can auto-detect UART and USB interfaces, but the SPI interface must be selected by strapping the

SCL pin to 0.

The complete algorithm is summarized as follows:

1. Determine if any local NVRAM contains a valid configuration file. If it does and a transport configuration entry is present, select

the active transport according to entry, and then exit the transport detection routine.

2. Look for start-of-frame (SOF) on the USB interface. If it is present, select USB.

3. Look for CTS_N = 0 on the UART interface. If it is present, select UART.

4. Repeat Step 2 and Step 3 until transport is determined.

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CYW20704

5.3 USB Interface

5.3.1 Features

The following USB interface features are supported:

■ USB Protocol, Revision 2.0, full-speed compliant with LPM support (up to 12 Mbps)

■ Global and selective suspend and resume with remote wake-up

■ Bluetooth HCI

■ HID, DFU, UHE (proprietary method to emulate an HID device at system boot)

■ Integrated detach resistor

Note: If the USB transport is not used, tie the CYW20704 USB pins and VDD_USB to ground.

5.3.2 Operation

The CYW20704 can be configured to boot up as a single USB peripheral, and the host detects a single USB Bluetooth device.

The CYW20704 can boot up showing the independent interfaces connected to logical USB devices internal to the CYW20704—a

generic Bluetooth device, a mouse, and a keyboard. In this mode, the mouse and keyboard are emulated devices, since they con-

nect to real HID devices via a Bluetooth link. The Bluetooth link to these HID devices is hidden from the USB host. To the host, the

mouse and/or keyboard appear to be directly connected to the USB port. This Cypress proprietary architecture is called USB HID

Emulation (UHE).

The USB device, configuration, and string descriptors are fully programmable, allowing manufacturers to customize the descriptors,

including vendor and product IDs, the CYW20704 uses to identify itself on the USB port. To make custom USB descriptor informa-

tion available at boot time, stored it in external NVRAM.

In the single USB peripheral operating mode, the Bluetooth device is configured to include the following interfaces:

Interface 0

Contains a Control endpoint (Endpoint 0x00) for HCI commands, a Bulk In Endpoint (Endpoint 0x82) for receiving

ACL data, a Bulk Out Endpoint (Endpoint 0x02) for transmitting ACL data, and an Interrupt Endpoint (Endpoint

0x81) for HCI events.

Interface 1

Interface 2

Contains Isochronous In and Out endpoints (Endpoints 0x83 and 0x03) for SCO traffic. Several alternate Interface

1 settings are available for reserving the proper bandwidth of isochronous data (depending on the application).

Contains Bulk In and Bulk Out endpoints (Endpoints 0x84 and 0x04) used for proprietary testing and debugging

purposes. These endpoints can be ignored during normal operation.

5.3.3 UHE Support

The CYW20704 supports the USB device model (USB 2.0-compatible, full-speed compliant with LPM support). Optional mouse and

keyboard interfaces utilize Cypress’s proprietary USB HID Emulation (UHE) architecture, which allows these Bluetooth devices

appear as standalone HID devices even though connected through a Bluetooth link.

The presence of UHE devices requires the CYW20704 to be configured as a composite device (Composite mode). In this mode, the

Bluetooth mouse and keyboard interfaces are independently controlled and appear as standalone logical devices.

Cypress’s standard composite configuration uses the following layout:

■ Interface 0—Keyboard

■ Interface 1—Mouse

■ Interface 2/3/4—Bluetooth (as described above)

When operating in Composite mode, every interface does not have to be enabled—each can be optionally enabled. The configura-

tion record in NVRAM determines which devices are present.

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CYW20704

5.4 UART Interface

The CYW20704 shares a single UART for Bluetooth. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjust-

able baud rates from 38400 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud

rate selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command.

UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through the

AHB interface through either DMA or the CPU. The UART supports the Bluetooth 4.1 UART HCI specification: H4, and a custom

Extended H4. The default baud rate is 115.2 Kbaud.

The CYW20704 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol (SLIP).

It can also perform wake-on activity. For example, activity on the RX or CTS inputs can wake the chip from a sleep state.

Normally, the UART baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detection,

and the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is

included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW20704

UARTs operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%.

Table 6. Example of Common Baud Rates

Desired Rate

Actual Rate

Error (%)

4000000

3000000

2000000

1500000

921600

460800

230400

115200

57600

4000000

3000000

2000000

1500000

923077

461538

230796

115385

57692

0.00

0.16

0.17

0.16

0.00

38400

5.5 Simultaneous UART Transport and Bridging

Note: Simultaneous UART transport and bridging is only valid for the HCI operating mode.

The CYW20704 supports UART or USB interfaces that can function as the host controller interface (HCI). Typically, a customer

application would choose one of the two interfaces and the other would be idle. The CYW20704 allows the UART transport to oper-

ate simultaneously with the USB. To operate this way, the assumption is that the USB would function as the primary host transport,

while the UART would function as a secondary communication channel that can operate at the same time. This can enable the fol-

lowing applications:

■ Bridging primary HCI transport traffic to another device via the UART

■ Generic communication to an external device for a vendor-supported application via the UART

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CYW20704

6. Frequency References

The CYW20704 uses an external crystal for generating all radio frequencies and normal operation clocking. As an alternative, an

external frequency reference can be used.

6.1 Crystal Interface and Clock Generation

The CYW20704 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing, enabling it to

operate from any of a multitude of frequency sources. The source can be external, such as a crystal interfaced directly to the device

or an external frequency reference can be used.

Typical crystal frequencies of 20 MHz and 40 MHz are supported using the XTAL_STRAP_1 pin on the CYW20704. The signal char-

acteristics for the crystal interface are listed in Table 7 on page 19.

Table 7. Crystal Interface Signal Characteristics

Parameter

Acceptable frequencies

Crystal load capacitance

ESR

Crystal

19.2–52 MHz in 2 ppm^asteps

12 (typical)

External Frequency Reference

12–52 MHz in 2 ppm^asteps

Units

–

N/A

–

pF

60 (max)

Ω

Power dissipation

Input signal amplitude

200 (max)

–

μW

mVp-p

N/A

400 to 1200

2000 to 3300 (requires a 10 pF DC blocking

capacitor to attenuate the signal)

Signal type

N/A

Square-wave or sine-wave

–

Input impedance

≥1

≤2

MΩ

pF

Phase noise

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

N/A

–

< –120

< –130

< –135

< –136

dBc/Hz

Tolerance without frequency

trimming^b

±20

ppm

Initial frequency tolerance trimming ±50

range

±50

ppm

a. The frequency step size is approximately 80 Hz resolution.

b. AT-Cut crystal or TXCO recommended.

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CYW20704

6.2 Crystal Oscillator

The CYW20704 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscil-

lator, including all external components, is shown in Figure 6.

Figure 6. Recommended Oscillator Configuration

XOIN

0 ~18 pF*

Crystal

Oscillator

XOOUT

0 ~18 pF*

*Capacitor value range depends on

the manufacturer of the XTAL as well

as board layout.

6.3 Frequency Selection

Any frequency within the range specified for the crystal and frequency reference can be used. Since bit timing is derived from the ref-

erence frequency, the CYW20704 must have the reference frequency set correctly in order for any of the USB, UART, and PCM

interfaces to function properly.

The CYW20704 reference frequency can be selected by using BT_XTAL_STRAP_1. The typical crystal frequencies of 20 MHz and

40 MHz are supported.

The GPIO_2 pin needs to be tied to ground when a dedicated Bluetooth crystal is used.

Clock (MHz):XTAL_Strap_1 (Pin-F2)

40: Low

20: High

If the application requires a frequencies other than these, the value can be stored in an external NVRAM. Programming the refer-

ence frequency in NVRAM provides the maximum flexibility in the selection of the reference frequency, since any frequency within

the specified range for crystal and external frequency reference can be used. During power-on reset (POR), the device downloads

the parameter settings stored in NVRAM, which can be programmed to include the reference frequency and frequency trim values.

Typically, this is how a PC Bluetooth application is configured.

6.4 Frequency Trimming

The CYW20704 uses a fractional-N synthesizer to digitally fine-tune the frequency reference input to within ±2 ppm tuning accuracy.

This trimming function can be applied to either the crystal or an reference frequency source. Unlike the typical crystal-trimming meth-

ods used, the CYW20704 changes the frequency using a fully digital implementation and is much more stable and unaffected by

crystal characteristics or temperature. Input impedance and loading characteristics remain unchanged on the crystal during the trim-

ming process and are unaffected by process and temperature variations.

The option to use or not use frequency trimming is based on the system designer’s cost trade-off between bill-of-materials (BOM)

cost of the crystal and the added manufacturing cost associated with frequency trimming. The frequency trimming value can either

be stored in the host and written to the CYW20704 as a vendor-specific HCI command or stored in NVRAM and subsequently

recalled during POR.

Frequency trimming is not a substitute for the poor use of tuning capacitors at an crystal oscillator (XTAL). Occasionally, trimming

can help alleviate hardware changes.

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CYW20704

7. Pin-out and Signal Descriptions

7.1 Pin Descriptions

Table 8. CYW20704 FcBGA Signal Descriptions

FcBGA Pin

(49-Ball)

Signal

I/O

Power Domain

Description

Radio

VDD_RF

Voltage Regulators

N/A

RFOP

A2

A4

A5

I/O

RF I/O antenna port

XO_IN

XO_OUT

I

Crystal or reference input

Crystal oscillator output

O

VBAT

D1

E1

E2

F1

I

VBAT input pin

2.5V LDO input

2.5V LDO output

1.2V LDO output

VDD2P5_IN

VDD2P5_OUT

VDDC_OUT

I

N/A

O

N/A

Straps

BT_XTAL_STRAP_1

F2

I

VDDO

This pin is used as strap for choosing the XTAL

frequencies.

RST_N

A6

G7

I

VDDO

Active-low reset input

BT_TM1

VDDO

Reserved: connect to ground.

Digital I/O

VDDO

BT_GPIO_0

BT_GPIO_1

BT_GPIO_2

F8

F7

E4

I

BT_GPIO_0/BT_DEV_WAKE

Asignal from the host to the CYW20704 device that the

host requires attention.

O

I

VDDO

BT_GPIO_1/BT_HOST_WAKE

A signal from the CYW20704 device to the host

indicating that the Bluetooth device requires attention.

When high, this signal extends the XTAL warm-up time

for external CLK requests. Otherwise, it is typically

connected to ground when a dedicated BT crystal is

used.

BT_GPIO_3

BT_GPIO_4

C5

D6

I/O

VDDO

General-purpose I/O.

General-purpose I/O. It can also be configured as a GCI

pin.

BT_GPIO_5

BT_GPIO_6

BT_GPIO_7

B5

B6

C6

I/O

VDDO

General-purpose I/O. It can also be configured as a GCI

pin.

General-purpose I/O. It can also be configured as a GCI

pin.

General-purpose I/O. It can also be configured as a GCI

pin.

BT_UART_RXD

BT_UART_TXD

BT_UART_RTS_N

BT_UART_CTS_N

BT_CLK_REQ

F5

F4

F3

G4

G8

D8

E8

E7

D7

I/O

O

VDDO

UART receive data

UART transmit data

UART request to send output

UART clear to send input

This pin is used for shared-clock application.

BSC clock

SPI2_MISO_I2S_SCL

SPI2_MOSI_I2S_SDA

SPI2_CLK

I/O

BSC data

Serial flash SPI clock

SPI2_CSN

Serial flash active-low chip select

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CYW20704

Table 8. CYW20704 FcBGA Signal Descriptions (Cont.)

FcBGA Pin

Signal

I/O

Power Domain

Description

(49-Ball)

I2S_DI/PCM_IN

C7

A8

B7

C8

I/O

VDDO

USB

PCM/I2S data input

PCM/I2S data output

PCM/I2S clock

I2S_DO/PCM_OUT

I2S_CLK/PCM_CLK

I2S_WS/PCM_SYNC

I/O

PCM sync/I2S word select

BT_HUSB_DP

BT_HUSB_DN

G2

G3

I/O

VDD_USB

JTAG

USB D+ signal. If not used, connect to GND.

USB D- signal. If not used, connect to GND.

JTAG_SEL

D5

G1

I/O

I

VDDO

Supplies

N/A

Used for debugging

BT_VDD_USB

3.3V USB transceiver supply voltage. If the USB

transport is not needed, connect this pin to GND.

BT_IFVDD1P2

BT_PAVDD2P5

BT_LNAVDD1P2

BT_VCOVDD1P2

BT_PLLVDD1P2

VDDC

B4

A1

B1

C1

A3

I

N/A

Radio IF PLL supply

Radio PA supply

Radio LNA supply

Radio VCO supply

Radio RF PLL supply

Core logic supply

Digital I/O supply voltage

Ground

B8, G6

G5

VDDO

VSS

A7, B2, B3, C2, D2, –

F6

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CYW20704

8. Ball Grid Arrays

Figure 7 shows the top view of the 49-ball 4.5 mm x 4 mm x 0.8 mm (FcBGA).

Figure 7. 4.5 mm x 4 mm x 0.8 mm (FcBGA) Array

Figure 8. Ball-Out for the 49-Ball FcBGA

1

2

3

4

5

6

7

8

BT_

PAVDD2P5

BT_

PLLVDD1P2

I2S_DO/

PCM_OUT

RFOP

XO_IN

XO_OUT

RST_N

VSSC

A

B

C

D

E

F

BT_LNAVDD1

P2

BT_

IFVDD1P2

I2S_CLK/

PCM_CLK

VSS

BT_GPIO_5 BT_GPIO_6

BT_GPIO_3 BT_GPIO_7

VDDC

BT_

VCOVDD1P2

I2S_DI/

PCM_IN

I2S_WS/

PCM_SYNC

SPI2_MISO_

I2C_SCL

VBAT

JTAG_SEL

BT_GPIO_4

SPI2_CSN

SPI2_CLK

VDD2P5_

OUT

SPI2_MOSI_

I2C_SDA

VDD2P5_IN

VDDC_OUT

BT_GPIO_2

BT_GPIO_1/ BT_GPIO_0/

BT_XTAL

_STRAP_1

BT_UART

_RST_N

BT_UART

_TXD

BT_UART

_RXD

VSS

BT_HOST_

WAKE

BT_DEV

_WAKE

BT_VDD

_USB

BT_HUSB

_DP

BT_HUSB

_DN

BT_UART

_CTS_N

BT_CLK

_REQ

VDDO

VDDC

BT_TM1

G

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CYW20704

9. Electrical Characteristics

Note: All voltages listed in Table 9 are referenced to V_DD

.

Table 9. Absolute Maximum Voltages

Requirement Parameter

Specification

Nominal

Units

Minimum

Maximum

Ambient Temperature of Operation

Storage temperature

ESD Tolerance HBM

ESD Tolerance MM

ESD Tolerance CDM

Latch-up

–30

–40

25

85

°C

V

–

150

–2000

–100

–500

–200

1.14

3

–

2000

100

500

200

1.26

3.6

–

V

–

V

–

mA

V

VDD Core

1.2

3.3

1.2

2.5

VDD IO

V

VDD RF (excluding class 1 PA)

VDD PA (class 1 mode)

1.14

2.25

1.26

2.75

V

Table 10. Power Supply Specifications

Parameter

Conditions

Min.

Typ.

Max.

Units

VBAT input

–

3.0

3.3

3.6

V

2.5V LDO input

Table 11. VDDC LDO Electrical Specifications

Parameter

Conditions

Min.

Typ.

Units

Input Voltage

–

3.0

–

3.3

3.6

V

Nominal Output

Voltage

1.2

–

DC Accuracy

–

–5

–

5

%

Load Current

–

40

200

0.2

–

mA

mV

%Vo/V

μA

Dropout Voltage

Line Regulation

I

_load= 40 mA

–

Vin from 1.62V to 3.6V, I_load= 40 mA

–

Power Down Current Vin = 3.3V @25C

–

0.2

–

Over Current Limit

–

100

0.8

–

mA

μF

External Output

Capacitor

Ceramic cap with ESR ≤0.5Ω

1

4.7

External Input

Capacitor

Ceramic, X5R, 0402, ±20%, 10V.

–

1

–

μF

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CYW20704

Table 12. BTLDO_2P5 Electrical Specifications

Parameters

Conditions

Min = Vo + 0.2V = 2.7V

(for Vo = 2.5V)

Dropout voltage requirement must be met

under maximum load for performance

specs.

Min

Typ

Max

Units

Input supply voltage,

Vin

3.0

3.3

3.6

–

V

Nominal output

voltage, Vo

Default = 2.5V

–

2.5

–

V

Output voltage

programmability

Range

2.2

2.8

5

V

%

Accuracy at any step (including line/load –5

regulation), load >0.1 mA

Dropout voltage

Output current

At max load

–

200

70

mV

mA

μA

Quiescent current

No load; Vin = Vo + 0.2V

8

16

Max load @ 70 mA; Vin = Vo + 0.2V

660

700

Leakage current

Power-down mode. At junction

temperature 85°C.

–

1.5

2.2

1

5

μA

μF

External output

capacitor, Co

Ceramic, X5R, 0402, (ESR: 5m-240 mΩ), 0.7

±20%, 6.3V

2.64

–

External input

capacitor

Ceramic, X5R, 0402, ±20%, 10V

–

Table 13. Digital I/O Characteristics

Characteristics

Input low voltage (VDDO = 3.3V)

Input high voltage (VDDO = 3.3V)

Output low voltage

Symbol

V_IL

Minimum

Typical

Maximum

Unit

–

0.8

–

V

V_IH

V_OL

V_OH

I_IL

2.0

–

V

0.4

–

V

Output high voltage

VDDO – 0.4V

V

Input low current

–

1.0

2.0

0.4

μA

mA

pF

Input high current

I_IH

Output low current (VDDO = 3.3V, V_OL= 0.4V)

Output high current (VDDO = 3.3V, V_OH= 2.9V)

Input capacitance

I_OL

I_OH

C_IN

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CYW20704

Table 14. USB/UART Interface Level

Parameter

I/O supply voltage

Symbol

Minimum

3.0

Typical

Maximum

Unit

VDD_USB/VDDO

–

3.6

500

–

V

Supply current

Icchpf

Vih

–

mA

V

Input high voltage (driven)

Input high voltage (floating)

Input low voltage

Differential input sensitivity^a

Differential common-mode range^a

Output low voltage

2.0

2.7

–

Vihz

Vil

3.6

0.8

–

V

Vdi

0.2

0.8

0.0

2.8

1.3

V

Vcm

Vol

2.5

0.3

3.6

2.0

V

Output high voltage (driven)

Output signal crossover voltage^a

Voh

Vcrs

V

a. Applies to USB only.

Table 15. Bluetooth and BLE Current Consumption

Operating Mode

VBAT (VBAT=3.6V) Typical

Units

Sleep

114

μA

Standard 1.28s Inquiry Scan

500 ms Sniff Master (–4 Att)

DM1/DH1 Master

DM3/DH3 Master

DM5/DH5 Master

3DH5/3DH1 Master

SCO HV3 Master

BLE SCAN^a

334

μA

900

μA

32.15

38.14

38.46

25.94

14.64

355

mA

μA

BLE ADV: Unconnectable 1.00 sec

BLE Connected 1 sec

176

835

μA

Note: Current measurements were done with 12 dBm TX power for GFSK and 9 dBm TX power for EDR and BLE.

a. No devices present. A 1.28 second interval with a scan window of 11.25 ms.

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CYW20704

9.1 RF Specifications

Table 16. Receiver RF Specifications^{a, b}

Parameter

General

Conditions

Minimum

Typical ^c

Maximum

Unit

MHz

Frequency range

RX sensitivity ^d

–

2402

–

2480

–

GFSK, 0.1% BER, 1 Mbps

/4-DQPSK, 0.01% BER, 2 Mbps

8-DPSK, 0.01% BER, 3 Mbps

GFSK, 1 Mbps

–

–93.5

–95.5

–89.5

–

dBm

–

Maximum input

–20

Maximum input

/4-DQPSK, 8-DPSK, 2/3 Mbps

–

Interference Performance

■ GFSK Modulation^e

C/I cochannel

GFSK, 0.1% BER

–

9.5

–5

11

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I > 3 MHz adjacent channel

C/I image channel

0

–40

–49

–27

–37

–30.0

–40.0

–9.0

–20.0

C/I 1 MHz adjacent to image channel GFSK, 0.1% BER

■ QPSK Modulation^f

C/I cochannel

/4-DQPSK, 0.1% BER

–

11

13

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I > 3 MHz adjacent channel

C/I image channel

/4-DQPSK, 0.1% BER

8-DPSK, 0.1% BER

–8

0

–40

–50

–27

–40

–30.0

–40.0

–7.0

–20.0

/4-DQPSK, 0.1% BER

^{C/I 1 MHz adjacent to image channel}/4-DQPSK, 0.1% BER

■ 8PSK Modulation^g

C/I cochannel

8-DPSK, 0.1% BER

–

17

21

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I > 3 MHz adjacent channel

C/I Image channel

–5

5

–40

–47

–20

–35

–25.0

–33.0

0

C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER

–13.0

Out-of-Band Blocking Performance (CW) ^h

30 MHz–2000 MHz

2000–2399 MHz

0.1% BER

–

–10.0

–27

–

dBm

2498–3000 MHz

–27

3000 MHz–12.75 GHz

–10.0

Document Number: 002-14786 Rev. *E

Page 27 of 49

CYW20704

Table 16. Receiver RF Specifications^{a, b}(Cont.)

Parameter

Conditions

Minimum

Typical ^c

–10 ⁱ

Maximum

Unit

dBm

Out-of-Band Blocking Performance, Modulated Interferer

776–764 MHz

824–849 MHz

1850–1910 MHz

824–849 MHz

880–915 MHz

1710–1785 MHz

1850–1910 MHz

1920–1980 MHz

CDMA

–

CDMA

–

–10 ⁱ

–23 ⁱ

–10 ⁱ

–23 ⁱ

dBm

CDMA

EDGE/GSM

WCDMA

Intermodulation Performance ^j

BT, Df = 4 MHz

–

–39.0

–

dBm

Spurious Emissions ^k

30 MHz to 1 GHz

1–12.75 GHz

–

–62

–47

–

dBm

–

dBm

65–108 MHz

FM RX

CDMA

EDGE/GSM

PCS

–147

dBm/Hz

746–764 MHz

–

851–894 MHz

–

925–960 MHz

–

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

–

WCDMA

–

a. All specifications are single ended. Unused inputs are left open.

b. All specifications, except typical, are for industrial temperatures.

c. Typical operating conditions are 3.3V VBAT and 25°C ambient temperature. The final TX power depends on the insertion loss due to the

connector and the antenna. Typically, less than 2 dB. However, the actual value depends on the connector and antenna and must be

measured. The stated number is for chip output power.

d. The receiver sensitivity is measured at BER of 0.1% on the device interface.

e. Typical GFSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –45 dB, –42 dB, and –41 dB, respectively.

f.

Typical QPSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –46 dB, –43 dB, and –42 dB, respectively.

g. Typical 8PSK CI numbers at –7 MHz, –5 MHz, and –3 MHz are –50 dB, –45 dB, and –45 dB, respectively.

h. Meets this specification using front-end band pass filter.

i.

j.

Numbers are referred to the pin output with an external BPF filter.

f0 = -64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 –

f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.

k. Includes baseband radiated emissions.

Document Number: 002-14786 Rev. *E

Page 28 of 49

CYW20704

Table 17. Transmitter RF Specifications ^{a b}

Parameter

General

Conditions

Minimum

Typical

Maximum

Unit

MHz

Frequency range

–

2402

–

2480

Class1: GFSK TX power ^c

Class1: EDR TX power ^d

Class 2: GFSK TX power

Power control step

–

2

12

9

–

8

dBm

dB

2

4

Modulation Accuracy

/4-DQPSK Frequency Stability

/4-DQPSK RMS DEVM

/4-QPSK Peak DEVM

/4-DQPSK 99% DEVM

8-DPSK frequency stability

8-DPSK RMS DEVM

8-DPSK Peak DEVM

8-DPSK 99% DEVM

–

–10

–

10

20

35

30

10

13

25

20

kHz

%

–

%

–

%

–10

–

kHz

%

–

%

–

%

In-Band Spurious Emissions

1.0 MHz < |M – N| < 1.5 MHz

1.5 MHz < |M – N| < 2.5 MHz

|M – N| > 2.5 MHz

–

–26

–20

–40

dBc

dBm

Out-of-Band Spurious Emissions

30 MHz to 1 GHz

–

–36.0 ^e

–30.0 ^{e, f}

–47.0

dBm

1–12.75 GHz

1.8–1.9 GHz

5.15–5.3 GHz

–47.0

GPS Band Noise Emission (without a front-end band pass filter)

1572.92 MHz to 1577.92 MHz

Out-of-Band Noise Emissions (without a front-end band pass filter)

–

–150

–127

dBm/Hz

65–108 MHz

FM RX

–

–145

–140

–

dBm/Hz

746–764 MHz

869–960 MHz

925–960 MHz

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

CDMA

EDGE/GSM

PCS

WCDMA

a. All specifications are for industrial temperatures.

b. All specifications are single-ended. Unused input are left open.

c. +12 dBm output for GFSK measured with PA VDD = 2.5V.

d. +9 dBm output for EDR measured with PA VDD = 2.5V.

e. Maximum value is the value required for Bluetooth qualification.

f.

Meets this spec using a front-end bandpass filter.

Document Number: 002-14786 Rev. *E

Page 29 of 49

CYW20704

Table 18. BLE RF Specifications

Parameter

Frequency Range

RX Sense^a

Conditions

Minimum

Typical

Maximum

Unit

MHz

n/a

2402

–

2480

GFSK, 0.1% BER, 1 Mbps

–96

9

–

dBm

kHz

%

TX Power^b

n/a

–

Mod Char: Delta F1 average

Mod Char: Delta F2 max^c

Mod Char: Ratio

225

99.9

0.8

255

–

275

–

0.95

–

%

a. Dirty TX is Off.

b. The BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm

out. The BLE TX power at the antenna port cannot exceed the 10 dBm EIRP specification limit.

c. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.

Document Number: 002-14786 Rev. *E

Page 30 of 49

CYW20704

9.2 Timing and AC Characteristics

In this section, use the numbers listed in the reference column to interpret the timing diagrams.

9.2.1 Startup Timing

The global reset signal in the CYW20704 is a logical OR (actually a wired AND, since the signals are active low) of the RST_N input

and the internal POR signals. The last signal to be released determines the time at which the chip is released from reset. The POR

is typically asserted for 2.4 ms after the POR threshold is crossed.

The following two figures illustrate two startup timing scenarios.

Figure 9. Startup Timing

ꢀ3.96 ms

VDDO

~ 2.4 ms

VDDO POR

0.5 ms

VDDC

7.5 ms

VDDC Reset

VDDC Reset/Share XTAL

9.2.2 USB Full-Speed Timing

Table 19 through Table 10 shows timing specifications for VDD_USB = 3.3V, V = 0V, and T = 0°C to 85°C operating

SS

A

temperature range.

Table 19. USB Full-Speed Timing Specifications

Reference

Characteristics

Minimum

Maximum

20

Unit

1

2

3

4

Transition rise time

Transition fall time

4

ns

%

20

Rise/fall timing matching

Full-speed data rate

90

12 – 0.25%

111

12 + 0.25%

Mb/s

Figure 10. USB Full-Speed Timing

2

1

D+

90%

V_CRS

10%

D-

Document Number: 002-14786 Rev. *E

Page 31 of 49

CYW20704

9.2.3 UART Timing

Table 20. UART Timing Specifications

Ref No.

Characteristics

Minimum

Typical

Maximum

Unit

1

2

3

Delay time

UART_CTS_N low to UART TXD valid.

–

1.50

0.67

1.33

Bit periods

Setup time

Bit periods

UART_CTS_N high before midpoint of stop bit.

Delay time

Midpoint of stop bit to UART_RTS_N high.

Figure 11. UART Timing

UART_CTS_N

1

2

UART_TXD

Midpoint of STOP bit

UART_RXD

3

UART_RTS_N

Document Number: 002-14786 Rev. *E

Page 32 of 49

CYW20704

9.2.4 PCM Interface Timing

Short Frame Sync, Master Mode

Figure 12. PCM Timing Diagram (Short Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM_SYNC

8

PCM_OUT

5

HIGH IMPEDANCE

7

6

PCM_IN

Table 21. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)

Ref No. Characteristics Minimum

Typical

Maximum

12

Unit

MHz

1

2

3

4

5

6

7

8

PCM bit clock frequency

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

–

41

0

–

ns

–

25

–

0

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit period to

PCM_OUT becoming high impedance

0

25

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CYW20704

Short Frame Sync, Slave Mode

Figure 13. PCM Timing Diagram (Short Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

4

5

PCM_SYNC

PCM_OUT

9

HIGH IMPEDANCE

8

6

7

PCM_IN

Table 9-14. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)

Ref No. Characteristics Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

8

9

PCM bit clock frequency

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

–

12

–

41

8

ns

–

8

–

0

25

–

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit period to

PCM_OUT becoming high impedance

0

25

Document Number: 002-14786 Rev. *E

Page 34 of 49

CYW20704

Long Frame Sync, Master Mode

Figure 14. PCM Timing Diagram (Long Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

8

HIGH IMPEDANCE

Bit 0

Bit 1

5

7

6

PCM_IN

Table 22. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)

Ref No. Characteristics Minimum

Typical

Maximum

12

Unit

MHz

1

2

3

4

5

6

7

8

PCM bit clock frequency

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

–

41

0

–

ns

–

25

–

0

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit period to

PCM_OUT becoming high impedance

0

25

Document Number: 002-14786 Rev. *E

Page 35 of 49

CYW20704

Long Frame Sync, Slave Mode

Figure 15. PCM Timing Diagram (Long Frame Sync, Slave Mode

1

2

3

PCM_BCLK

4

5

PCM_SYNC

9

PCM_OUT

PCM_IN

Bit 0

HIGH IMPEDANCE

8

Bit 1

6

7

Table 23. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)

Ref No. Characteristics Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

8

9

PCM bit clock frequency

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

–

12

–

41

8

ns

–

8

–

0

25

–

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit period to

PCM_OUT becoming high impedance

0

25

Document Number: 002-14786 Rev. *E

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CYW20704

Short Frame Sync, Burst Mode

Figure 16. PCM Burst Mode Timing (Receive Only, Short Frame Sync)

1

2

3

PCM_BCLK

PCM_SYNC

4

5

7

6

PCM_IN

Table 24. PCM Burst Mode (Receive Only, Short Frame Sync)

Ref No. Characteristics

Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

PCM bit clock frequency

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_IN setup

–

24

–

20.8

8

–

ns

–

8

–

8

–

PCM_IN hold

8

–

Document Number: 002-14786 Rev. *E

Page 37 of 49

CYW20704

Long Frame Sync, Burst Mode

Figure 17. PCM Burst Mode Timing (Receive Only, Long Frame Sync)

1

2

3

PCM_BCLK

PCM_SYNC

4

5

7

6

Bit 0

PCM_IN

Bit 1

Table 25. PCM Burst Mode (Receive Only, Long Frame Sync)

Ref No. Characteristics

Minimum

Typical

Maximum

Unit

MHz

1

2

3

4

5

6

7

PCM bit clock frequency

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_IN setup

–

24

–

20.8

8

–

ns

–

8

–

8

–

PCM_IN hold

8

–

Document Number: 002-14786 Rev. *E

Page 38 of 49

CYW20704

2

9.3 I S Interface

The CYW20704 supports two independent I²S digital audio ports. The I²S interface supports both master and slave modes. The I²S

signals are:

■ I²S clock: I²S SCK

■ I²S Word Select: I²S WS

■ I²S Data Out: I²S SDO

■ I²S Data In: I²S SDI

I²S SCK and I²S WS become outputs in master mode and inputs in slave mode, while I²S SDO always stays as an output. The

channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I²S bus,

per the I²S specification. The MSB of each data word is transmitted one bit clock cycle after the I²S WS transition, synchronous with

the falling edge of bit clock. Left-channel data is transmitted when I²S WS is low, and right-channel data is transmitted when I²S WS

is high. Data bits sent by the CYW20704 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver

on the rising edge of I2S_SSCK.

The clock rate in master mode is either of the following:

48 kHz x 32 bits per frame = 1.536 MHz

48 kHz x 50 bits per frame = 2.400 MHz

The master clock is generated from the input reference clock using a N/M clock divider.

In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.

Document Number: 002-14786 Rev. *E

Page 39 of 49

CYW20704

9.3.1 I²S Timing

Note: Timing values specified in Table 26 are relative to high and low threshold levels.

Table 26. Timing for I²S Transmitters and Receivers

Transmitter

Receiver

Lower Limit Upper Limit

Min Max

Lower LImit

Min Max

Upper Limit

Min Max

Notes

Min

Max

a

Clock Period T

T

–

T

–

tr

r

Master Mode: Clock generated by transmitter or receiver

b

HIGH t_HC

LOWt_LC

0.35T

–

0.35T

–

tr

Slave Mode: Clock accepted by transmitter or receiver

c

d

HIGH t_HC

–

0.35T

–

0.35T

–

tr

LOW t_LC

Rise time t_RC

0.15T

tr

Transmitter

e

d

Delay t_dtr

–

0

–

0.8T

–

Hold time t_htr

–

Receiver

f

Setup time t_sr

Hold time t_hr

–

0.2T

0

–

r

a. The system clock period T must be greater than T_trand T_rbecause both the transmitter and receiver have to be able to handle the data

transfer rate.

b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t_HCand

t_LCare specified with respect to T.

c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal.

So long as the minimum periods are greater than 0.35T_r, any clock that meets the requirements can be used.

d. Because the delay (t_dtr) and the maximum transmitter speed (defined by T_tr) are related, a fast transmitter driven by a slow clock edge can

result in t_dtrnot exceeding t_RCwhich means t_htrbecomes zero or negative. Therefore, the transmitter has to guarantee that t_htris greater

than or equal to zero, so long as the clock rise-time t_RCis not more than t_RCmax, where t_RCmaxis not less than 0.15T_tr.

e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving

the receiver sufficient setup time.

f.

The data setup and hold time must not be less than the specified receiver setup and hold time.

Note: The time periods specified in Figure 18 and Figure 19 are defined by the transmitter speed. The receiver specifications must

match transmitter performance.

Document Number: 002-14786 Rev. *E

Page 40 of 49

CYW20704

Figure 18. I²S Transmitter Timing

T

t_RC*

t_LC> 0.35T

t_HC> 0.35T

V_H= 2.0V

V_L= 0.8V

SCK

t_htr> 0

t_otr< 0.8T

SD and WS

T = Clock period

T_tr= Minimum allowed clock period for transmitter

T = T_tr

* t_RCis only relevant for transmitters in slave mode.

Figure 19. I²S Receiver Timing

T

t_LC> 0.35T

t_HC> 0.35

V_H= 2.0V

V_L= 0.8V

SCK

t_sr> 0.2T

t_hr> 0

SD and WS

T = Clock period

T_r= Minimum allowed clock period for transmitter

T > T_r

Document Number: 002-14786 Rev. *E

Page 41 of 49

CYW20704

9.3.2 BSC Interface Timing

Figure 20 and Table 27 define the timing requirements for the BSC interface.

Figure 20. BSC Interface Timing Diagram

1

5

SCL

2

4

7

8

6

3

SDA

IN

10

9

SDA

OUT

Table 27. BSC Interface Timing Specifications

Reference Characteristics

Minimum

Maximum

100

Unit

kHz

1

Clock frequency

–

400

800

1000

2

3

4

5

6

7

8

9

START condition setup time

START condition hold time

Clock low time

650

280

650

280

0

–

ns

–

Clock high time

–

Data input hold time^a

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time^b

–

100

280

–

400

–

10

650

a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions

b. Time that the cbus must be free before a new transaction can start.

Document Number: 002-14786 Rev. *E

Page 42 of 49

CYW20704

9.3.3 SPI Timing

The SPI interface can be clocked up to 12 MHz.

Figure 21 and Table 28 define the timing requirements when operating in SPI Mode 0 and 2.

Figure 21. SPI Timing, Mode 0 and 2

5

SPI_CSN

SPI_INT

(DirectWrite)

SPI_INT

(DirectRead)

1

SPI_CLK

(Mode 0)

SPI_CLK

(Mode 2)

2

First Bit

Second Bit

Last bit

SPI_MOSI

SPI_MISO

First Bit

Not Driven

Table 28. SPI Mode 0 and 2

Reference

Characteristics

Minimum

Maximum

Unit

ns

1

2

3

4

5

Time from master assert SPI_CSN to first clock edge

Hold time for MOSI data lines

45

–

12

½ SCK

100

ns

Time from last sample on MOSI/MISO to slave deassert SPI_INT

Time from slave deassert SPI_INT to master deassert SPI_CSN

Idle time between subsequent SPI transactions

0

–

1 SCK

–

Document Number: 002-14786 Rev. *E

Page 43 of 49

CYW20704

Figure 22 and Table 29 define the timing requirements when operating in SPI Mode 1 and 3.

Figure 22. SPI Timing, Mode 1 and 3

SPI_CSN

5

SPI_INT

(DirectWrite)

3

4

SPI_INT

(DirectRead)

SPI_CLK

1

(Mode 1)

SPI_CLK

(Mode 3)

2

Invalid bit

First bit

Last bit

SPI_MOSI

SPI_MISO

Not Driven

Table 29. SPI Mode 1 and 3

Reference

Characteristics

Minimum

Maximum

Unit

ns

1

2

3

Time from master assert SPI_CSN to first clock edge

Hold time for MOSI data lines

45

12

0

–

½ SCK

100

ns

Time from last sample on MOSI/MISO to slave

deassert SPI_INT

4

5

Time from slave deassert SPI_INT to master

deassert SPI_CSN

0

–

ns

Idle time between subsequent SPI transactions

1 SCK

Document Number: 002-14786 Rev. *E

Page 44 of 49

CYW20704

10. Mechanical Information

Figure 23. 49-Ball FcBGA Mechanical Drawing

Document Number: 002-14786 Rev. *E

Page 45 of 49

CYW20704

10.1 Tape, Reel, and Packing Specification

Figure 24. Reel, Labeling, and Packing Specification

Device Orientation/Mix Lot Number

Each reel may contain up to three lot numbers, independent of the date code.

Individual lots must be labeled on the box, moisture barrier bag, and the reel.

Pin 1

Top‐right corner toward sprocket holes.

?

Moisture Barrier Bag Contents/Label

Desiccant pouch (minimum 1)

Humidity indicator (minimum 1)

Reel (maximum 1)

Document Number: 002-14786 Rev. *E

Page 46 of 49

CYW20704

11. Ordering Information

Table 30 provides the available part number and its ordering information. This package is rated from –30°C to +85°C.

Table 30. Ordering Information

Part Number

Package Description

CYW20704UA2KFFB1G

Commercial 49-ball FcBGA, 4.5 mm x 4.0 mm x 0.8 mm, RoHS-compliant, halogen-free

Document Number: 002-14786 Rev. *E

Page 47 of 49

CYW20704

Document History

Document Title: CYW20704 Single-Chip Bluetooth Transceiver and Baseband Processor

Document Number: 002-14786

Orig. of Submission

Revision

ECN

Description of Change

Change

Date

**

–

04/22/2015

20704-DS100-R

Initial release

20704-DS101-R

Updated:

*A

*B

*C

*D

*E

–

11/06/2015

02/18/2016

02/29/2016

03/18/2016

09/29/2016

•

Table 6-1: “Crystal Interface Signal Characteristics,” on page 20

–

20704-DS102-R

Updated:

•

Table 11-1: “Ordering Information,” on page 48

–

20704-DS103-R

Added:

•

“Recommended BT Coexistence Interface Assignments” on page 13

UTSV

20704-DS104-R

Updated:

•

Table 9-8: “Receiver RF Specifications” on page 28

5445323

Updated to Cypress Template

Document Number: 002-14786 Rev. *E

Page 48 of 49

CYW20704

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

Lighting & Power Control

Memory

cypress.com/support

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

49

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-14786 Rev. *E

Revised September 29, 2016

Page 49 of 49

型号	制造商	描述	价格	文档
BCM20705	CYPRESS	Single-Chip Bluetooth Transceiver and Baseband Processor	获取价格
BCM20705A1KWFBG	CYPRESS	Single-Chip Bluetooth Transceiver and Baseband Processor	获取价格
BCM20705A1KWFBGT	CYPRESS	Single-Chip Bluetooth Transceiver and Baseband Processor	获取价格
BCM20705B0KWFBG	CYPRESS	Single-Chip Bluetooth Transceiver and Baseband Processor	获取价格
BCM20705B0KWFBGT	CYPRESS	Single-Chip Bluetooth Transceiver and Baseband Processor	获取价格
BCM20706	CYPRESS	Embedded Bluetooth 4.2 SoC with MCU, Bluetooth Transceiver, and Baseband Processor	获取价格
BCM20706UA1KFFB1G	CYPRESS	Embedded Bluetooth 4.2 SoC with MCU, Bluetooth Transceiver, and Baseband Processor	获取价格
BCM20706UA1KFFB4G	CYPRESS	Telecom Circuit, 1-Func, CMOS, PBGA49, 4.50 X 4 MM, ROHS COMPLIANT, FBGA-49	获取价格
BCM20707	CYPRESS	Complies with Bluetooth Core Specification version 4.2 including BR/EDR/BLE	获取价格
BCM20707UA1KFFB1G	CYPRESS	Complies with Bluetooth Core Specification version 4.2 including BR/EDR/BLE	获取价格

BCM20704UA2KFFB1G

BCM20704UA2KFFB1G 概述

BCM20704UA2KFFB1G 数据手册

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