BCM4325GKWBG [CYPRESS]
Telecom Circuit, 1-Func, PBGA339, WLCSP-339;
| 型号： | BCM4325GKWBG |
| 厂家： | 
CYPRESS |
| 描述： | Telecom Circuit, 1-Func, PBGA339, WLCSP-339 电信 电信集成电路 |
| 文件： | 总139页 (文件大小：2480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products. Although the document is marked with the name
“Broadcom”, the company that originally developed the specification, Cypress will continue to offer these products to
new and existing customers.
CONTINUITY OF SPECIFICATIONS
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have
been made are the result of normal document improvements and are noted in the document history page, where
supported. Future revisions will occur when appropriate, and changes will be noted in a document history page.
CONTINUITY OF ORDERING PART NUMBERS
Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part
Numbers listed in this document.
FOR MORE INFORMATION
Please visit our website at www.cypress.com or contact your local sales office for additional information about
Cypress products and services.
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ABOUT CYPRESS
Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative
automotive, industrial, home automation and appliances, consumer electronics and medical products. Cypress’s
programmable systems-on-chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity
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Cypress Semiconductor Corporation
Document Number: 002-15049 Rev. *
198 Champion Court
San Jose, CA 95134-1709
408-943-2600
Revised July 1, 2016
Revised September 19, 2016
*E
PRELIMINARY DATA SHEET
BCM4325
IEEE 802.11 a/b/g MAC/Baseband/Radio Plus
Bluetooth 3.0 + HS and FM Receiver Single-Chip
Combination
GENERAL DESCRIPTION
The Broadcom® BCM4325 single-chip device provides
the highest level of integration for a mobile or handheld
wireless systems with integrated IEEE 802.11™ a/b/g
MAC/baseband/radio, Bluetooth® 3.0 + HS and a FM
radio receiver.
InConcert provides the highest possible degree of
collaboration between Bluetooth® and WLAN using a
shared 2.4 GHz antenna, along with coexistence support
for external radio technologies such as GPS, WiMax and
Ultra Wide-Band (UWB).
Designed to address the needs of highly mobile devices
that require minimal power consumption and board area,
the BCM4325 provides a compact ultra-small form-factor
solution with minimal external components. This solution
drives down the costs of mass volumes, while allowing for
flexibility in the size, form, and function of handheld
devices.
As a result, the overall quality of simultaneous voice,
video, and data transmission on a handheld system is
enhanced while minimizing the PCB footprint.
Designed to support flexible power supply topologies,
including operation directly from the rechargeable battery
in a mobile platform, the BCM4325 integrates a power
management unit with five LDOs and two switching
regulators.
Utilizing advanced design techniques and process
technologies to deliver low active and idle power, the
BCM4325 extends system battery life while maintaining
consistent connectivity and high throughput.
The integrated CMOS WLAN 2.4 GHz and 5 GHz power
amplifiers provide sufficient output power to meet the
needs of most WLAN devices, without the need for an
external PA. Furthermore, the integrated buck-boost
regulator allows the internal power amplifiers to operate
at optimal performance, even at low Vbatt supply
voltages. Transmit and receive baluns are also integrated.
An SDIO system interface (4b, 1b, or SPI) is provided for
WLAN and an independent, high-speed UART is
provided for the Bluetooth section.
A unique feature of the BCM4325 is its implementation of
highly sophisticated InConcert™ (IEEE 802.15.2) radio
coexistence algorithms and hardware mechanisms.
Vbatt
VIO
WL_RST_N
WLAN Host I/F
5 GHz WLAN Tx
SW
5 GHz WLAN Rx
SDIO
WL_WAKE_N1
WL_HOST_WAKE_N1
BT_RST_N
UART
I2S
2.4 GHz WLAN Tx
2.4 GHz WLAN/BT Rx
Bluetooth Tx
Bluetooth Host I/F
FM Host I/F
SW
CBF
BCM4325
PCM
BT_WAKE1
BT_HOST_WAKE1
BSC2
FM Rx
FM_IRQ1, 3
Ref Frequency
TCXO
LPO Clock
32.768 kHz
Notes: 1. Indication for optional GPIO functions.
2. BSC is Phillips® I2C-compatible.
3. For information on the FM_IRQ signal, refer to the following Broadcom documents:
BCM4325 FM_RDS Block Setup Quick Start Guide (4325-QSG100-X) and
FM Command and Control Specification (4325-AN400-X).
Figure 1: Functional Block Diagram
4325-DS04-R
6/30/09
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203
BCM4325
Preliminary Data Sheet
6/30/09
FEATURES
•
Security
General Features
-
-
-
-
-
WPA™ and WPA2™ (Personal) support for powerful
encryption and authentication
•
•
•
Supports a battery voltage ranging from 2.3V to
5.5V with the internal buck-boost switching
regulator
AES and TKIP acceleration hardware for faster data
encryption and 802.11i compatibility
Cisco® Compatible Extension—(CCX, CCX 2.0, CCX 3.0,
CCX 4.0) certified
SecureEasySetup™ for simple Wi-Fi® setup and WPA2/
WPA security configuration
Low power consumption and dynamic power
management maximize battery life of handheld
devices
Five LDO regulators and two switching regulators
with an on-chip, programmable power
management unit
Wi-Fi Protected Setup (WPS)
•
•
Supports IEEE 802.11d, e (WMM, QoS, WMM-PS), h, i, j (k, r,
and w in the future)
•
•
•
Integrated CMOS power amplifiers deliver greater
than 20 dBm of linear output power
Worldwide regulatory support – Global products supported
with worldwide homologated design
Supports a single 2.4 GHz antenna shared
between WLAN and Bluetooth
Bluetooth Features
Internal fractional nPLL allows support for a wide
range of reference clock frequencies.
•
Bluetooth Core specification 3.0 + HS compliant when
combined with Bluetooth 3.0 + HS qualified host software,
including Alternate MAC/PHY, read encryption key size,
enhanced power control, and unicast connectionless data.
•
•
2k-bit OTP for storing board parameters
196-ball flip-chip FBGA package (7.5 mm x
7.5 mm x 1.05 mm, 0.5 mm pitch) and 339-pin
WLCSP package (6.51 mm x 5.81 mm x 0.42 mm,
0.25 mm pitch). Dimensions are nominal, see
Figure 35 on page 115 and Figure 36 on page 116
for maximum dimensions)
•
•
Supports extended Synchronous Connections (eSCO), for
enhanced voice quality by allowing for retransmission of
dropped packets
Adaptive Frequency Hopping (AFH) for reducing radio
frequency interference
•
Provides an ultra-small form-factor solution and
ultra low-power consumption to support low-cost
requirements
•
•
Bluetooth Class 1 support with PA bias adjust
Interface support—Host Controller Interface (HCI) using a
high-speed UART interface and PCM for audio data
IEEE 802.11x Features
•
•
•
•
Integrates the InConcert collaborative WLAN coexistence,
including the 802.15.2 3-wire coexistence support
•
Single-band 2.4 GHz 802.11 b/g or dual-band
2.4 GHz and 5 GHz 802.11 a/b/g pin-compatible
options
Supports dual Advanced Audio Distribution Profile (A2DP) for
stereo sound
•
•
Integrated WLAN CMOS power amplifiers deliver
greater than 20 dBm of linear output power.
Automatic frequency detection for standard crystal and TCXO
values
Provides
external
coexistence handshake
interface to support additional wireless
technologies such as GPS, WiMax, or UWB
Embedded ARM7 RISC processor and on-chip memory
FM Radio Features
•
•
Supports SDIO v1.2 (4-bit and 1-bit) and SPI, with
SDIO clock speeds up to 50 MHz
•
FM receiver
-
-
76 MHz to 108 MHz FM bands
Integrated ARM7® RISC processor and on-chip
memory for complete WLAN subsystem
functionality minimizing the need to wake up the
applications processor for standard WLAN
functions. This allows for further minimization of
power consumption, while maintaining the
capability to field upgrade with future features.
European Radio Data Systems (RDS) and
North American Radio Broadcast Data System (RBDS)
modulation support
•
•
•
I2C-compatible BSC communications support
Stereo analog output
I2S and PCM interfaces
Broadcom Corporation
Page ii
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
REVISION HISTORY
Revision
Date
Description
4325-DS04-R
6/30/09
Updated:
• Title
• “General Decsription: on page i
• “Bluetooth Features” on page ii
• “Overview” on page 1
• Table 2, ”Crystal Interface Signal Characteristics,” on page 6
• Table 3, ”LPO Signal Requirements,” on page 9
• “Bluetooth Features” on page 11
• “Bluetooth 2.1 and 3.0 Features” on page 14
• “Bluetooth UART Interface” on page 20
• “One-Time-Programmable (OTP) Memory” on page 33
• “JTAG Interface” on page 34
• Table 8, ”196-Ball FBGA Signal Descriptions,” on page 43
• Table 9, ”339-Pin WLCSP Signal Descriptions,” on page 52
• Table 14, ”WLAN GPIO Functions and Strapping Options,” on page 67
• Table 21, ”ESD Specifications,” on page 75
• Table 22, ”Environmental Ratings,” on page 76
• Table 23, ”Recommended Operating Conditions and DC Characteristics,” on page 76
• “WLAN Receiver Blocking Performance” on page 86
• “SDIO Host Timing Requirement” on page 107
• Table 57, ”Ordering Information,” on page 120
4325-DS03-R
3/11/09
Updated:
• General Description on page i
• Features on page ii
• “Overview” on page 1
• “Mobile Phone Usage Model” on page 2
• “Power Supply Topology” on page 4
• “Reset Circuits” on page 5
• “Crystal Interface and Clock Generation” on page 6
• Table 2, ”Crystal Interface Signal Characteristics,” on page 6
• Figure 6, ”Recommended Oscillator Configuration,” on page 7
• “Frequency Selection” on page 8
• Table 3, ”LPO Signal Requirements,” on page 9
• “Broadcom Serial Control (BSC) Bus” on page 23
• Table 6, ”196-Ball FBGA Signal Assignments by Ball Number,” on page 37
• Table 7, ”339-Pin WLCSP Signal Assignments by Pin Number and X- and Y-Coordinates,”
on page 39
• Table 8, ”196-Ball FBGA Signal Descriptions,” on page 43
• Table 9, ”339-Pin WLCSP Signal Descriptions,” on page 53
• Table 14, ”WLAN GPIO Functions and Strapping Options,” on page 68
• Table 15, ”BT GPIO Signals,” on page 69
• Table 17, ”BT/FM Interface I/O Status,” on page 72
• Table 18, ”WLAN Interface I/O Status,” on page 74
• Table 20, ”Absolute Maximum Ratings,” on page 76
Broadcom Corporation
Document 4325-DS04-R
Page iii
BCM4325
Preliminary Data Sheet
6/30/09
Revision
Date
Description
• Section 16 ”Operating Conditions and DC Characteristics” on page 76 (title changed; was
DC Characteristics)
• Section ”Recommended Operating Conditions” on page 77 (heading changed; was DC
Characteristics)
• Table 21, ”ESD Specifications,” on page 76
• Table 22, ”Environmental Ratings,” on page 77
• Table 23, ”Recommended Operating Conditions and DC Characteristics,” on page 77
• Table 24, ”Bluetooth and FM Current Consumption,” on page 78
• Table 25, ”WLAN Current Consumption using Power Topology #1 (Vbatt with Buck-
Boost),” on page 79
• Table 26, ”Bluetooth Receiver RF Specifications,” on page 80
• Table 27, ”Bluetooth Transmitter RF Specifications,” on page 82
• Table 28, ”FM Receiver Specifications,” on page 83
• Table 31, ”2.4 GHz Band Local Oscillator Specifications,” on page 87
• Table 32, ”2.4 GHz Band Receiver RF Specifications,” on page 88
• Table 34, ”2.4 GHz Band Transmitter RF Specifications,” on page 89
• Table 35, ”5 GHz Band Receiver RF Specifications,” on page 90
• Table 39, ”CLDO,” on page 93
• Table 40, ”LNLDOi,” on page 94
• Table 42, ”Buck-Boost Regulator,” on page 96
• Figure 16, ”UART Timing,” on page 97
• Table , ”SDIO Host Timing Requirement,” on page 108
• Table , ”Reset and Regulator Control Signal Sequencing,” on page 108
• Table , ”Signal and Power-up Sequence Timing Diagrams,” on page 108
• “Package Thermal Characteristics” on page 114
• “Miscellaneous Characteristics” on page 115
• Table 57, ”Ordering Information,” on page 121
Added:
• Figure 32, ”Power-Up Timing for WL ON and BT ON (WL REG_ON signal connected to
WL_RST_N, BT separated),” on page 112
• Figure 33, ”Power-Up Timing for WL OFF and BT ON (WL REG_ON signal connected to
WL_RST_N, BT separated),” on page 113
• Figure 34, ”Power-Up Timing for WL ON and BT OFF (WL REG_ON signal connected to
WL_RST_N, BT separated),” on page 113
Broadcom Corporation
Page iv
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Revision
Date
Description
4325-DS02-R
08/15/08
Updated:
• Figure 8, ”Power Supply Building Blocks,” on page 27.
• Table 3, ”Crystal Interface Signal Characteristics,” on page 31.
• Voltage for integrated LDO pins in Table 7 on page 44 and Table 8 on page 53.
• Table 19, ”Absolute Maximum Ratings,” on page 75.
• Table 20, ”Recommended Operating Conditions and DC Characteristics,” on page 75.
• Table 28, ”2.4-GHz Band Transmitter RF Specifications,” on page 85.
• Table 30, ”2.4-GHz Receiver Performance Specifications,” on page 86.
• Table 49, ”196-Ball FBGA Package Thermal Characteristics,” on page 110.
• Figure 28, ”339-Pin WLCSP Mechanical Information,” on page 113.
• Table 52, ”Ordering Information,” on page 118.Added:
• Figure 9, ”Power Topology Example,” on page 28.
• Table 15, ”Pin Default Pull-Up/Pull-Down,” on page 69.
• Table 16, ”BT/FM Interface I/O Status,” on page 71.
• Table 17, ”WLAN Interface I/O Status,” on page 72.
• Table 21, ”Bluetooth and FM Current,” on page 76.
• “SDIO Timing” on page 102.
• Section 21 ”Power-Up Sequence and Timing” on page 105.
• Figure 24, ”Power-Up Timing for WL Off and BT Off (VDDC Provided Externally),” on
page 108.
• Table 51, ”Miscellaneous Characteristics,” on page 111.
• Figure 30, ”WLAN Section Second Metal Keepout Area,” on page 115.
4325-DS01-R
12/14/07
Updated:
• General Description on page i
• Features on page ii
• Figure 2, ”BCM4325 Block Diagram,” on page 1
• Section 2 ”Bluetooth + FM Subsystem Overview” on page 2
• Integrated Section 3 into Section 2 ”Bluetooth + FM Subsystem Overview” on page 2
• Section 4 ”Microprocessor and Memory Unit for Bluetooth”: “External Reset” on page 11
• Section 6 ”FM Receiver Subsystem”:
- RDS/RBDS” on page 18
- Other Features” on page 18
• Section 8 ”WLAN 802.11 Radio Subsystem”: “Transmitter Path” on page 25
• Section 12 ”BCM4325 On-Chip Power Supplies”:
- Figure 8, ”BCM4325 Power Supply Building Blocks,” on page 28
- BCM4325 Example Power Supply Topology” on page 29
- Removed “BCM4325 Power Supply Applications–Power Efficiency
• Section 13 ”Frequency References”:
- Table 3, ”Crystal Interface Signal Characteristics,” on page 32
- Figure 11, ”Recommended Oscillator Configuration,” on page 33
- Figure 12, ”Recommended TCXO Connection,” on page 33
Broadcom Corporation
Document 4325-DS04-R
Page v
Revision
Date
Description
4325-DS01-R
(Cont.)
12/14/07
Added:
• Section 14 ”Pinout and Signal Descriptions”:
- Table 6, ”339-Pin WLCSP Signal Assignments by Pin Number and X- and Y-
Coordinates,” on page 38
- Table 7, ”196-Ball FBGA Signal Descriptions,” on page 42
- Table 8, ”339-Pin WLCSP Signal Descriptions,” on page 51
- Table 9, ”BT_VDDO Domain (1.8V to 3.3V),” on page 63
- Table 10, ”VDDIO Domain (1.8V to 3.3V),” on page 64
- Table 11, ”VDDIO_RF Domain (1.8V to 3.3V),” on page 65
- Table 12, ”VDDIO_SD Domain (1.8V to 3.3V),” on page 65
• “WLAN GPIO Signals” on page 66
• Section 17 ”WLAN RF Specifications”
- Table 24, ”2.4-GHz Band Transmitter RF Specifications,” on page 81
- Table 26, ”2.4-GHz Receiver Performance Specifications,” on page 82
- Table 29, ”5-GHz Band Local Oscillator Frequency Generator Specifications,” on page
83
• Section 18 ”BCM4325 Internal Regulator Electrical Specifications”:
- Table 31, ”CLDO,” on page 85
- Table 32, ”LNLDOi,” on page 86
- Table 34, ”Core Buck Regulator,” on page 87
- Table 35, ”Buck-Boost Regulator,” on page 88
- Added: “Regulator Current” on page 89
- Removed Analog/RF Buck Regulator section
• Section 22 ”Mechanical Information”: “339-Pin WLCSP Mechanical Information” on page
107
• Table 46, ”Environmental Characteristics,” on page 105
• Section 24 ”WLCSP Keepout Area”
4325-DS00-R
03/22/07
Initial release
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2009 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the registered
trademarks of Broadcom Corporation and/or its subsidiaries in the United States, certain other countries, and/or the EU.
Bluetooth® is a trademark of the Bluetooth SIG. Any other trademarks or trade names mentioned are the property of their
respective owners.
Confidential and Proprietary Information: This document and the software are proprietary properties of Broadcom
Corporation. This software package may only be used in accordance with the Broadcom Corporation license agreement.
Preliminary Data Sheet
6/30/09
BCM4325
TABLE OF CONTENTS
Section 1: BCM4325 Overview............................................................................................1
Overview ....................................................................................................................................................... 1
Mobile Phone Usage Model......................................................................................................................... 2
Section 2: On-Chip Power Supplies and Reset.................................................................3
Power Supply Topology .............................................................................................................................. 4
Reset Circuits............................................................................................................................................... 5
Section 3: Frequency References......................................................................................6
Crystal Interface and Clock Generation..................................................................................................... 6
Crystal Oscillator ......................................................................................................................................... 7
External Frequency Reference ................................................................................................................... 7
Frequency Selection.................................................................................................................................... 8
Frequency Trimming.................................................................................................................................... 8
LPO Clock Interface..................................................................................................................................... 9
Section 4: Bluetooth + FM Subsystem Overview ...........................................................10
Features ...................................................................................................................................................... 11
Bluetooth Features................................................................................................................................ 11
FM Radio Features ............................................................................................................................... 12
Bluetooth Radio ......................................................................................................................................... 12
Transmit ................................................................................................................................................ 12
Digital Modulator............................................................................................................................ 12
Power Amplifier.............................................................................................................................. 13
Receive................................................................................................................................................. 13
Digital Demodulator and Bit Synchronizer ..................................................................................... 13
Receiver Signal Strength Indicator ................................................................................................ 13
Local Oscillator Generation................................................................................................................... 13
Calibration............................................................................................................................................. 13
Section 5: Bluetooth Baseband Core...............................................................................14
Bluetooth 2.1 and 3.0 Features ................................................................................................................. 14
Frequency Hopping Generator ................................................................................................................. 14
Link Control Layer ..................................................................................................................................... 14
Broadcom Corporation
Document 4325-DS04-R
Page vii
BCM4325
Preliminary Data Sheet
6/30/09
Test Mode Support .....................................................................................................................................15
Bluetooth Power Management Unit ..........................................................................................................15
RF Power Management.........................................................................................................................16
Host Controller Power Management .....................................................................................................16
BBC Power Management......................................................................................................................16
FM Power Management ........................................................................................................................16
Adaptive Frequency Hopping....................................................................................................................17
Advanced Bluetooth/WLAN Coexistence.................................................................................................17
Fast Connection (Interlaced Page and Inquiry Scans)............................................................................17
Section 6: Microprocessor and Memory Unit for Bluetooth ......................................... 18
RAM, ROM, and Patch Memory .................................................................................................................18
Section 7: Bluetooth Peripheral Transport Unit............................................................. 19
PCM Interface for Bluetooth and SCO Audio...........................................................................................19
Slot Mapping..........................................................................................................................................20
Frame Sync ...........................................................................................................................................20
Data Formatting.....................................................................................................................................20
PCM Interface for FM Audio..................................................................................................................20
Bluetooth UART Interface..........................................................................................................................20
Auto-Baudrate Detection .......................................................................................................................22
I2S Interface ................................................................................................................................................22
Section 8: FM Receiver Subsystem................................................................................. 23
Sensitivity....................................................................................................................................................23
PLL Tuning..................................................................................................................................................23
Digital FM Output........................................................................................................................................23
Analog FM Output.......................................................................................................................................23
Broadcom Serial Control (BSC) Bus.........................................................................................................23
RDS/RBDS...................................................................................................................................................24
Other Features ............................................................................................................................................24
Section 9: Wireless LAN Functional Description........................................................... 25
Introduction to IEEE Std 802.11 ................................................................................................................25
IEEE 802.11a/g MAC Features ...................................................................................................................25
IEEE 802.11a/g MAC Description ..............................................................................................................26
IEEE 802.11a/g PHY Features....................................................................................................................27
Broadcom Corporation
Page viii
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
IEEE 802.11a/g PHY Description............................................................................................................... 28
Section 10: WLAN 802.11 Radio Subsystem...................................................................30
Receiver Path ............................................................................................................................................. 31
Transmitter Path......................................................................................................................................... 31
Calibration .................................................................................................................................................. 31
Section 11: WLAN Power Management ...........................................................................32
Section 12: WLAN System Interfaces ..............................................................................33
SDIO V1.2.................................................................................................................................................... 33
GPIO Interface ............................................................................................................................................ 33
One-Time-Programmable (OTP) Memory................................................................................................. 33
External Coexistence Interface................................................................................................................. 34
JTAG Interface............................................................................................................................................ 34
WLAN UART Debug Interface ................................................................................................................... 34
Section 13: Software Architecture ...................................................................................35
Host Software Architecture....................................................................................................................... 35
Device Software Architecture ................................................................................................................... 35
Remote Downloader ............................................................................................................................. 36
Wireless Configuration Utility................................................................................................................... 36
Section 14: Pinout and Signal Descriptions....................................................................37
Signal Assignments................................................................................................................................... 37
196-Ball FBGA Pinout........................................................................................................................... 37
339-Pin WLCSP Pinout......................................................................................................................... 39
Section 15: Signal Descriptions .......................................................................................43
196-Ball FBGA Package....................................................................................................................... 43
339-Pin WLCSP Package..................................................................................................................... 52
Pin Voltage Domains ............................................................................................................................ 64
WLAN GPIO Signals and Strapping Options ........................................................................................ 67
Bluetooth GPIO Signals ........................................................................................................................ 68
Pin Default Pull-Up/Pull-Down .............................................................................................................. 69
Interface I/O Status............................................................................................................................... 71
SDIO Pin Description................................................................................................................................. 74
Broadcom Corporation
Document 4325-DS04-R
Page ix
BCM4325
Preliminary Data Sheet
6/30/09
Section 16: Operating Conditions and DC Characteristics........................................... 75
Absolute Maximum Ratings.......................................................................................................................75
Electrostatic Discharge Specifications ....................................................................................................75
Environmental Ratings...............................................................................................................................76
Recommended Operating Conditions ......................................................................................................76
Bluetooth and FM Current Consumption...............................................................................................77
WLAN Current Consumption.................................................................................................................78
Section 17: Bluetooth RF Specifications ........................................................................ 79
Section 18: FM Receiver Specifications.......................................................................... 82
Section 19: WLAN RF Specifications .............................................................................. 85
Introduction.................................................................................................................................................85
Cellular Blocking ........................................................................................................................................85
WLAN Receiver Blocking Performance.................................................................................................86
2.4 GHz Band General RF Specifications.................................................................................................86
2.4 GHz Band Local Oscillator Specifications .........................................................................................86
2.4 GHz Band Receiver RF Specifications ...............................................................................................87
2.4 GHz Receiver Performance Specifications ........................................................................................87
2.4 GHz Band Transmitter RF Specifications...........................................................................................88
5 GHz Band Receiver RF Specifications ..................................................................................................89
5 GHz Band Transmitter RF Specifications..............................................................................................90
5 GHz Band Local Oscillator Frequency Generator Specifications.......................................................90
5 GHz Receiver Performance Specifications ...........................................................................................91
Section 20: Internal Regulator Electrical Specifications............................................... 92
CLDO............................................................................................................................................................92
LNLDOi (i = 1, 2, or 4) .................................................................................................................................93
Core Buck Regulator..................................................................................................................................94
Buck-Boost Regulator................................................................................................................................95
Section 21: Interface Timing and AC Characteristics.................................................... 96
Bluetooth Peripheral Transport Unit Timing Specifications ..................................................................96
Bluetooth UART Timing.........................................................................................................................96
PCM Interface Timing............................................................................................................................97
Short Frame Sync, Master Mode ...................................................................................................97
Broadcom Corporation
Page x
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Short Frame Sync, Slave Mode..................................................................................................... 98
Long Frame Sync, Master Mode ................................................................................................... 99
Long Frame Sync, Slave Mode ................................................................................................... 100
FM I2S Timing........................................................................................................................................... 101
FM I2C-Compatible Timing...................................................................................................................... 103
SPROM Timing ......................................................................................................................................... 103
JTAG Timing............................................................................................................................................. 104
SDIO Timing.............................................................................................................................................. 104
Section 22: Power-Up Sequence and Timing................................................................107
SDIO Host Timing Requirement.............................................................................................................. 107
Reset and Regulator Control Signal Sequencing ................................................................................. 107
Signal and Power-up Sequence Timing Diagrams ............................................................................. 108
Section 23: Package Information ...................................................................................113
Package Thermal Characteristics........................................................................................................... 113
Junction Temperature Estimation and PSIjt Versus Thetajc............................................................... 113
Environmental Characteristics ............................................................................................................... 113
Miscellaneous Characteristics................................................................................................................ 114
Section 24: Mechanical Information...............................................................................115
196-Ball FBGA Package........................................................................................................................... 115
339-Pin WLCSP Package......................................................................................................................... 116
Section 25: WLCSP Keepout Area .................................................................................117
Section 26: Ordering Information...................................................................................120
Broadcom Corporation
Document 4325-DS04-R
Page xi
BCM4325
Preliminary Data Sheet
6/30/09
LIST OF FIGURES
Figure 1: Functional Block Diagram ................................................................................................................... i
Figure 2: BCM4325 Block Diagram...................................................................................................................1
Figure 3: BCM4325 System Block Diagram......................................................................................................2
Figure 4: Power Supply Building Blocks............................................................................................................3
Figure 5: Power Topology Example ..................................................................................................................4
Figure 6: Recommended Oscillator Configuration ............................................................................................7
Figure 7: Recommended TCXO Connection.....................................................................................................7
Figure 8: PCM Interface with Linear PCM Codec ...........................................................................................19
Figure 9: IEEE 802.11a/g MAC Block Diagram...............................................................................................26
Figure 10: IEEE 802.11a/g PHY Block Diagram ...............................................................................................28
Figure 11: Radio Functional Block Diagram......................................................................................................30
Figure 12: Device Software Architecture...........................................................................................................36
Figure 13: Signal Connections to SDIO Card (SD 4-Bit Mode).........................................................................74
Figure 14: Signal Connections to SDIO Card (SD 1-Bit Mode).........................................................................74
Figure 15: Signal Connections to SDIO Card (SPI Mode) ................................................................................74
Figure 16: UART Timing....................................................................................................................................96
Figure 17: PCM (Short Frame Sync, Master Mode) Timing..............................................................................97
Figure 18: PCM (Short Frame Sync, Slave Mode) Timing ................................................................................98
Figure 19: PCM (Long Frame Sync, Master Mode) Timing...............................................................................99
Figure 20: PCM (Long Frame Sync, Slave Mode) Timing...............................................................................100
Figure 21: I2S Transmitter Timing...................................................................................................................101
Figure 22: I2S Receiver Timing.......................................................................................................................101
Figure 23: SDIO Bus Timing (Default Mode)...................................................................................................104
Figure 24: SDIO Bus Timing (High-Speed Mode)...........................................................................................105
Figure 25: Power-Up Timing for WL On and BT On........................................................................................108
Figure 26: Power-Up Timing for WL On and BT Off........................................................................................108
Figure 27: Power-Up Timing for WL Off and BT On........................................................................................109
Figure 28: Power-Up Timing for WL Off and BT Off (VDDC Provided by BCM4325).....................................109
Figure 29: Power-Up Timing for WL Off and BT Off (VDDC Provided Externally) ..........................................110
Figure 30: Power-Up Timing for WL On and BT On (REG_ON signals are
connected to RST_N signals) ........................................................................................................110
Figure 31: Power-Up Timing for WL Off and BT On (REG_ON signals are
connected to RST_N signals) ........................................................................................................111
Broadcom Corporation
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Document 4325-DS04-R
Preliminary Data Sheet
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BCM4325
Figure 32: Power-Up Timing for WL ON and BT ON (WL REG_ON signal
connected to WL_RST_N, BT separated) ..................................................................................... 111
Figure 33: Power-Up Timing for WL OFF and BT ON (WL REG_ON signal
connected to WL_RST_N, BT separated) ..................................................................................... 112
Figure 34: Power-Up Timing for WL ON and BT OFF (WL REG_ON signal
connected to WL_RST_N, BT separated) ..................................................................................... 112
Figure 35: 196-Ball FBGA Mechanical Information......................................................................................... 115
Figure 36: 339-Pin WLCSP Mechanical Information ...................................................................................... 116
Figure 37: WLAN Section Top Metal Keepout Area ....................................................................................... 117
Figure 38: WLAN Section Second Metal Keepout Area ................................................................................. 118
Figure 39: BT and FM Keepout Area.............................................................................................................. 119
Figure 40: BT and FM first and Second Keepout Area Enlargement.............................................................. 119
Broadcom Corporation
Document 4325-DS04-R
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BCM4325
Preliminary Data Sheet
6/30/09
LIST OF TABLES
Table 1: Reset Control Signals ........................................................................................................................5
Table 2: Crystal Interface Signal Characteristics .............................................................................................6
Table 3: LPO Signal Requirements..................................................................................................................9
Table 4: Power Control Pin Description .........................................................................................................16
Table 5: Common Baud Rate Examples........................................................................................................21
Table 6: 196-Ball FBGA Signal Assignments by Ball Number.......................................................................37
Table 7: 339-Pin WLCSP Signal Assignments by Pin Number and X- and Y-Coordinates...........................39
Table 8: 196-Ball FBGA Signal Descriptions .................................................................................................43
Table 9: 339-Pin WLCSP Signal Descriptions ...............................................................................................52
Table 10: BT_VDDO Domain (1.8V to 3.3V)....................................................................................................64
Table 11: VDDIO Domain (1.8V to 3.3V) .........................................................................................................65
Table 12: VDDIO_RF Domain (1.8V to 3.3V) ..................................................................................................66
Table 13: VDDIO_SD Domain (1.8V to 3.3V) ..................................................................................................66
Table 14: WLAN GPIO Functions and Strapping Options ...............................................................................67
Table 15: BT GPIO Signals..............................................................................................................................68
Table 16: Pin Default Pull-Up/Pull-Down .........................................................................................................69
Table 17: BT/FM Interface I/O Status ..............................................................................................................71
Table 18: WLAN Interface I/O Status...............................................................................................................73
Table 19: SDIO Pin Description .......................................................................................................................74
Table 20: Absolute Maximum Ratings .............................................................................................................75
Table 21: ESD Specifications...........................................................................................................................75
Table 22: Environmental Ratings.....................................................................................................................76
Table 23: Recommended Operating Conditions and DC Characteristics........................................................76
Table 24: Bluetooth and FM Current Consumption..........................................................................................77
Table 25: WLAN Current Consumption using Power Topology #1 (Vbatt with Buck-Boost) ..........................78
Table 26: Bluetooth Receiver RF Specifications..............................................................................................79
Table 27: Bluetooth Transmitter RF Specifications .........................................................................................81
Table 28: FM Receiver Specifications..............................................................................................................82
Table 29: Blocking Signals from Embedded Cellular Transmitter at Cellular Antenna Port.............................85
Table 30: 2.4 GHz Band General RF Specifications........................................................................................86
Table 31: 2.4 GHz Band Local Oscillator Specifications..................................................................................86
Table 32: 2.4 GHz Band Receiver RF Specifications ......................................................................................87
Table 33: 2.4 GHz Receiver Performance Specifications................................................................................87
Broadcom Corporation
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Document 4325-DS04-R
Preliminary Data Sheet
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BCM4325
Table 34: 2.4 GHz Band Transmitter RF Specifications.................................................................................. 88
Table 35: 5 GHz Band Receiver RF Specifications ........................................................................................ 89
Table 36: 5 GHz Band Transmitter RF Specifications..................................................................................... 90
Table 37: 5 GHz Band Local Oscillator Frequency Generator Specifications ................................................. 90
Table 38: 5 GHz Receiver Performance Specifications................................................................................... 91
Table 39: CLDO............................................................................................................................................... 92
Table 40: LNLDOi............................................................................................................................................ 93
Table 41: Core Buck Regulator ....................................................................................................................... 94
Table 42: Buck-Boost Regulator...................................................................................................................... 95
Table 43: UART Timing Speicifications ........................................................................................................... 96
Table 44: PCM (Short Frame Sync, Master Mode) Timing Specifications ...................................................... 97
Table 45: PCM (Short Frame Sync, Slave Mode) Timing Specifications ........................................................ 98
Table 46: TPCM (Long Frame Sync, Master Mode) Timing Specifications..................................................... 99
Table 47: PCM (Long Frame Sync, Slave Mode) Timing Specifications....................................................... 100
Table 48: Timing for I2S Transmitters and Receivers ................................................................................... 102
Table 49: FM I2C-Compatible Interface Timing............................................................................................. 103
Table 50: SPROM Timing Characteristics..................................................................................................... 103
Table 51: JTAG Timing Characteristics......................................................................................................... 104
Table 52: SDIO Bus Timing Parameters (Default Mode).............................................................................. 105
Table 53: SDIO Bus Timing Parameters (High-Speed Mode)...................................................................... 106
Table 54: Control Signal Descriptions ........................................................................................................... 107
Table 55: Thermal Characteristics (Values in Still Air) ................................................................................. 113
Table 56: Miscellaneous Characteristics ....................................................................................................... 114
Table 57: Ordering Information...................................................................................................................... 120
Broadcom Corporation
Document 4325-DS04-R
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BCM4325
Preliminary Data Sheet
6/30/09
Broadcom Corporation
Page xvi
Document 4325-DS04-R
Preliminary Data Sheet
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BCM4325
Section 1: BCM4325 Overview
OVERVIEW
The Broadcom® BCM4325 single-chip device provides the highest level of integration for a mobile or handheld wireless
system, with integrated IEEE 802.11™ a/b/g (MAC/baseband/radio), Bluetooth® 3.0 + HS, and an FM receiver. Designed to
address the needs of highly mobile devices that require minimal power consumption and board area, the BCM4325 provides
a compact ultra-small form-factor solution with minimal external components. This solution drives down the costs for mass
volumes, while allowing for flexibility in size, form, and function of handheld devices. It is targeted at addressing the needs
of highly mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnects for the major physical blocks in the BCM4325 and associated external interfaces, which
are described in greater detail in subsequent sections of this document.
BCM4325
SW Reg.
LDO
FM Radio
Radio Control
Common Logic Block (CLB)
Antenna
Ext. PA Control
RF Switch Control
Regulator Control
Clock Control
LPO
Sleep Clock
Xtal
FM Demod, MDX,
RDX Decode
Enhanced
Ext/Shared
Coexistence Control
LNA Control
Xtal OSC.
POR
Analog Stereo
DACs
POR
Bluetooth
UART
BT-PLL
Wireless LAN
Dig I/O
Dbg-UART
BB-PLL
PCM, BSC*, I2S
ARM7TDMI
RAM
ROM
PMU Control
ARM7TDMI
SDIO Dev
SDIO/SPI
SDROM IF
WDog timer
OTP
SROM IF
JTAG
Intr Ctrl
Addr Decoder
Bus Arbiter
GPIO
GPIO
UART
JTAG
RAM (384 KB)
ROM (80 KB)
PMU Ctrl
AHB2EBI
DMA
UART
JTAG
BT clk/Hopper
RX/TX
802.11 abg
AHB2APB
LCU
MAC
APU
PHY
Blue RF IF
WDog timer
Remap/Pause
GPIO
Radio
Dig I/O
2.4 GHz
Shared LNA
5 GHz
Modem
Radio
SW Timer
PA
(Int)
PA
(Int)
TX
* BSC (Broadcom Serial Control) is I2C-compatible.
BPF
Figure 2: BCM4325 Block Diagram
Broadcom Corporation
Document 4325-DS04-R
BCM4325 Overview
Page 1
BCM4325
Preliminary Data Sheet
6/30/09
MOBILE PHONE USAGE MODEL
The BCM4325 incorporates a number of unique features to simplify integration into mobile phone platforms. Its flexible PCM
and UART interfaces enable it to transparently connect with the existing circuits. In addition, the TCXO and LPO inputs allow
the use of existing handset features to further minimize the size, power, and cost of the complete system.
•
The PCM interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing
to single or multiple external codec devices.
•
The UART interface supports hardware flow control with tight integration to power control side band signaling to support
the lowest power operation.
•
•
•
•
The TCXO interface accommodates any of the typical reference frequencies used by cell phones.
The BSC and analog FM interfaces are available for legacy systems.
New FM digital interfaces can use either I2S or PCM.
The highly linear design of the radio transceiver ensures that the device has the lowest output of spurious emissions
regardless of the state of operation. It has been fully characterized in the global cellular bands.
•
The transceiver design has excellent blocking (eliminating desensitization of the Bluetooth receiver) and inter-
modulation performance (distortion of the transmitted signal caused by the mixing of the cellular and Bluetooth
transmissions) in the presence of any cellular transmission (GSM, GPRS, CDMA, WCDMA, or iDEN). Minimal external
filtering is required for integration inside the handset.
The BCM4325 is designed to provide direct interface with new and existing handset designs, as shown in Figure 3.
Vbatt
VIO
WL_RST_N
WLAN Host I/F
5 GHz WLAN Tx
5 GHz WLAN Rx
SDIO
SW
SW
WL_WAKE_N1
WL_HOST_WAKE_N1
BT_RST_N
UART
I2S
2.4 GHz WLAN Tx
2.4 GHz WLAN/BT Rx
Bluetooth Tx
Bluetooth Host I/F
FM Host I/F
CBF
BCM4325
PCM
BT_WAKE1
BT_HOST_WAKE1
BSC2
FM Rx
FM_IRQ1, 3
Ref Frequency
TCXO
LPO Clock
32.768 kHz
Notes: 1. Indication for optional GPIO functions.
2. BSC is Phillips® I2C-compatible.
3. For information on the FM_IRQ signal, refer to the following Broadcom documents:
BCM4325 FM_RDS Block Setup Quick Start Guide (4325-QSG100-X) and
FM Command and Control Specification (4325-AN400-X).
Figure 3: BCM4325 System Block Diagram
Broadcom Corporation
Page 2
Mobile Phone Usage Model
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 2: On-Chip Power Supplies and Reset
The BCM4325 contains power supply building blocks, including one buck-boost switching regulator, one buck switching
regulator, and five low-noise LDOs to simplify power supply design for Bluetooth and WLAN interfaces in embedded designs.
From a single host power supply, power configurations can be implemented using the BCM4325 on-chip power elements to
create a self contained design. All of the regulators are available with the 339-pin WLCSP package. The 196-ball FBGA
package does not provide access to LNLDO4.
Figure 4 shows available voltage and current from each integrated regulator.
Low Noise LDOs
Switchers
BBOOST
(Buck-Boost Regulator)
2.3V – 5.5V Input (VBAT)
3.3V Output
300 mA
1.4 MHz Switching Frequency
CLDO
(Core LDO)
1.4V – 2V Input
1.25V Output
200 mA
CBUCK
(Core Buck Regulator)
2.3V – 5.5V Input (VBAT)
1.25V / 1.5V Output
300 mA
LNLDO1
(Low Noise LDO1)
1.4V – 2V Input
1.25V Output
130 mA
2.8 MHz Switching Frequency
LNLDO2
(Low Noise LDO2)
Programmable:
1.4V – 2V Input / 1.25V
Output (Default)
3.3V Input / 2.5V Output
80 mA
Available in 196-ball FBGA
and 339-pin WLCSP
packages.
LNLDO4
(Low Noise LDO4)
1.5 / 3.3V Input
1.25 / 2.5V Output
80 mA
Only available in 339-pin
WLCSP packages.
Figure 4: Power Supply Building Blocks
Broadcom Corporation
Document 4325-DS04-R
On-Chip Power Supplies and Reset
Page 3
BCM4325
Preliminary Data Sheet
6/30/09
POWER SUPPLY TOPOLOGY
At least seven different power supply topologies can be supported by the voltage regulators available on the BCM4325.
Figure 5 shows one example of a power topology for an application with Bluetooth Class 1 PA, FM and WLAN supplied by
a variable battery voltage (Vbatt).
To achieve maximum performance from the integrated WLAN Power Amplifiers (PAs), the VDDPA power supply voltages
must remain within the recommended operating voltage range. If the supply voltage to the PA deviates outside this range,
the linearity of the PA will be degraded, resulting in lower throughput and shorter range. To avoid this condition, the buck-
boost regulator can be used to provide a constant 3.3V supply to the PA over the full range of the Vbatt voltage variation.
The trade-off is the additional components required for the buck-boost regulator versus the impaired performance if it is not
used.
Complete details of all seven power supply topologies are provided in the BCM4325 Power Supply Topologies application
note (document number 4325-AN60X-R), available on docSAFE.
VDDIO, VDDIO_SD
VDDIO = 1.8V – 3.3V
CLD0
Digital Logic and
Noise Insensitive
Blocks
1.5V
1.25V
1.5V Input
1.25V Output
200 mA
CBUCK
2.3V – 5.5V Input
1.5V Output
300 mA
LNLD01
1.5V Input
1.25V Output
130 mA
Vbatt = 2.3V – 5.5V
1.25V
1.25V
Noise Sensitive
Blocks (Radios, AFE,
LNA, Block etc.)
LNLD02
1.5V Input
1.25V Output
80 mA
VDD_FM
2.5V
3.3V
Bluetooth PA
VDD_BTTF
VDD_BTPA = 2.5V
Vbatt = 2.3V – 5.5V
BBOOST
2.3V – 5.5V Input
3.3V Output
300 mA
WLAN PA
VDDIO_RF
2.5V
Internal LDO
sr_avdd2p5
OTP
Figure 5: Power Topology Example
Broadcom Corporation
Page 4
Power Supply Topology
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
RESET CIRCUITS
The BCM4325 has four signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits, and the internal
regulator blocks, allowing the host to control power consumption.
Table 1: Reset Control Signals
Signal
Description
WL_REG_ON
This signal is used by the PMU (with BT_REG_ON) to decide whether or not to power down the
internal BCM4325 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be
disabled. If WL_RST_N is low (regardless of the BT_RST_N state), the WLAN core is powered off.
BT_REG_ON
This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the
internal BCM4325 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be
disabled.
WL_RST_N
BT_RST_N
Low asserting reset for the WLAN core. This pin must be driven high or low (not left floating).
Low asserting reset for the Bluetooth core. This pin must be driven high or low (not left floating).
Note: WL_REG_ON and BT_REG_ON are OR gated together in the BCM4325.
For detailed timing diagrams of these signals and the required power-up sequences, see Section 22: “Power-Up Sequence
and Timing” on page 107.
Broadcom Corporation
Document 4325-DS04-R
Reset Circuits
Page 5
BCM4325
Preliminary Data Sheet
6/30/09
Section 3: Frequency References
The BCM4325 uses the following external frequency references for normal and low-power operational modes:
•
An external crystal or external frequency reference driven by a temperature-compensated crystal oscillator (TCXO)
signal for generating all radio frequencies and normal operation clocking.
•
An external 32.768-kHz Low Power Oscillator (LPO) for low-power mode timing.
CRYSTAL INTERFACE AND CLOCK GENERATION
The BCM4325 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing that enables
it to operate using a wide range of frequency references. An external source, such as a TCXO or a crystal interfaced directly
to the BCM4325, can be used. The default frequency reference setting is a 26 MHz crystal or TCXO. Table 2 list the
requirements and characteristics for the crystal or frequency reference.
Table 2: Crystal Interface Signal Characteristics
Parameter
Crystal
External Freq. Reference
Units
Frequency range
12–52 MHz in 2 ppm stepsd
12–52 MHz, in 2-ppm steps b
–
Crystal load capacitance
ESR (maximum)
12 e
N/A
pF
Ω
60
–
Power dissipation, max
Input signal AC amplitude
Signal type
200
N/A
N/A
N/A
–
uW
mVp-p
–
400 to 1200 f
Square wave or sine wave
Input impedance
≥ 1
≤ 4.7
MΩ
pF
Phase noise (maximum for f = 26 MHz a)
1 kHz
–
–
–
–
≤ –100
≤ –115
≤ –120
≤ –140
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
10 kHz
100 kHz
1 MHz
Auto-detection frequencies when using LPO b, c 12, 13, 14.4, 15.36, 16.2, 16.8, 12, 13, 14.4, 15.36, 16.2, 16.8, MHz
18, 19.2, 19.44, 19.68, 19.8,
20, 24, 26, 38.4
18, 19.2, 19.44, 19.68, 19.8,
20, 24, 26, 38.4
Frequency tolerance plus over temperature
without trimming
20
20
ppm
Initial frequency tolerance trimming range
50
50
ppm
ms
Time for stable system clock after power up or
XTAL_PU assertion
Warm-up time < 6 ms
Maximum hold time for host
< 6 ms
a. For a clock reference other than 26 MHz, 20*log10(f/26) dB should be added to the limits, where f = the reference clock
frequency in MHz.
b. Auto-detection of frequencies requires that the crystal or external frequency reference have less than 50 ppm of variation,
and the external LPO frequency have less than 200 ppm of variation at the time of auto-detection.
c. 52 MHz frequency reference is also supported. The BT_TM6 signal should be pulled low for 52 MHz clock reference.
d. The frequency step size is approximately 80 Hz resolution.
e. The precise value of load capacitance to center the frequency tolerance is dependent on board layout; see Broadcom
reference schematics for exact values.
Broadcom Corporation
Page 6
Frequency References
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
f. If the input signal amplitude is below 800 mV p-p, contact your Broadcom representative for applications assistance. DC
coupled digital clock with swing less than 1.32V is supported.
CRYSTAL OSCILLATOR
The BCM4325 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal
oscillator including all external components is shown in Figure 6.
C
O SCIN
10 – 33 pF
Note: The precise value of load capacitance to center
the frequency tolerance depends on the board layout.
Refer to Broadcom reference schematics for typical
starting values.
C
O SCO UT
221 Ohms
10 – 33 pF
Note : The value of the series resistor can be lower in
some designs. Refer to Broadcom reference schematics
for the exact value.
Figure 6: Recommended Oscillator Configuration
EXTERNAL FREQUENCY REFERENCE
As an alternative to a crystal, an external frequency reference, such as a TCXO signal, can be connected to the OSCIN pin
on the BCM4325 via a D.C. blocking capacitor, as shown in Figure 7. The external frequency reference input is designed to
not change the loading on the TCXO when the BCM4325 is powered up or powered down.
TCXO
OSCIN
Consult the reference
schematics for the best
value for this capacitor.
OSOUT
No Connect
Figure 7: Recommended TCXO Connection
Broadcom Corporation
Document 4325-DS04-R
Crystal Oscillator
Page 7
BCM4325
Preliminary Data Sheet
6/30/09
FREQUENCY SELECTION
Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the
standard handset references frequencies of 12, 13, 14.4, 16.2, 16.8, 18, 19.2, 19.44, 19.68, 19.8, 20, 24, 26, 38.4, and
52 MHz, but any other frequency between these as desired by the system designer. The BCM4325 must have the reference
frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all bit timing is derived
from the reference frequency.
The reference frequency for the BCM4325 may be set in one of the following ways:
•
•
Specify the frequency in the nvram.txt file.
Auto-detect the standard handset reference frequencies using an external LPO clock.
The BCM4325 is set at the factory to a default frequency of 26 MHz. For a typical design using a crystal it is recommended
that the default frequency be used.
For applications such as handsets and portable smart communication devices, where the reference frequency is one of the
standard frequencies commonly used, the BCM4325 automatically detects the reference frequency and programs itself to
the correct reference frequency. In order for auto-frequency detection to work correctly, the BCM4325 must have a valid and
stable 32.768-kHz LPO clock present during power-on reset.
FREQUENCY TRIMMING
The BCM4325 uses a fractional-N synthesizer to digitally fine tune the frequency reference input to within 2 ppm tuning
accuracy. This trimming function can be applied to either the crystal or an external frequency source such as a TCXO. Unlike
the typical crystal trimming methods used, the BCM4325 changes the frequency using a fully digital implementation and is
much more stable and unaffected by either the crystal characteristics or the temperature. The input impedance and loading
characteristics remain unchanged on either the TCXO or the crystal during the trimming process and are unaffected by
process and temperature variations.
The option of whether to use frequency trimming would be determined by a cost trade-off between the cost of the crystal and
the added manufacturing cost associated with frequency trimming. Frequency trimming value can be stored in the host and
written back to the BCM4325.
Broadcom Corporation
Page 8
Frequency Selection
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
LPO Clock Interface
An additional frequency reference is the LPO clock that the BCM4325 uses to provide low-power mode timing for park, hold,
and sniff. The LPO clock should be provided externally to the device from a stable and accurate 32.768-kHz source.
Table 3: LPO Signal Requirements
Parameter
LPO Clock
Units
Nominal input frequency
Frequency accuracy
Duty cycle
32.768
200 a
kHz
ppm
30% to 70%
less than 1
–
Jitter (when FM is used)
Input signal amplitude
Signal type
Hz (integrated from 300 Hz to 15 kHz)
200 to 1800
Square wave or sine wave
mV, p-p
–
Input impedanceb
>100k
< 5
Ω
pF
®
a. +150 if FM is used. See Broadcom Bluetooth SoC Crystal, TCXO, RFIC, and LPO User Guide (43XX_20XX-1xx-R) for
details.
b. When power is applied, or switched off.
Broadcom Corporation
Document 4325-DS04-R
LPO Clock Interface
Page 9
BCM4325
Preliminary Data Sheet
6/30/09
Section 4: Bluetooth + FM Subsystem Overview
The Broadcom BCM4325 includes a Bluetooth® 3.0 + HS compliant standalone baseband processor with an integrated 2.4
GHz transceiver, integrated FM and RDS/RBDS receiver, and an integrated FM baseband processor. It features the highest
level of integration and eliminates all critical external components, thus minimizing the footprint and system cost of
implementing a Bluetooth and FM solution. The BCM4325 is firmware upgradable for future specifications.
The BCM4325 is the optimal solution for any voice or data application that requires the Bluetooth SIG standard Host
Controller Interface (HCI) using a high-speed UART and PCM. The BCM4325 incorporates all Bluetooth 2.1 + EDR features
including eSCO, AFH, Fast Connect, all EDR packet types and lengths, and all errata. The BCM4325 also includes
InConcert and other industry-collaborative coexistence solutions.
Note: The BCM4325 is designed to be firmware upgradable to any foreseeable future enhancements to the
Bluetooth specification by the Bluetooth SIG.
The Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent industrial temperature
applications and the tightest integration into mobile handsets and portable devices. It is fully compatible with all standard
TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS and cellular radios.
The BCM4325 also integrates a complete FM and RDS/RBDS solution. The integrated solution saves power and board
space, minimizes the BOM, and maximizes interface flexibility over a separate Bluetooth and FM solution. The FM
subsystem can operate independently of Bluetooth and achieve full performance while Bluetooth is operating. It is designed
to cover from 76 MHz, up to 108 MHz, bands (US, Europe, Japan) and to operate from a 32 kHz LPO input. The FM
subsystem supports an I2C-compliant Broadcom Serial Control (BSC) interface and analog outputs for legacy systems, as
well as digital interface options, such as I2S and PCM. The I2S and PCM interfaces support 48 kHz operation and can be
configured as either master or slave. The analog interface consists of high-quality, line-level stereo DACs.
The BCM4325 FM subsystem includes advanced RDS/RBDS capability. The BCM4325 synchronizes, demodulates, and
decodes RDS/RBDS signals including CRC processing, post data filter detection, signal quality estimation, and buffering
thus making it easy for an external application to read and process the RDS/RBDS data.
The FM radio provides excellent reception, with 1 μV for 26 dB (S+N)/N typical sensitivity and greater than 60 dB SNDR
capability, allowing easier system integration and antenna design. The FM subsystem includes many sought after features,
including signal-dependant mono/stereo blend, soft mute, and signal bandwidth control. The system has digital RSSI, signal
quality, and IF frequency error indicators for system monitoring. The FM subsystem contains embedded automatic search
and scan features, and large RDS data buffers to simplify the interface with an external host.
Broadcom Corporation
Page 10
Bluetooth + FM Subsystem Overview
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
FEATURES
BLUETOOTH FEATURES
Major Bluetooth features of the BCM4325 include:
•
•
•
Supports key features of upcoming Bluetooth standards
Class 1 support with PA bias adjust
Support for BT v3.0 + HS features combined with Broadcom’s v3.0 + HS qualified host software, including alternate
MAC/PHY, read encryption key size, enhanced power control, and unicast connectionless data.
•
Fully supports Bluetooth Core Specification version 2.1 + EDR features:
-
-
-
-
-
-
-
-
-
Adaptive Frequency Hopping (AFH)
Quality of Service (QoS)
Extended Synchronous Connections (eSCO)—Voice Connections
Fast Connect
Secure Simple Pairing (SSP)
Sniff Subrating (SSR)
Encryption Pause Resume (EPR)
Extended Inquiry Response (EIR)
Link Supervision Timeout (LST)
•
•
•
•
Maximum UART baud rates up to four Mbps
Supports Bluetooth Enhanced Data Rate (EDR)
Supports maximum Bluetooth data rates over HCI UART
Multipoint operation with up to seven active slaves
-
-
Maximum of seven simultaneous active ACL links
Maximum of three simultaneous active SCO and eSCO with scatternet support
•
•
Scatternet operation with up to four active piconets with background scan and support for scatter mode
High-speed HCI UART transport support with low-power out-of-band BT_WAKE and HOST_WAKE signaling (see “Host
Controller Power Management” on page 16)
•
•
•
•
Channel quality driven data rate and packet type selection
Standard Bluetooth test modes
Extended radio and production test mode features
Full support for power savings modes
-
-
-
Bluetooth clock request
Bluetooth standard park, hold, and sniff
Deep sleep modes and software regulator shutdown
•
TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power oscillator (LDO),
which can be used during power save mode for better timing accuracy
Broadcom Corporation
Document 4325-DS04-R
Features
Page 11
BCM4325
Preliminary Data Sheet
6/30/09
FM RADIO FEATURES
Major FM Radio features include:
•
•
•
•
•
•
•
•
•
•
•
•
•
76 MHz to 108 MHz FM bands supported (US, Europe, and Japan)
Excellent FM radio performance with 1 μV sensitivity for 26 dB (S+N)/N
FM subsystem control using the BSC bus or through the Bluetooth HCI interface
Signal dependent stereo/mono blending
Signal dependent soft mute
Auto search and tuning modes
Audio silence detection
RSSI, IF frequency, status indicators
RDS and RBDS demodulator and decoder with filter and buffering functions
Automatic frequency jump
FM subsystem operates from 32 kHz low-power oscillator (LPO) or reference clock inputs
Improved audio interface capabilities with full-featured PCM, I2S, and analog stereo DAC
I2S can be master or slave
BLUETOOTH RADIO
The BCM4325 includes an integrated radio transceiver, optimized for use in 2.4 GHz Bluetooth wireless systems. Its design
provides low-power, low-cost, robust communications for applications operating in the globally available, 2.4 GHz,
unlicensed ISM band. The radio transceiver is fully compliant with Bluetooth radio and EDR specifications and meets or
exceeds the requirements to provide the highest communication link quality of service.
Note: Sharing a single 2.4 GHz antenna between the Bluetooth and WLAN sections is supported when an
appropriate SP3T switch is used in the external RF signal path.
TRANSMIT
The BCM4325 features a fully integrated zero-IF transmitter. The baseband transmit data is digitally GFSK-modulated in the
modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal
filtering, I/Q upconversion, output power amplifier (PA), and RF filtering. The transmitter path also incorporates new
modulation schemes π/4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to support EDR.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK, Π/4DQPSK, and 8-DPSK signal. The
fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal
and is much more stable than direct VCO modulation schemes.
Broadcom Corporation
Page 12
Bluetooth Radio
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Power Amplifier
The fully integrated PA provides a maximum output signal level (see Table 27: “Bluetooth Transmitter RF Specifications,”
on page 81) using a highly linearized, temperature compensated design. This provides greater flexibility in front-end
matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, no external filters are
required for meeting Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset
applications where the Bluetooth is integrated next to the cellular radio minimal external filtering can be applied to achieve
near thermal noise levels for spurious and radiated noise emissions.
The integrated power amplifier is Bluetooth Class 2 compliant and includes power control adjustment with a 28 dB range
and 4 dB nominal step size. The integrated power amplifier can be configured as a PA driver to an external power amplifier
for full Bluetooth Class 1 compliance.
RECEIVE
The receiver path uses a low-IF scheme to down convert the received signal for demodulation in the digital demodulator and
bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip
channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front end topology with built-in out-of-band
attenuation enables the BCM4325 to be used in most applications with no off-chip filtering. For integrated handset operation
where the Bluetooth function is integrated close to the cellular transmitter, minimal external filtering is required to eliminate
the desensitization of the receiver by the cellular transmit signal.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer takes the low-IF received signal and performs an optimal frequency tracking
and bit synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the BCM4325 provides an Receiver Signal Strength Indicator (RSSI) signal to the baseband so that the
controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to
determine whether the transmitter should increase or decrease its output power.
LOCAL OSCILLATOR GENERATION
Local Oscillator generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available
channels. The local oscillator generation subblock employs an architecture for high immunity to local oscillation pulling
during PA operation. The BCM4325 uses an internal RF and IF loop filter.
CALIBRATION
The BCM4325 radio transceiver features an automated calibration scheme that is fully self contained in the radio. No user
interaction is required during normal operation or during manufacturing to provide the optimal performance. Calibration
optimizes the performance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase
characteristics of filters, matching between key components, and key gain blocks. This takes into account process variation
and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops and
calibrates for temperature variations as the device cools and heats during normal operation in its environment.
Broadcom Corporation
Document 4325-DS04-R
Bluetooth Radio
Page 13
BCM4325
Preliminary Data Sheet
6/30/09
Section 5: Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high performance Bluetooth
operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that
passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage,
optimally segments and packages data into baseband packets, manages connection status indicators, and composes and
decodes HCI packets. In addition to these functions, it independently handles HCI event types, and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security
of the TX/RX data before sending over the air:
•
Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy
check (CRC), data decryption, and data dewhitening in the receiver.
•
Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening
in the transmitter.
BLUETOOTH 2.1 AND 3.0 FEATURES
The BBC supports the following Bluetooth 2.1 features:
•
•
•
Extended Inquiry Response (EIR) Shortens the time to retrieve device name, specific profile and mode.
Encryption Pause Resume (EPR)
Sniff Subrating (SSR)
Enables the use of Bluetooth technology in a much more secure environment.
Optimizes power consumption for low duty cycle asymmetrical data flow, which
subsequently extends battery life.
•
•
Simple Pairing (SP)
Reduces the number of steps with minimal or no user interaction when connecting
two devices.
Link Supervision Timeout (LST)
In addition, the BBC is compliant with the Bluetooth Core specification 3.0 + HS when combined with Bluetooth 3.0 + HS
qualified host software—including Alternate MAC/PHY, read encryption key size, enhanced power control, and unicast
connectionless data.
FREQUENCY HOPPING GENERATOR
The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller
state, Bluetooth clock, and the device address.
LINK CONTROL LAYER
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control
Unit (LCU). This layer consists of the command controller that takes commands from the software and other controllers that
are either activated or configured by the command controller to perform the link control tasks.
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Bluetooth Baseband Core
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Each task performs a different state function in the Bluetooth link controller.
•
Major states
-
-
Standby
Connection
•
Substates
-
-
-
-
-
-
-
Page
Page Scan
Inquiry
Inquiry Scan
Park
Sniff
Hold
TEST MODE SUPPORT
The BCM4325 fully supports Bluetooth Test mode as described in Part 1 of the Specification of the Bluetooth System
Version 2.1. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the BCM4325 also supports enhanced testing features to simplify RF
debugging and qualification and type approval testing. These features include:
•
Fixed frequency carrier wave (unmodulated) transmission
-
-
Simplifies some type approval measurements (Japan)
Aids in transmitter performance analysis
•
Fixed frequency constant receiver mode
-
-
-
Receiver output directed to I/O pin
Allows for direct BER measurements using standard RF test equipment
Facilitates spurious emissions testing for receive mode
•
Fixed frequency constant transmission
-
-
8-bit fixed pattern or PRBS-9
Enables modulated signal measurements with standard RF test equipment
BLUETOOTH POWER MANAGEMENT UNIT
The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software
through power management registers, or packet handling in the baseband core.
The power management functions provided by the BCM4325 are:
•
•
•
•
RF Power Management
Host Controller Power Management
BBC Power Management
FM Power Management
Broadcom Corporation
Document 4325-DS04-R
Test Mode Support
Page 15
BCM4325
Preliminary Data Sheet
6/30/09
RF POWER MANAGEMENT
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz
transceiver. The transceiver then processes the power-down functions accordingly.
HOST CONTROLLER POWER MANAGEMENT
When running in UART mode, the BCM4325 may be configured so that dedicated signals are used for power management
hand shaking between the BCM4325 and the host. The basic power saving functions supported by those handshaking
signals include the standard Bluetooth defined power savings modes and standby modes of operation.
An alternative to using the BT_WAKE and HOST_WAKE signalling uses the CTS and RTS as a combination of UART
handshake signals during normal operation and as BT_WAKE and HOST_WAKE when the device is in a power saving
mode.
Table 4 describes the power control handshake signals used with the UART interface.
Table 4: Power Control Pin Description
Mapped to
Signal
Type Description
Pin
BT_WAKE
BT_GPIO_0
I
Bluetooth device wakeup. Signal from the host to the BCM4325 indicating that the
host requires attention.
• Asserted: Bluetooth device must wakeup or remain awake.
• Deasserted: Bluetooth device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
HOST_WAKE BT_GPIO_1
O
Host wake up. Signal from the BCM4325 to the host indicating that the BCM4325
requires attention.
• Asserted: Host device must wakeup or remain awake.
• Deasserted: Host device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
Note: Successful operation of the power management handshaking signals requires coordination between the
BCM4325 firmware and the host software.
BBC POWER MANAGEMENT
The following are low power operations for the BBC:
•
•
Physical layer packet handling turns RF on and off dynamically within packet TX and RX.
Bluetooth-specified low-power connection modes are sniff, hold, and park. While in these modes, the BCM4325 runs on
the low-power oscillator and wakes up after a predefined time period.
FM POWER MANAGEMENT
The BCM4325 FM subsystem can operate independently of, or in tandem with, the Bluetooth RF and BBC subsystems. The
FM subsystem power management scheme operates in conjunction with the Bluetooth RF and BBC subsystems.
Broadcom Corporation
Page 16
Bluetooth Power Management Unit
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
ADAPTIVE FREQUENCY HOPPING
The BCM4325 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel
map selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate
frequency-hop map.
ADVANCED BLUETOOTH/WLAN COEXISTENCE
The BCM4325 includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die
solution. These coexistence technologies are targeted at small form factor platforms such as cell phones and media players,
including applications such as VoWLAN + SCO and Video-over-WLAN + High-Fidelity BT stereo. Support is provided for
platforms that share a single antenna between Bluetooth and 802.11g. Dual antenna applications are also supported. The
BCM4325 radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna
applications. This is possible only via an integrated solution (shared LNA and joint AGC algorithm). It has superior
performance versus implementations that need to arbitrate between Bluetooth and WLAN reception.
The BCM4325 integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced
coexistence interface. The Packet Traffic Scheduler (PTS) can suitably schedule future packet transmissions (versus merely
supporting arbitration on a packet-by-packet basis as employed in discrete Bluetooth/WLAN solutions) and can factor in
beacon arrival times, duration of upcoming packet transmissions, etc. Information is exchanged between the Bluetooth and
WLAN cores without host processor involvement.
The BCM4325 also supports Transmit Power Control (TPC) on the STA together with standard Bluetooth TPC to limit mutual
interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding
with Bluetooth frames. Improved channel classification techniques have been implemented in Bluetooth for faster and more
accurate detection and elimination of interferers (including non-WLAN 2.4 GHz interference).
FAST CONNECTION (INTERLACED PAGE AND INQUIRY SCANS)
The BCM4325 supports page scan and inquiry scan modes that significantly reduce the average inquiry response and
connection times. These scanning modes are compatible with the Bluetooth version 2.1 page and inquiry procedures.
Broadcom Corporation
Document 4325-DS04-R
Adaptive Frequency Hopping
Page 17
BCM4325
Preliminary Data Sheet
6/30/09
Section 6: Microprocessor and Memory Unit for
Bluetooth
The Bluetooth microprocessor core is based on ARM7TDMIS® 32 bit RISC processor with embedded ICE-RT debug and
JTAG interface units. It runs software from the link control layer, up to the Host Controller Interface (HCI).
The ARM core is paired with a memory unit that contains 256 KB of ROM memory for program storage and boot ROM, 48 KB
of RAM for data scratchpad and patch RAM code. The internal boot ROM allows for flexibility during power-on reset to enable
the same device to be used in various configurations. At power-up, the lower layer protocol stack is executed from the
internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or features additions. These
patches may be downloaded from the host to the BCM4325 through the UART transports. The mechanism for downloading
via UART is identical to the proven interface of the BCM2045 device.
RAM, ROM, AND PATCH MEMORY
The BCM4325 Bluetooth core has 48 KB of internal RAM which is mapped between general purpose scratch pad memory
and patch memory and 256 KB of ROM used for the lower layer protocol stack, test mode software, and boot ROM. The
patch memory capability enables the addition of code changes for purposes of feature additions and bug fixes to the ROM
memory.
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Page 18
Microprocessor and Memory Unit for Bluetooth
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 7: Bluetooth Peripheral Transport Unit
PCM INTERFACE FOR BLUETOOTH AND SCO AUDIO
The PCM Interface on the BCM4325 can connect to linear PCM Codec devices in master or slave mode. In master mode,
the BCM4325 generates the BT_PCM_CLK and BT_PCM_SYNC signals, and in slave mode, these signals are provided by
another master on the PCM interface and are inputs to the BCM4325.
The BCM4325 supports up to three SCO or eSCO channels through the PCM Interface and each channel can be
independently mapped to any of the available slots in a frame.
The configuration of the PCM interface may be adjusted by the host through the use of Vendor Specific HCI Commands.
Figure 8 shows three options for connecting a BCM4325 to a PCM codec device as either a master or slave connection.
PCM_IN
PCM_OUT
PCM_BCLK
PCM_SYNC
PCM Codec
(Master)
BCM4325
(Slave)
PCM Interface Slave Mode
PCM_IN
PCM_OUT
PCM_BCLK
PCM_SYNC
BCM4325
(Master)
PCM Codec
(Slave)
PCM Interface Master Mode
PCM_IN
PCM_OUT
PCM_BCLK
PCM_SYNC
PCM Codec
(Hybrid)
BCM4325
(Hybrid)
PCM Interface Hybrid Mode
Figure 8: PCM Interface with Linear PCM Codec
Broadcom Corporation
Document 4325-DS04-R
Bluetooth Peripheral Transport Unit
Page 19
BCM4325
Preliminary Data Sheet
6/30/09
SLOT MAPPING
The BCM4325 supports up to three simultaneous full-duplex SCO or eSCO channels. These three channels are time
multiplexed onto the single PCM interface by using a time slotting scheme where the 8-kHz audio sample interval is divided
into up to 16 slots. The number of slots is dependant on the selected interface rate of 128 kHz, 256 kHz, 512 kHz, 1024 kHz,
or 2048 kHz. The corresponding number of slots for these interface rates is one, two, four, eight and 16, respectively.
Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver
tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver
tristates its output after the falling edge of the PCM clock during the last bit of the slot.
FRAME SYNC
The BCM4325 supports both short and long frame sync types in both master and slave configurations. In the short frame
sync mode, the frame sync signal is an active-high pulse at the 8 kHz audio frame rate that is a single-bit period in width and
synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects
the first bit of the first slot to start at the next rising edge of the clock. In the long frame sync mode, the frame sync signal is
again an active-high pulse at the 8 kHz audio frame rate; however, the duration is three bit periods and the pulse starts
coincident with the first bit of the first slot.
DATA FORMATTING
The BCM4325 may be configured to generate and accept several different data formats. The BCM4325 uses 13 of the 16
bits in each PCM frame. The location and order of these 13 bits is configurable to support various data formats on the PCM
interface. The remaining three bits are ignored on the input, and may be filled with 0s, 1s, sign bit, or a programmed value
on the output. The default format is 13-bit, 2’s complement data, left-justified, and clocked MSB first.
PCM INTERFACE FOR FM AUDIO
The BCM4325 also supports a mode where the FM stereo audio is output over the PCM Interface in master or slave mode.
A BT_PCM_SYNC sample rate of 48 kHz is supported with associated BT_PCM_CLK rate of 1.536 MHz. The
BT_PCM_SYNC signal follows the short frame sync format. In this FM audio mode, the BT_PCM_IN signal is ignored and
FM audio is output on the BT_PCM_OUT signal. The FM stereo audio is presented MSB first onto the BT_PCM_OUT signal
with the 16 bits of left-channel data first followed by the 16 bits of right-channel data.
BLUETOOTH UART INTERFACE
The Bluetooth UART physical interface is a standard, 4-wire interface (RX, TX, RTS, CTS) with adjustable baud rates from
9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection.
Alternatively, the baud rate may be selected via a vendor specific UART HCI command. The BCM4325 has a 480-byte
receive FIFO and a 480-byte transmit FIFO to support EDR. The interface supports the Bluetooth 3.0 UART HCI
specification.
The BCM4325 has the added capability to perform wake-on-activity, where it can be asleep and have activity on the RX or
CTS inputs to wake up the chip.
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Page 20
Bluetooth UART Interface
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
In order to support both high and low baud rates efficiently, the UART clock can be selected as either 24 or 48 MHz.
Generally, the higher speed clock is needed for baud rates over 3 Mbaud, however a lower speed clock may be used to
achieve a more accurate baud rate under 3 Mbaud. The baud rate of the BCM4325 UART is controlled by two values. The
first is a UART clock divisor (also called the DLBR register) that divides the UART clock by an integer multiple of 16. The
second is a baud rate adjustment (also called the DHBR register) that is used to specify a number of UART clock cycles to
stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time,
and up to eight UART clock cycles can be inserted into the end of each bit time.
When setting the baud rate manually, the UART clock divisor is an 8-bit value that is stored as a 256 desired divisor. For
example, a desired divisor of 13 is stored as 256 – 13 = 243 = 0xF3.
The baud rate adjustment is also an 8-bit value, of which the four MSBs are the number of additional clock cycles to insert
in the first half of each bit time, and the four LSBs are the number of clock cycles to insert in the second half of each bit time.
If either of these two values is over eight, it is rounded to eight.
To program the baud rate for high-rate mode (greater than 1.5 Mbaud), divide UART clock by the desired rate to compute
the number of UART clock cycles per bit. This number must be from eight to 15 for the high-rate mode, and is programmed
into the DLBR as 256 minus the number of clocks. For three Mbaud, the calculation would be as follows:
24,000,000/3,000,000 = 8 and 256 – 8 = 248 = 0xF8.
To compute normal 2048 baud rate mode (<1.5 Mbaud), the calculation is expressed as:
24 MHz/((16xUART clock divisor) + total inserted 24 MHz clock cycles)
Table 5 contains example values to generate common baud rates.
Table 5: Common Baud Rate Examples
Baud Rate Adjustment
High Nibble Low Nibble
0x00 0x00
UART Clock
Divisora
Desired Baud
Rate (bps)
Actual Baud Rate
(bps)
Error (%)
4000000
3692000
3000000
2000000
1500000
1444444
921600
460800
230400
115200
57600
0xF4
0xF3
0xF8
0xF4
0xFF
0xFE
0xFF
0xFD
0xFA
0xF3
0xE6
0xD9
0xCC
0xB2
0x98
0x64
4000000
3692308
3000000
2000000
1500000
1454544
923077
461538
230796
115385
57692
0.00
0.01
0.00
0.00
0.00
0.70
0.16
0.16
0.17
0.16
0.16
0.00
0.16
0.00
0.16
0.00
0x00
0x00
0x00
0x00
0x00
0x05
0x02
0x04
0x00
0x00
0x01
0x00
0x01
0x00
0x02
0x00
0x00
0x00
0x00
0x01
0x05
0x02
0x04
0x00
0x00
0x00
0x00
0x01
0x00
0x02
38400
38400
28800
28846
19200
19200
14400
14423
9600
9600
a. The value in this column is 256 minus the desired divisor.
Broadcom Corporation
Document 4325-DS04-R
Bluetooth UART Interface
Page 21
BCM4325
Preliminary Data Sheet
6/30/09
Normally, the UART baud rate is set by a configuration record downloaded after reset or automatic baud rate detection and
the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is
provided through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The
BCM4325 UART operates correctly with the host UART, if the combined baud rate error of the two devices is within 5%.
AUTO-BAUDRATE DETECTION
The BCM4325 may be put into a state where it attempts to automatically detect the baud rate. This is done by holding the
BT_UART_CTS_N signal low during reset or power up. An auto-baud character A (0x41) or the HCI_RESET command
{0x01, 0x03, 0x0C, 0x00} can be sent from the host to train the BCM4325 UART when this feature is used.
The corresponding successful returns from BCM4325 auto-baud response are:
{0x41, 0x30, 0x34, 0x31} for the autobaud character
{0x04, 0x0E, 0x04, 0x01, 0x03, 0x0C, 0x00, 0x34, 0x31} for the HCI_RESET command
The run-time configuration download through the vendor specified commands is required to further configure the BCM4325
for normal operations. The BCM4325 can automatically detect baud rates up to the external crystal frequency divided by 16.
I2S INTERFACE
The 3-wire I2S interface for FM audio supports both master and slave modes. Input reference clock frequencies of 13 MHz,
19.2 MHz, 26 MHz, and 38.4 MHz are supported.
The three I2S signals are:
I2S Clock:
I2S Word Select: I2S_WS
I2S Data Out:
I2S_SDO
I2S_SCK
I2S_SCK and I2S_WS become outputs in Master mode and inputs in Slave mode, while I2S_SDO always stays as an
output. I2S data input is not supported. The channel word length is 16 bits and the data is justified so that the MSB of the left
channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one
bit clock cycle after the I2S_WS transition, synchronous with the falling edge of bit clock. Left channel data is transmitted
when I2S_WS is low, and right channel data is transmitted when I2S_WS is high. Data bits sent by the BCM4325 are
synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK.
The clock rate in master mode is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using a N/M clock divider. In Slave mode, any clock rate is
supported to a maximum of 3.072 MHz.
The I2S_SCK interface is available as multiplexed signals onto:
•
•
PCM interface
Class 1 control signals
Broadcom Corporation
Page 22
I2S Interface
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 8: FM Receiver Subsystem
The BCM4325 includes a completely integrated FM radio receiver with RDS/RBDS, covering all FM bands from 76 MHz to
108 MHz. The receiver is controlled through commands on the BSC bus or the HCI. FM audio is available as stereo analog
output or in digital form through I2S or PCM. The FM subsystem can operate independently or in tandem with the Bluetooth
subsystem and can be powered up or down separately.
SENSITIVITY
The internal LNA has a noise figure (NF) of 6 dB, which helps achieve excellent sensitivity of –107 dBm, or 1 μV in 50Ω.
PLL TUNING
Clocks are locked to a reference clock or a 32.768 kHz external LPO, and no factory alignment is required.
DIGITAL FM OUTPUT
The FM radio audio is available digitally through the shared PCM and I2S pins and the sampling rate is nominally at 48 kHz.
The PCM interface runs off either the FM or the Bluetooth clock. The BCM4325 supports 3-wire I2S audio interface in either
master or slave configuration. The master or slave configuration is selected via HCI commands. In addition, multiple
sampling rates are supported, derived from either the FM or Bluetooth clocks.
ANALOG FM OUTPUT
The demodulated FM audio signal is available as line-level analog stereo output, generated by twin internal 16-bit DACs.
BROADCOM SERIAL CONTROL (BSC) BUS
The BCM4325 implements an I2C-compatible BSC slave bus interface to control the FM subsystem. The BSC bus interface
depends on the reference clock input being active. The interface supports a clock rate up to 400 kHz. The BSC slave address
is programmable using the UART HCI interface and requires a configuration download. The interface supports 7-bit
addressing mode and may require external pull-ups. Initial BSC communication has to be conducted at 100 kHz.
Broadcom Corporation
Document 4325-DS04-R
FM Receiver Subsystem
Page 23
BCM4325
Preliminary Data Sheet
6/30/09
RDS/RBDS
The BCM4325 integrates a RDS/RBDS demodulator and decoder with programmable filtering and buffering functions. The
RDS/RBDS data can be read out through either the HCI or BSC interfaces.
In addition, the RDS/RBDS functionality supports the following:
•
•
•
•
•
•
•
•
•
•
Block decoding, error correction and synchronization
Storage capability up to 126 blocks of RDS data
Full or partial block B match detect and interrupt to host
Audio pause detection with programmable parameters
Program Identification (PI) code detection and interrupt to host
Automatic frequency jump
Block E filtering
Soft mute
Signal dependant mono/stereo blend
Programmable de-emphasis
OTHER FEATURES
•
•
•
•
Single-ended or differential FM RF input
Auto search and tuning
Digital-level indicator (RSSI, IF Frequency)
Low current consumption
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RDS/RBDS
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 9: Wireless LAN Functional Description
INTRODUCTION TO IEEE STD 802.11
IEEE Std 802.11 defines two different ways to configure a wireless network: ad hoc mode and infrastructure mode. In ad
hoc mode, nodes are brought together to form a network on the fly, whereas infrastructure mode uses fixed access points
through which mobile nodes can communicate. These network access points are sometimes connected to wired networks
through bridging or routing functions.
The medium access control (MAC) layer is a contention-resolution protocol that is responsible for maintaining order in the
use of a shared wireless medium. IEEE 802.11 specifies both contention-based and contention-free channel access
mechanisms. The contention-based scheme is also called the distributed coordination function and the contention-free
scheme is also called the point coordination function.
The distributed coordination function employs a carrier sense multiple access with collision avoidance (CSMA/CA) protocol.
In this protocol, when the MAC receives a packet to be transmitted from its higher layer, the MAC first listens to ensure that
no other node is transmitting. If the channel is clear, it then transmits the packet. Otherwise, it chooses a random backoff
factor that determines the amount of time the node must wait until it is allowed to transmit its packet. During periods in which
the channel is clear, the MAC waiting to transmit decrements its backoff counter, and when the channel is busy, it does not
decrement its backoff counter. When the backoff counter reaches zero, the MAC transmits the packet. Because the
probability that two nodes will choose the same backoff factor is low, collisions between packets are minimized. Collision
detection, as employed in Ethernet, cannot be used for the radio frequency transmissions of devices following IEEE 802.11.
The IEEE 802.11 nodes are half-duplex—when a node is transmitting, it cannot hear any other node in the system that is
transmitting because its own signal drowns out any others arriving at the node.
Optionally, when a packet is to be transmitted, the transmitting node can first send out a short request to send (RTS) packet
containing information on the length of the packet. If the receiving node hears the RTS, it responds with a short clear to send
(CTS) packet. After this exchange, the transmitting node sends its packet. When the packet is received successfully, as
determined by a cyclic redundancy check (CRC), the receiving node transmits an acknowledgment (ACK) packet. This back
and forth exchange is necessary to avoid the hidden node problem. Hidden node is a situation where node A can
communicate with node B, node B can communicate with node C, but node A cannot communicate with node C. For
instance, although node A can sense that the channel is clear, node C can be transmitting to node B. This protocol alerts
node A that node B is busy, and that it must wait before transmitting its packet.
IEEE 802.11A/G MAC FEATURES
The IEEE 802.11a/g MAC features include:
•
•
•
•
•
•
•
Programmable independent basic service set (IBSS), or infrastructure mode
Passive scanning
Network allocation vector (NAV), inter-frame space (IFS), and timing synchronization function (TSF) functionality
Backoff
RTS/CTS procedure
Transmission of response frames (ACK/CTS)
Address filtering of RX frames as specified by IBSS rules
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Document 4325-DS04-R
Wireless LAN Functional Description
Page 25
BCM4325
Preliminary Data Sheet
6/30/09
•
•
•
Multirate support
Frame-bursting and afterburner
Programmable target beacon transmission time (TBTT), beacon transmission/cancellation and programmable
announcement traffic indication message (ATIM) window
•
•
CF conformance: setting NAV for neighborhood point coordination function operation
Privacy through a variety of Wired Equivalent Privacy (WEP) encryption schemes and dynamically programmable WEP
keys
•
•
Power management
Statistics counters for MIB support
IEEE 802.11A/G MAC DESCRIPTION
The MAC core provides the support required for the transmission and reception of sequences of packets, together with
related timing, without any packet-by-packet driver interaction. Time critical tasks requiring response times of only a few
milliseconds are handled in the MAC core. This achieves the required timing on the medium while keeping the host driver
easier to write and maintain. Also, incoming packets are buffered in the MAC core, which allows the MAC driver to process
them in bursts as and when it gets access to the buffers.
The MAC driver interacts with the MAC core to prepare queues of packets to transmit and to analyze and forward received
packets. The internal blocks of the MAC core are connected to a Programmable State Machine (PSM) through an internal
bus. See Figure 9.
Control/Status Registers and Interface to ARM7
4 Tx FIFOs
Template
Tx Status FIFO
Tx FIFO
Code Memory
Programmable
State Machine
(PSM)
Wireless Security Engine
Power
management
Tx Engine
Rx Engine
Timing and
Control
Data Memory
PHY Interface
Figure 9: IEEE 802.11a/g MAC Block Diagram
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IEEE 802.11a/g MAC Description
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
There are registers for controlling and monitoring the status of the MAC core and interfacing with the TX/RX FIFOs. There
are four transmit FIFOs: asynchronous, priority, Broadcast/Multicast (BC/MC) and ATIM. Each transmit FIFO is 3 KB deep.
In addition to the transmit FIFOs, there is a 1-KB template area for response frames. Whenever the CPU has a frame to
transmit, the CPU queues the frame into one of the transmit FIFOs with a TX descriptor containing TX control information.
The PSM schedules the transmission on the medium depending on the frame type, transmission rules in IEEE 802.11
protocol, and the current medium occupancy scenario. After the transmission is completed and an ACK is received, a TX
status is returned to the host confirming the same in the TX status FIFO.
The MAC contains a single 4.5 KB RX FIFO. Whenever a frame is received, the frame is sent to the ARM processor along
with an RX descriptor that contains additional information about the frame reception conditions.
The Power Management block maintains the information regarding the power management state of the core to help in
dynamic decisions by the core regarding frame transmission.
The WEP block performs the required WEP operation on the TX/RX frames. The WEP block supports separate transmit and
receive keys with four shared keys and 50 link-specific keys. The link-specific keys are used to establish a secure link
between any two STAs, with the required key being shared between only those two STAs and hence excluding all the other
STAs in the same network from deciphering the communication between those two STAs. The WEP block supports the
following encryption schemes that can be selected on a per destination basis:
•
•
•
•
•
•
None: The WEP block acts as a passthrough
WEP: 40-bit secure key and 24-bit IV as defined in IEEE Std 802.11-1999
WEP128: 104-bit secure key and 24-bit IV
WEP2: 128-bit secure key and 128-bit IV
TKIP: 802.11i
AES: 802.11i
The transmit engine is responsible for the byte flow from the TX FIFO to the PHY interface through the WEP block and the
addition of an FCS (CRC-32) as required by IEEE 802.11. Similarly, the receive engine is responsible for byte flow from the
PHY interface to the RX FIFO through the WEP block and for detection of errors in the RX frame.
The timing block performs the TSF, NAV, and IFS functionality as described in IEEE 802.11-1999.
The Programmable State Machine (PSM) coordinates the operation of different hardware blocks required for both
transmission and reception. The PSM also maintains the statistics counters required for MIB support.
IEEE 802.11A/G PHY FEATURES
The integrated IEEE 802.11a/g physical layer device (PHY) features include:
•
•
•
•
•
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 Mbit/s
Programmable antenna selection
Automatic gain control (AGC)
Available per packet channel quality and signal strength measurements
Dual antenna support with single weight combiner
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Document 4325-DS04-R
IEEE 802.11a/g PHY Features
Page 27
BCM4325
Preliminary Data Sheet
6/30/09
IEEE 802.11A/G PHY DESCRIPTION
The Wireless Local Area Network (WLAN) PHY integrated in this IC provides baseband processing at data rates of 1, 2, 5.5,
6, 9, and 11, 12, 18, 24, 36, 48, and 54 Mbit/s, as specified in the direct sequence spread spectrum (DSSS) and orthogonal
frequency division multiplexing (OFDM) portions of IEEE 802.11a/g. This core acts as an intermediary between the MAC on
the one hand, and the integrated 2.4 GHz/5 GHz radio integrated circuit on the other, converting back and forth between
packets and baseband waveforms.
An overview of the operations carried out by the PHY is shown on Figure 10. Upon transmission, physical layer framing is
first added to a packet received from the MAC. The resulting bits are then scrambled, modulated, filtered, and finally sent to
the radio through a pair of 80 MHz, 9-bit Digital-to-Analog Converters (DACs). Modulation is selected per packet as either
differential binary phase shift keying (DBPSK), differential quadrature phase shift keying (DQPSK), complementary code
keying (CCK), or OFDM. The first two types of modulation provide data rates of 1 Mbps and 2 Mbps, respectively, and
require spreading the modulated symbols with a length 11 Barker code. CCK modulation is used for data rates of 5.5 Mbps
and 11 Mbps and inherently includes the spreading. OFDM modulation is used for data rates of 6, 9, 12, 18, 24, 36, 48, and
54 Mbps. A high data rate is achieved by using multiple carriers that are modulated using binary or quadrature phase shift
keying (BPSK or QPSK) or using 16- or 64-quadrature amplitude modulation (16 QAM or 64 QAM).
MAC Interface
Descramble and
Frame and Scramble
Deframe
RX FSM
TX FSM
Rake Receiver and
DPSK Demodulation
Equalizer and CCK
Demodulation
Modulate/Spread
PHY Registers
Timing and Frequency Correction
TX Filter
DAC
COFDM
Sync/AGC
ADC
2.4-GHz/5-GHz Dual-Band Radio Interface
Figure 10: IEEE 802.11a/g PHY Block Diagram
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IEEE 802.11a/g PHY Description
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
On reception, the reverse operations are performed. The inphase (I) and quadrature (Q) baseband waveforms coming from
a pair of 40 MHz, 9-bit ADCs are demodulated into bits and then descrambled and deframed. To improve the likelihood of
correct reception, however, the waveforms are subjected to timing and frequency offset corrections (adapted throughout
packet reception) prior to demodulation.
Additionally, the receiver must perform synchronization at the start of packet reception, which includes automatic gain control
(AGC), antenna selection, and frequency offset and timing estimation. A state machine coordinates all of these activities
(using information from the PHY framing) to decide how to handle the packet body.
A register interface accessible from both the MAC and the host allows programming of the PHY parameters, although
information generally needed per packet is passed as part of the packet itself. For example, this is true of preamble type and
data rate on transmission, as well as the channel metrics signal quality (SQ) and signal strength on reception. The internal
radio registers are accessed indirectly through the PHY registers.
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Document 4325-DS04-R
IEEE 802.11a/g PHY Description
Page 29
BCM4325
Preliminary Data Sheet
6/30/09
Section 10:WLAN 802.11 Radio Subsystem
The BCM4325 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz or 5 GHz
Wireless LAN systems. It is designed to provide low-power, low-cost, and robust communications for applications operating
in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. With an external transmit power amplifier, it develops
full output power per the IEEE 802.11a/g Specification. The transmit and receive sections include all on-chip filtering, mixing,
and gain control functions.
Note: Sharing a single 2.4 GHz antenna between the Bluetooth and WLAN sections is supported when an
appropriate SP3T switch is used in the external RF signal path.
Phase
Shifter
5-GHz
RF Input
LNA
Rx I
LPF
LPF
To Baseband
5-GHz
RF Input
Phase
Shifter
LNA
LNA
MUX
Rx Q
2.4-GHz
RF Input
Phase
Shifter
2.4-GHz
RF Input
Phase
Shifter
LNA
5 GHz
2.4 GHz
2.4 GHz
LO
Generation
Reference Clock
To Bluetooth
PLL
5 GHz
5-GHz
RF Output
Tx I
LPF
LPF
AMP
AMP
From Baseband
Tx Q
MUX
2.4-GHz
RF Output
Control Interface
Control
Interface
Calibration
Figure 11: Radio Functional Block Diagram
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WLAN 802.11 Radio Subsystem
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
RECEIVER PATH
The BCM4325 has a wide dynamic range, direct conversion receiver. It employs high order on-chip channel filtering to
ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. The excellent noise figure of the
receiver makes an external LNA unnecessary.
TRANSMITTER PATH
A linear, on-chip power amplifier is included. This power amplifier is capable of delivering 20 dBm of nominal output power
and adheres to IEEE 802.11a and 802.11g specifications. The Tx gain has a 32 dB range with a resolution of 0.25 dB.
Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5 GHz U-NII bands, respectively.
CALIBRATION
The BCM4325 features dynamic on-chip calibration, eliminating process variation across components. This enables the
BCM4325 to be used in high volume applications, because calibration routines are not required during manufacturing
testing. These calibration routines are performed periodically in the course of normal radio operation. An example of this is
automatic calibration of the baseband filters for optimum transmit and receive performance.
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Document 4325-DS04-R
Receiver Path
Page 31
BCM4325
Preliminary Data Sheet
6/30/09
Section 11: WLAN Power Management
The BCM4325 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas
of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce
leakage current and supply voltages. Additionally, the BCM4325 integrated RAM is a high Vt memory with dynamic clock
control. The dominant supply current consumed by the RAM is leakage current only.
Additionally, the BCM4325 includes an advanced WLAN power management unit (PMU). The PMU provides significant
power savings by putting the BCM4325 into various power management states appropriate to the current environment and
activities that are being performed. The power management unit enables and disables internal regulators, switches, and
other blocks based on a computation of the required resources and a table that describes the relationship between resources
and the time needed to enable and disable them. Power up sequences are fully programmable. Configurable, free running
counters (running at 32 kHz LPO clock) in the PMU are used to turn on/turn off individual regulators and power switches.
Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever
possible.
The BCM4325 WLAN power states are described as follows:
•
•
Power-down mode The BCM4325 is effectively powered off by shutting down all internal regulators. The chip is
brought out of this mode by external logic reenabling the internal regulators.
Active mode
All BCM4325 WLAN functions are powered up and fully functional with active carrier sensing and
frame transmission and receiving. All required regulators are enabled and put in the most efficient
mode (PWM or Burst) based on the load current. Clock speeds are dynamically adjusted by the
PMU.
•
Sleep mode
The WLAN radio, AFE, PLLs, and the ROMs are powered down. The rest of the BCM4325
remains powered up in an IDLE state. All main clocks are shut down. The 32 kHz LPO clock is
available only for the PMU. This condition is necessary to allow the PMU to wake up the chip and
transition to active mode. In Sleep mode, the primary power consumed is due to leakage current.
The external switcher and internal baseband switcher are put into Burst mode (for better efficiency
at low load currents).
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WLAN Power Management
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 12: WLAN System Interfaces
SDIO V1.2
The BCM4325 WLAN section supports SDIO version 1.2 for both the 1-bit (25 Mbps), 4-bit (100 Mbps) modes, and high
speed 4-bit (50 MHz clocks – 200 Mbps). It has the ability to stop the SDIO clock and map the interrupt signal into a GPIO
pin. This out-of-band interrupt signal notifies the host when the WLAN device needs to turn on the SDIO interface.
The ability to force control of the gated clocks from within the WLAN chip is also provided.
Three SDIO functions are supported:
•
•
Function 0—Standard SDIO function (Max BlockSize/ByteCount = 32B)
Function 1—Backplane Function to access the internal System On Chip (SOC) address space (Max BlockSize/
ByteCount = 64B)
•
Function 2—WLAN Function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount = 512B)
Detailed SDIO pin description and signal connection block diagrams are provided in Section 14: “Pinout and Signal
Descriptions” on page 37.
GPIO INTERFACE
There are five General Purpose I/O (GPIO) pins available on the FBGA package and 15 on the WLCSP package, which can
be used to connect to various external devices. Upon power up and reset, these pins become tri-stated. Subsequently, they
can be programmed to be either input or output pins via the GPIO control register. An internal pull-up resistor is included on
each GPIO. If a GPIO output enable is not asserted, and the corresponding GPIO signal is not being driven externally, the
GPIO is read as high.
ONE-TIME-PROGRAMMABLE (OTP) MEMORY
Various hardware configuration parameters may be stored in an internal 2k-bit OTP memory, which is read by system
software after device reset. In addition, customer-specific parameters, including the System Vendor ID and the MAC address
can be stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP device is 0. Once any bits are programmed to a 1, they can never be
reprogrammed back to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with
Broadcom's WLAN manufacturing test tools. Alternatively multiple write cycles can be used to selectively program specific
bytes, but only bits which are still in the 0 state can be altered during each programming cycle.
Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with
the reference board design package. Documentation on the OTP development process is available at Broadcom’s Customer
Support Portal (CSP) at http://www.broadcom.com/support.
As an alternative to using the internal OTP, an external 4-wire SPROM interface can be enabled.
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Document 4325-DS04-R
WLAN System Interfaces
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BCM4325
Preliminary Data Sheet
6/30/09
EXTERNAL COEXISTENCE INTERFACE
An external handshake interface is provided to enable signaling between the device and an external co-located wireless
device, such as GPS, WiMax or UWB, to manage wireless medium sharing for optimum performance. The provided signals
are:
•
•
•
•
•
ERCX_STATUS
ERCX_RF_ACTIVE
ERCX_TX_FREQ
ERCX_TX_PRISEL (WLCSP package only)
ERCX_TXCONF (WLCSP package only)
JTAG INTERFACE
The BCM4325 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly
testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by using proprietary
debug and characterization test tools during board bringup. Therefore, it is highly recommended to provide access to the
JTAG pins by means of test points or a header on all PCB designs.
WLAN UART DEBUG INTERFACE
Two universal asynchronous receiver/transmitter (UART) interfaces are provided for the 339-pin WLCSP package (one
UART interface for the 196-ball FBGA package) that can be attached to RS-232 data termination equipment (DTE) for
exchanging and managing data with other serial devices. These UART interfaces are primarily used for debugging during
development. Each interface is compatible with the industry standard 16550 UART. One UART provides TX and RX signals
only. The other UART provides a full set of control signals. Hardware assisted flow control is provided. FIFO size is 64 × 8.
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External Coexistence Interface
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Preliminary Data Sheet
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BCM4325
Section 13:Software Architecture
HOST SOFTWARE ARCHITECTURE
The host driver provides a transparent connection between the host operating system and the BCM4325 media (for example,
WLAN) by presenting a network driver interface to the host operating system and communicating with the BCM4325 over
an interface-specific bus (SPI, SDIO, and so on) to:
•
•
Forward transmit and receive frames between the host network stack and the BCM4325 device, and
Pass control requests from the host to the BCM4325 device, returning the BCM4325 device responses
The driver communicates with the BCM4325 over the bus using a control channel and a data channel to pass control
messages and data messages. The actual message format is based on the BDC protocol.
DEVICE SOFTWARE ARCHITECTURE
The wireless device, protocol, and bus drivers are run on the embedded ARM® processor and a Broadcom-defined operating
system called HNDRTE that enables the transfer of 1500-byte Ethernet frames and control frames (using BDC message
sets) over the SDIO interface between the host and the device.
This transfer requires a message-oriented (framed) interconnect between the host and device. The SDIO bus is an
addressed bus—each host-initiated bus operation contains an explicit device target address—and does not natively support
a higher level data frame concept. Broadcom has implemented a hardware/software message encapsulation scheme that
ignores the bus operation code address and prefixes each frame with a 4-byte length tag for framing. The device presents
a packet level interface over which data, control and asynchronous event (from the device) packets are supported.
The data and control packets received from the bus are initially processed by the bus driver and then passed on to the
protocol driver. If the packets are data packets, they are transferred to the wireless device driver (and out through its
medium), and a data packet received from the device medium follows the same path in the reverse direction. If the packets
are control packets, the protocol header is decoded by the protocol driver. If the packets are wireless IOCTL packets, the
IOCTL API of the wireless driver is called to configure the wireless device. The microcode running in the D11 core processes
all time critical tasks.
Broadcom Corporation
Document 4325-DS04-R
Software Architecture
Page 35
BCM4325
Preliminary Data Sheet
6/30/09
REMOTE DOWNLOADER
The remote downloader is used to download the BCM4325 firmware image into the device from the host. When the
BCM4325 device powers up, it is ready to receive the firmware image from the host system.
SPI/SDIO
BDC Protocol
Wireless Device Driver
D11 Core
Figure 12: Device Software Architecture
WIRELESS CONFIGURATION UTILITY
The device driver that supports the Broadcom IEEE 802.11 family of wireless solutions provides an input/output control
(IOCTL) interface for making advanced configuration settings. The IOCTL interface makes it possible to make settings that
are normally not possible when using just the native operating system-specific IEEE 802.11 configuration mechanisms. The
utility uses IOCTLs to query or set a number of different driver/chip operating properties.
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Wireless Configuration Utility
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 14: Pinout and Signal Descriptions
SIGNAL ASSIGNMENTS
196-BALL FBGA PINOUT
Table 6: 196-Ball FBGA Signal Assignments by Ball Number
Ball Signal
Ball Signal
Ball Signal
Ball Signal
C9
WRF_AFE_TEST_ONI
F3
ERCX_STATUS
H11
H12
H13
H14
J1
WRF_GPIO_OUT2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
SR_VFB1
C10
C11
C12
C13
C14
D1
WRF_AFE_TSSI_A
AVSS
F4
VDDIO
WRF_VDDVCO_1P2
WRF_VDDPFDCP_1P2
AVSS
SR_VBAT1B
F5
TCK
SR_VLX1
AVSS
F6
AMODE_RX_PU
GMODE_RX_PU
VSS
WL_RST_N
AVSS
F7
VDDIO_SD
RF_SW_CTRL_N_3
AMODE_TX_PU
RF_SW_CTRL_N_0
WRF_DISABLE_N
WRF_EXTCOUPLE_AIN
WRF_EXTCOUPLE_GIN
WRF_VDDPAG_3P3
WRF_RFOUTP_G
AVSS
AVSS
F8
J2
WL_GPIO_2
SDIO_DATA_2
WL_UART_TX0
WL_GPIO_7
SPROM_CS
BT_PCM_CLK
BT_TM6
SR_VFBBB
F9
VDDIO_RF
VDDIO_RF
WRF_AFE_TEST_QN
AVSS
J3
D2
WL_REG_ON
SR_AVSS
F10
F11
F12
F13
F14
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
H1
J4
D3
J5
D4
TMS
J6
D5
LV_TESTMODE
GMODE_EXT_LNA_GAIN
WRF_AFE_AVDD_TXDAC
WRF_AFE_TEST_ONQ
WRF_AFE_TEST_OPQ
WRF_AFE_AVDD_AUX
WRF_AFE_TEST_IP
WRF_VDDTX_1P2
AVSS
WRF_PA_100UA
WRF_RFINP_G1
SR_VOUTBB
WL_GPIO_6
WL_GPIO_1
ERCX_RF_ACTIVE
WL_GPIO_0
VDDIO
J7
D6
J8
D7
J9
BT_GPIO_0
BT_VSSC_0
BT_VDDC
D8
J10
J11
J12
J13
J14
K1
WRF_RFOUTP_A
SR_AVDD2P5
D9
D10
D11
D12
D13
D14
E1
WRF_VDDD_1P2
WRF_VDDCAB_1P2
BT_RFION
SR_PLDO
SR_VBAT1A
JTAG_TRST_N
RF_SW_CTRL_P_3
RF_SW_CTRL_N_1
RF_SW_CTRL_P_0
GMODE_TX_PU
VSS
SDIO_CLK
WRF_RFINP_A1
SR_VLX1BB
BT_VDDO
K2
XTAL_PU
VDDC
K3
SPROM_CLK
SDIO_CMD
E2
SR_VBATBB
AVSS
K4
E3
BT_REG_ON
WRF_GPIO_OUT1
WRF_VDDLO_1P2
AVSS
K5
BT_PCM_IN
BT_GPIO_4
BT_GPIO_5
BT_GPIO_7
BT_TM1
WRF_AFE_AVDD_RXAD
C
E4
VSS
K6
B10
B11
B12
B13
B14
C1
WRF_AFE_TEST_IN
AVSS
E5
TDI
K7
E6
TAP_SEL
WRF_RFINN_G1_XFMR
SPROM_DOUT
SDIO_DATA_1
WL_UART_RX0
VDDC
K8
AVSS
E7
RF_SW_CTRL_P_1
VSS
K9
WRF_VDDPAA_3P3
AVSS
E8
H2
K10
K11
K12
K13
K14
L1
BT_GPIO_2
WRF_VDDA_1P2
BT_VDDRF
E9
WRF_AFE_TSSI_G
WRF_BBPLL_VDD_1P2
WRF_AFE_TEST_QP
WRF_AFE_IQADC_VREF
WRF_VDDRX_1P2
WRF_RFINN_A1_XFMR
SR_VLX2BB
H3
SR_VNLDO
SR_TESTSWG
SR_PVSS
E10
E11
E12
E13
E14
F1
H4
C2
H5
OTP_VDD25
VDDIO
BTFM_VSS
C3
H6
BT_RFIOP
C4
TDO
H7
ERCX_TX_FREQ
SPROM_DIN
BT_GPIO_1
VDDC
VOUT_CLDO
SDIO_DATA_0
VDDIO_SD
C5
TEST_SE
H8
L2
C6
VDDIO_RF
H9
L3
C7
WRF_AFE_DIGIT_TEST1
WRF_AFE_TEST_OPI
F2
SR_PVSSB
H10
L4
BT_SDA
C8
Broadcom Corporation
Document 4325-DS04-R
Pinout and Signal Descriptions
Page 37
BCM4325
Preliminary Data Sheet
6/30/09
Ball Signal
Ball Signal
L5
BT_PCM_OUT
P10
P11
P12
P13
P14
FM_VDDRF
L6
BT_GPIO_6
BT_UART_RXD
BT_TM2
FM_RXP
L7
FM_RXN
L8
FM_VDDIF
BT_VDDPLL
L9
FM_ADVSS
VDD_XTAL
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
WRF_RES_EXT
WRF_EXTREFIN
BT_VDDIFIFP
BT_VDDTF
VOUT_LNLDO1
VIN_CLDO
VIN_LNLDO1
BT_VSSC_0
BT_PCM_SYNC
BT_GPIO_3
FM_AUDIO_OUT1
FM_ADVDD
FM_AUDIO_OUT2
FM_VDDVCO
FM_CVAR
BTFM_VSS
BT_VDDVCO
BTFM_VSS
VIN_LNLDO2
BT_VDDO
N2
N3
AVDD2P5_LDO
BT_VDDC
N4
N5
BT_SCL
N6
BT_UART_RTS_N
BT_COEX_OUT0
BT_TM0
N7
N8
N9
BT_RST_N
N10
N11
N12
N13
N14
P1
FM_VDDPLL
BTFM_VSS
N/C
N/C
BTFM_VSS
VREF_LDO
P2
AVSS1_LDO
VOUT_LNLDO2
BT_UART_TXD
BT_UART_CTS_N
SDIO_DATA_3
BT_COEX_OUT1
OSCIN
P3
P4
P5
P6
P7
P8
P9
OSCOUT
Broadcom Corporation
Page 38
Signal Assignments
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
339-PIN WLCSP PINOUT
Note: The X- and Y-coordinate orientation is looking at the silicon face (i.e., looking up at the bottom of the die at the bumps,
as opposed to top down). Refer to Figure 36 on page 116 for X- and Y-coordinate origin information.
Note: The WLCSP package was optimized and eight pins were removed (originally 347-pin WLCSP package). However, the
CSP package pin out was not renumbered. The following pins were removed: Pin 1 WRF_PA_BYPGND_3P3, Pin 154
VOUT_LNLDO3, Pin 157 VIN_LNLDO3, Pin 258 usb20d_ulpi_stp, Pin 282 usb20d_ulpi_data_6, Pin 283 usb20d_ulpi_data_5,
Pin 295 usb20d_ulpi_data_7, and Pin 307 usb20d_ulpi_nxt
Table 7: 339-Pin WLCSP Signal Assignments by Pin Number and X- and Y-Coordinates
Pin # Signal Name
X-Coord Y-Coord
211.8 4063.055
Pin # Signal Name
X-Coord Y-Coord
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
WRF_RFINP_A1
WRF_EXTCOUPLE_GIN
WRF_BBPLL_GND_1P2
WRF_GNDLO_1P2
WRF_RFINN_A1_XFMR
WRF_VDDRX_1P2
WRF_GNDRX_1P2
WRF_VDDLO_1P2
WRF_GPIO_OUT1
WRF_GPIO_OUT2
WRF_RFINN_G2_XFMR
WRF_PA_100UA
WRF_RFINP_G2
WRF_RFINP_G1
WRF_VDDVCO_1P2
WRF_GNDVCO_1P2
WRF_RFINN_G1_XFMR
WRF_GNDD_1P2
WRF_VDDD_1P2
WRF_GNDPFDCP_1P2
WRF_VDDPFDCP_1P2
WRF_GNDA_1P2
WRF_VDDA_1P2
WRF_VDDCAB_1P2
WRF_GNDCAB_1P2
WRF_EXTREFIN
WRF_RES_EXT
2
WRF_RFOUTN_A
184.63
684.63
5538.005
5538.005
5538.005
5538.005
5538.005
5538.005
5538.005
5538.005
5254.51
2676.285 4051.17
2926.285 4036.35
1544.575 3877.305
3
WRF_VDDPAA_3P3
WRF_VDDPAA_3P3
WRF_RFOUTP_A
WRF_RFOUTN_G
WRF_VDDPAG_3P3
WRF_VDDPAG_3P3
WRF_RFOUTP_G
4
434.63
5
934.63
1184.63
1684.63
1434.63
1934.63
2186.84
211.8
461.8
711.8
3784.06
3784.06
3605.83
6
7
8
1544.575 3627.305
1794.575 3627.305
2044.575 3627.305
9
10
WRF_AFE_pad_AVSS_
RXADC
11
12
WRF_AFE_AVDD_RXADC 2523.96
5254.245
5254.245
211.8
461.8
211.8
211.8
3534.045
3534.045
3244.045
2956.455
WRF_AFE_pad_AVSS_
TXDAC
2773.96
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
WRF_AFE_AVDD_TXDAC 3073.81
5254.245
4933.17
4822.4
WRF_GNDPAA_3P3
WRF_GNDTX_1P2
WRF_GNDPAA_3P3
WRF_GNDPAG_3P3
WRF_GNDPAG_3P3
WRF_AFE_test_In
184.63
1305.455 2993.545
1555.455 2993.545
419.98
934.63
4933.17
4902.645
4902.645
4954.545
5004.235
5004.235
4704.5
211.8
711.8
961.8
211.8
461.8
711.8
961.8
211.8
461.8
2666.455
2655
2655
2405
2405
2405
2405
2155
2155
1184.63
1934.63
2182.26
2823.81
3073.81
2182.26
2573.81
2823.81
3073.81
211.8
WRF_AFE_test_opI
WRF_AFE_test_onQ
WRF_AFE_test_Ip
WRF_AFE_TSSI_A
WRF_AFE_test_onI
WRF_AFE_test_opQ
WRF_RFINN_A2_XFMR
WRF_VDDTX_1P2
WRF_AFE_iqadc_VREF
WRF_AFE_AVDD_AUX
WRF_AFE_TSSI_G
WRF_RFINP_A2
4779.235
4754.235
4754.235
4663.165
1818.185 2155
2068.185 2155
1551.915 4506.545
BT_RFION
202
452
893
202
452
202
452
202
1875
1875
1847
1625
1625
1375
1375
1125
2182.26
2573.81
3073.81
211.8
4453.92
4529.235
4504.235
4384.17
BT_VDDRF
BT_VSSRF
BT_RFIOP
BT_VSSPA
WRF_EXTCOUPLE_AIN
WRF_BBPLL_VDD_1P2
WRF_AFE_test_Qp
WRF_AFE_test_Qn
2676.285 4301.17
2926.285 4301.17
BT_VDDTF
BT_VSSIF
2196.31
2446.31
4202.195
4202.195
BT_VDDIF
Broadcom Corporation
Document 4325-DS04-R
Signal Assignments
Page 39
BCM4325
Preliminary Data Sheet
6/30/09
Pin # Signal Name
X-Coord Y-Coord
Pin # Signal Name
X-Coord Y-Coord
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
FM_ADVSS
FM_ADVDD
BT_VDDVCO
FM_VSSVCO
FM_AUDIO_OUT2
FM_AUDIO_OUT1
BT_VDDPLL
BT_VSSVCO
BT_VSSPLL
No Connect (NC)
No Connect (NC)
FM_VSSRX
FM_CVAR
2468
2839
202
935
935
748
744
685
685
435
435
435
435
435
435
435
435
435
435
185
185
185
185
185
185
185
185
185
185
150
5548
5548
5548
5548
5548
5548
5548
117 SR_AVSS
4872.985 4895.4
5122.985 4895.4
5622.985 4895.4
6122.985 4895.4
118 SR_VBAT1A
119 SR_AVSS
1492
2468
2839
150
120 SR_VDDNLDO
121 BT_REG_ON
122 SR_VBATBB
123 SR_VBATBB
124 SR_VFBBB
125 WL_REG_ON
126 SR_VBATBB
127 SR_VBATBB
128 SR_VBATBB
129 SR_VLX1BB
130 SR_VLX1BB
131 SR_VLX1BB
132 SR_VLX1BB
133 SR_PVSSB
134 SR_PVSSB
135 SR_PVSSB
136 SR_PVSSB
137 SR_VLX2BB
138 SR_VLX2BB
139 SR_VLX2BB
140 SR_VLX2BB
141 SR_VOUTBB
142 SR_VOUTBB
143 SR_VOUTBB
144 SR_VOUTBB
145 VIN_CLDO
5498
5748
5998
6248
4676
4676
4676
4676
400
650
5372.985 4459.4
5622.985 4459.4
5872.985 4459.4
6122.985 4459.4
900
1150
1400
1650
1900
2150
2400
150
5498
5748
5998
6248
4240
4240
4240
4240
FM_VSSPLL
VSS_XTAL
VDD_XTAL
DUMMY_BUMP
FM_VSSIF
5372.985 4023.4
5622.985 4023.4
5872.985 4023.4
6122.985 4023.4
400
FM_VDDIF
650
FM_RXN
900
FM_RXP
1150
1400
1650
1900
2150
2400
2650
4748
4998
5248
5498
5748
5998
6248
5498
5748
5998
6248
3804
3804
3804
3804
FM_VDDRX
FM_VDDVCO
FM_VDDPLL
oscin
5372.985 3587.4
5622.985 3587.4
5872.985 3587.4
6122.985 3587.4
oscout
BT_RST_N
SR_VFB2
SR_VLX2
5497.96
5747.96
1118.285
1118.285
100 SR_VBAT1A
101 SR_VLX1
146 VIN_CLDO
147 VOUT_CLDO
148 VOUT_CLDO
149 VIN_LNLDO1
150 VIN_LNLDO1
151 VOUT_LNLDO1
152 VOUT_LNLDO1
153 AVSS1_LDO
155 VIN_LNLDO2
156 VOUT_LNLDO2
158 VIN_LNLDO4
159 VOUT_LNLDO4
160 AVDD2P5_LDO
161 AVSS2_LDO
162 VREF_LDO
163 packageoption_0
164 rf_sw_ctrl_n_0
5997.965 1118.285
102 SR_PVSS1
103 SR_VFB1
6247.97
5497.96
5747.96
1118.285
868.285
868.285
104 SR_VBAT1B
105 SR_PVSS2
106 SR_VLX2
4872.985 5331.4
5122.985 5331.4
5372.985 5331.4
5622.985 5331.4
5872.985 5331.4
6122.985 5331.4
5997.965 868.285
6247.97
5497.96
868.285
618.285
107 SR_VBAT1A
108 SR_VLX1
5997.965 618.285
6247.97 618.285
5997.965 368.285
109 SR_PVSS1
110 SR_VSSPLDO
111 SR_PVSS2
112 SR_VBAT1A
113 SR_VLX1
4998
5248
5498
5748
5998
6248
5112
5112
5112
5112
5112
5112
6247.97
5747.96
368.285
118.285
5997.965 118.285
114 SR_PVSS1
115 SR_TESTSWG
116 SR_AVDD2P5
6247.97
3325
118.285
5400
3575
5400
Broadcom Corporation
Page 40
Signal Assignments
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Pin # Signal Name
X-Coord Y-Coord
Pin # Signal Name
X-Coord Y-Coord
165 VDDIO_RF
166 test_se
4075
4325
3325
3575
3825
4075
4325
4575
3325
3575
3825
4075
4325
4575
3325
3575
3825
4075
4325
4575
3275
3525
3775
4025
4275
4525
4775
5025
3525
3775
4025
4275
4525
4775
5025
3275
3525
3775
4025
4275
4525
4775
5025
3275
3525
3775
5400
5400
5150
5150
5150
5150
5150
5150
4900
4900
4900
4900
4900
4900
4650
4650
4650
4650
4650
4650
4150
4400
4400
4400
4400
4400
4400
4400
4150
4150
4150
4150
4150
4150
4150
3900
3900
3900
3900
3900
3900
3900
3900
3650
3650
3650
211 VDD
4025
4275
4525
4775
5025
3775
4025
4275
4525
4775
5025
4025
4275
4525
4775
5025
5275
5525
5775
6025
3025
3775
4275
4525
4775
5025
5275
5525
5775
6025
3025
3275
3525
3775
4025
4275
5025
5275
5525
5775
6025
3025
3275
3525
3775
4025
3650
3650
3650
3650
3650
3400
3400
3400
3400
3400
3400
3150
3150
3150
3150
3150
3150
3150
3150
3150
2900
2900
2900
2900
2900
2900
2900
2900
2900
2900
2650
2650
2650
2650
2650
2650
2650
2650
2650
2650
2650
2400
2400
2400
2400
2400
212 VSS
167 packageoption_1
168 rf_sw_ctrl_p_0
169 wrf_afe_digit_test1
170 rf_sw_ctrl_p_2
171 tdo
213 WL_GPIO_0
214 sflash_d
215 ercx_rf_active
216 VDDIO
217 VDD
172 jtag_trst_n
173 packageoption_2
174 rf_sw_ctrl_n_1
175 gmode_ext_lna_gain
176 rf_sw_ctrl_n_2
177 tap_sel
218 VSS
219 ercx_tx_freq
220 VDD
221 VDD
222 VSS
223 VDDIO
178 WL_RST_N
179 packageoption_3
180 wrf_disable_n
181 rf_sw_ctrl_p_1
182 amode_tx_pu
183 lv_testmode
184 tck
224 WL_GPIO_13
225 WL_GPIO_7
226 VDDIO
227 VDDIO
228 sflash_c
229 sflash_s
230 ercx_txconf
231 BT_VDDO
232 VDD
185 VDDIO_RF
186 gmode_rx_pu
187 gmode_tx_pu
188 amode_ext_lna_gain
189 rf_sw_ctrl_n_3
190 tdi
233 sprom_din
234 otp_vdd25
235 WL_GPIO_14
236 WL_GPIO_9
237 WL_GPIO_5
238 WL_GPIO_4
239 WL_GPIO_2
240 WL_GPIO_1
241 BT_VSSC_0
242 BT_VDDO
243 BT_VDDO
244 VDD
191 tms
192 VSS
193 VDDIO_RF
194 VDDIO_RF
195 wrf_afe_digit_test2
196 amode_rx_pu
197 rf_sw_ctrl_p_3
198 VDDIO_RF
199 ercx_prisel
200 VDD
245 VSS
246 sprom_cs
247 wl_uart_rx0
248 WL_GPIO_12
249 WL_GPIO_10
250 WL_GPIO_8
251 WL_GPIO_6
252 BT_GPIO_1
253 BT_VSSC_0
254 BT_VSSC_0
255 BT_VSSC_0
256 VSS
201 VDD
202 VDD
203 VDD
204 VSS
205 VDDIO_RF
206 sflash_q
207 ercx_status
208 VSS
209 VSS
210 VDDIO
Broadcom Corporation
Document 4325-DS04-R
Signal Assignments
Page 41
BCM4325
Preliminary Data Sheet
6/30/09
Pin # Signal Name
X-Coord Y-Coord
Pin # Signal Name
X-Coord Y-Coord
257 VDDIO_SD
259 wl_uart_tx0
260 wl_uart_tx1
261 WL_GPIO_15
262 WL_GPIO_11
263 BT_XA_18
4525
5275
5525
5775
6025
2525
2775
3025
3275
3525
3775
4025
4275
4525
4775
2400
2400
2400
2400
2400
2150
2150
2150
2150
2150
2150
2150
2150
2150
2150
2150
2150
2150
1900
1900
1900
1900
1900
1900
1900
1900
1900
1900
1650
1650
1650
1650
1650
1650
1650
1650
1650
1400
1400
1400
1400
1400
1400
1400
1400
1400
308 BT_XCS_N
309 BT_TM0
3255
3505
3755
4005
4255
4505
4755
5005
3255
3505
3755
4005
4255
4505
4755
5005
3255
3505
3755
4005
4255
4505
4755
5005
3525
3775
4025
4275
4525
4775
5025
3525
3775
4025
4275
4525
4775
5025
5275
5525
1150
1150
1150
1150
1150
1150
1150
1150
900
900
900
900
900
900
900
900
650
650
650
650
650
650
650
650
400
400
400
400
400
400
400
150
150
150
150
150
150
150
150
240
310 BT_XA_5
311 BT_XA_9
312 BT_XA_13
313 BT_XD_1
314 BT_XD_7
315 BT_XD_13
316 BT_TM2
264 BT_GPIO_0
265 BT_XA_17
266 BT_VDDC
267 BT_VDDC
317 BT_XA_2
318 BT_GPIO_6
319 BT_GPIO_3
320 BT_VDDC
321 BT_UART_TXD
322 BT_VSSC_0
323 BT_VSSC_0
324 BT_XWE_N
325 BT_TM6
268 BT_PCM_CLK
269 BT_UART_RXD
270 SDIO_DATA_3
271 SDIO_DATA_2
272 SDIO_DATA_1
273 WRF_AFE_DIGIT_TEST0 5025
274 xtal_pu
5775
6025
3275
3525
3775
4025
4275
4525
5275
5525
5775
6025
3275
3525
3775
4025
4275
4525
4775
5275
5525
3275
3525
3775
4025
4275
4525
4775
5025
6000
275 wl_uart_rx1
276 BT_XOE_N
277 BT_COEX_OUT0
278 BT_XA_7
326 BT_XA_6
327 BT_XA_10
328 BT_PCM_SYNC
329 BT_XA_16
330 BT_VDDC
331 BT_XD_12
332 BT_XA_4
333 BT_GPIO_5
334 BT_XA_11
335 BT_XA_14
336 BT_SCL
279 BT_XA_15
280 BT_XD_3
281 SDIO_CMD
284 SDIO_DATA_0
285 SDIO_CLK
286 sprom_clk
287 sprom_dout
288 BT_TM1
289 BT_XA_3
337 BT_XD_6
338 BT_VDDO
339 BT_GPIO_7
340 BT_GPIO_4
341 BT_PCM_IN
342 BT_UART_CTS_N
343 BT_XD_0
344 BT_XD_5
345 BT_XD_11
346 BT_XD_14
347 BT_XD_15
290 BT_XA_8
291 BT_UART_RTS_N
292 BT_XD_2
293 BT_XD_4
294 BT_XD_9
296 VDDIO_SD
297 VDDIO_SD
298 BT_GPIO_2
299 BT_XA_1
300 BT_COEX_OUT1
301 BT_XA_12
302 BT_PCM_OUT
303 BT_SDA
304 BT_XD_8
305 BT_XD_10
306 VDD
Broadcom Corporation
Page 42
Signal Assignments
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 15: Signal Descriptions
196-BALL FBGA PACKAGE
Table 8: 196-Ball FBGA Signal Descriptions
Type Description
Ball
Signal Name
Number
WLAN RF
A12
A14
F14
D14
G14
E14
L11
L12
A10
A9
WRF_RFOUTP_G
WRF_RFOUTP_A
O
O
I
WLAN 802.11g Internal Power Amplifier output (50Ω)
WLAN 802.11a Internal Power Amplifier output (50Ω)
WLAN 802.11g Internal LNA RX input (50Ω)
WRF_RFINP_G1
WRF_RFINP_A1
I
WLAN 802.11a Internal LNA RX Positive input (100Ω)
WLAN 802.11g RX transformer ground
WRF_RFINN_G1_XFMR
WRF_RFINN_A1_XFMR
WRF_RES_EXT
O
I
WLAN 802.11a Internal LNA RX Negative input (100Ω)
Connect to external 15 kΩ resistor to ground
32.768 kHz LPO clock input. Used for low-power mode timing
WLAN directional coupler input for 802.11g (50Ω)
WLAN directional coupler input for 802.11a (50Ω)
Transmit signal strength indicator for external 802.11g Power Amplifier
Transmit signal strength indicator for external 802.11a Power Amplifier
Disables WLAN radio when low.
I
WRF_EXTREFIN
I
WRF_EXTCOUPLE_GIN
WRF_EXTCOUPLE_AIN
WRF_AFE_TSSI_G
WRF_AFE_TSSI_A
WRF_DISABLE_N
I
I
E9
I
C10
A8
I
I
Integrated LDOs
P1
M1
P3
VREF_LDO
O
O
O
Vref bypass. Connect to external capacitor.
1.25V output for LNLDO1, 130 mA
VOUT_LNLDO1
VOUT_LNLDO2
1.25V output for LNLDO2, 80 mA. It can be programmed to output 2.5V
after reset (LNLDO2 is OFF by default. Software can program it to 1.25V or
2.5V before enabling it).
M3
N1
VIN_LNLDO1
VIN_LNLDO2
I
I
1.5V input for LNLDO1, 130 mA.
Note: If LNLDO1 is not used, this pin must be connected to ground.
3.3V or 1.5V input (which could be the output of CBUCK), 80 mA current.
Note: If LNLDO2 is not used, this pin must be connected to ground.
1.25V output for CLDO, 200 mA
L1
VOUT_CLDO
VIN_CLDO
O
I
M2
1.5V input for CLDO, 200 mA.
Note: If CLDO is not used, this pin must be connected to ground.
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 43
BCM4325
Preliminary Data Sheet
6/30/09
Table 8: 196-Ball FBGA Signal Descriptions (Cont.)
Type Description
Ball
Number
Signal Name
Integrated Switching Regulators
G1
C1
F1
E1
A3
D1
SR_VOUTBB
SR_VNLDO
SR_VLX2BB
SR_VLX1BB
SR_VLX1
O
O
O
O
O
I
Buck Boost Regulator. 3.3V output
NLDO Output. 220 nF external compensating capacitor
Buck Boost Regulator. Inductor –ve terminal
Buck Boost Regulator. Inductor +ve terminal
Core Buck Regulator. Output to inductor
SR_VFBBB
Buck Boost Regulator. Voltage feedback.
Note: If not used, this pin should be connected to ground.
Core Buck Regulator. Output voltage feedback.
Note: This pin should be connected to ground if CBUCK is not used.
Buck Boost Regulator. Battery voltage Input.
A1
E2
SR_VFB1
I
I
SR_VBATBB
Note: This pin must be connected to VBAT (or an external 3.3V supply
even if the BBOOST and CBUCK regulators are not used.
A2
B3
C2
SR_VBAT1B
SR_VBAT1A
SR_TESTSWG
I
I
Clean VBAT supply for LDOs and Bandgap.
Note: This pin must be connected to VBAT (or an external 3.3V supply)
even if the BBOOST and CBUCK regulators are not used.
Core Buck Regulator. Battery voltage input.
Note: This pin must be connected to VBAT (or an external 3.3V supply)
even if the BBOOST and CBUCK regulators are not used.
I/O Connect to 2.5V VDD (which could be SR_AVDD2P5) with or without 0Ω
stuffing option.
F2
C3
D3
B2
B1
N3
SR_PVSSB
SR_PVSS
I
I
Buck Boost Regulator. Power Switch Ground
Core Buck Regulator. Power Switch Ground
Analog Ground
SR_AVSS
I
SR_PLDO
O
O
I
PLDO Output. 220 nF external compensating capacitor
2.5V LDO Output
SR_AVDD2P5
AVDD2P5_LDO
2.5V Supply for Internal LDO. Connect to SR_AVDD2P5
SDIO Bus Interface
K4
L2
H2
J3
SDIO_CMD
I/O SDIO Command Line.
See Table 18 on page 73 and Table 19 on page 74 for additional details.
I/O SDIO Data Line 0.
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SDIO_CLK
See Table 18 on page 73 and Table 19 on page 74 for additional details.
I/O SDIO Data Line 1.
See Table 18 on page 73 and Table 19 on page 74 for additional details.
I/O SDIO Data Line 2.
See Table 18 on page 73 and Table 19 on page 74 for additional details.
I/O SDIO Data Line 3.
P6
K1
See Table 18 on page 73 and Table 19 on page 74 for additional details.
I
SDIO Clock.
This is an input pin driven by the SDIO clock signal. It remains high
impedance when WL_RST_N is low. See Table 18 on page 73 and
Table 19 on page 74 for additional details.
Broadcom Corporation
Page 44
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 8: 196-Ball FBGA Signal Descriptions (Cont.)
Type Description
Ball
Signal Name
Number
WLAN UART
J4
WL_UART_TX0
WL_UART_RX0
I/O Serial output for WLAN UART.
Connect to RS-232 DTE for exchanging data with other serial devices. If not
used, it may be left unconnected.
H3
I/O Serial Input for WLAN UART.
Connect to RS-232 DTE for exchanging data with other serial devices. If not
used, it may be left unconnected.
JTAG Interface (test only)
D4
TMS
I
For normal operation, connect as described in the JTAG specification
(IEEE Std 1149.1). Otherwise, if JTAG is not used, this pin can be left
unconnected (NC) as it has an internal pull-up resistor.
C4
E5
TDO
TDI
O
I
For normal operation, connect as described in the JTAG specification
(IEEE Std 1149.1). Otherwise, if JTAG is not used, this pin can be left NC.
For normal operation, connect as described in the JTAG specification
(IEEE Std 1149.1). Otherwise, if JTAG is not used, this pin can be left NC,
as it has an internal pull-up resistor.
F5
E6
TCK
I
I
For normal operation, connect as described in the JTAG specification
(IEEE Std 1149.1). Otherwise, if JTAG is not used, this pin can be left NC,
as it has an internal pull-up resistor.
TAP_SEL
WLAN JTAG Tap Select.
Drive low to connect the JTAG interface with the main tap controller; drive
high to connect with the ARM tap controller. This pin has an internal pull-
down. For normal operation, the pin can be left as a NC.
B4
JTAG_TRST_N
I
For normal operation, connect as described in the JTAG specification
(IEEE Std 1149.1). Otherwise, if JTAG is not used, this pin can be left NC,
as it has an internal pull-up resistor.
SPROM
H1
SPROM_DOUT
SPROM_DIN
SPROM_CS
I/O SPROM Data Out.
Must be connected to DIN signal of the SPROM.
I/O SPROM Data In.
H8
J6
Must be connected to DOUT signal of the SPROM.
I/O SPROM Chip Select.
Must be connected to the chip select input of the SPROM (typically called
CS). This pin has an internal pull-down.
K3
SPROM_CLK
I/O SPROM Data Clock.
Must be connected to the serial clock input of the SPROM (typically called
SK).
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 45
BCM4325
Preliminary Data Sheet
6/30/09
Table 8: 196-Ball FBGA Signal Descriptions (Cont.)
Type Description
Ball
Number
Signal Name
RF Control Lines
A7
RF_SW_CTRL_N_0
I/O RF Switch Control Line.
Connect to the BT TX port of the front-end switch.
I/O RF Switch Control Line.
B6
RF_SW_CTRL_N_1
Connect to the WLAN TX port of the front-end switch.
I/O Programmable RF switch control line
I/O RF Switch Control Line.
A5
B7
RF_SW_CTRL_N_3
RF_SW_CTRL_P_0
Connect to the RX port (for both WLAN and BT) of the front-end switch.
I/O Programmable RF switch control line
I/O Programmable RF switch control line
I/O 802.11a external PA control
E7
B5
A6
F6
B8
C7
D6
RF_SW_CTRL_P_1
RF_SW_CTRL_P_3
AMODE_TX_PU
AMODE_RX_PU
I/O 802.11a external LNA power supply control
I/O 802.11g external PA control
GMODE_TX_PU
WRF_AFE_DIGIT_TEST1
GMODE_EXT_LNA_GAIN
I/O BT/WLAN external LNA power up control
I/O BT/WLAN external LNA gain control
WLAN GPIO
G5
G3
J2
WL_GPIO_0
I/O WLAN general purpose interface pins.
These pins ae high impedance on power up and reset. Subsequently, they
become an input or output under software control. These pins have a
programmable pull-up/down. See Table 18 on page 73 and Table 19 on
page 74 for additional details.
WL_GPIO_1
WL_GPIO_2
WL_GPIO_6
WL_GPIO_7
G2
J5
FM Receiver
P11
P12
M11
M9
FM_RXP
I
I
FM radio RF antenna port
FM_RXN
FM radio RF antenna port
FM_CVAR
I
Bypass node for FM VCO
FM_AUDIO_OUT2
FM_AUDIO_OUT1
O
O
FM analog audio output channel 2
FM analog audio output channel 1
M7
External Coexistence
H7
ERCX_TX_FREQ
I
Transmit frequency overlap signal from the external radio.
Used to indicate that the external radio is about to transmit on a restricted
channel defined by the coexistence mechanism.
F3
ERCX_STATUS
I
I
Coexistence Status from external radio.
Used to signal external radio priority status and receive/transmit direction.
G4
ERCX_RF_ACTIVE
Indicates external radio is active. This pin is asserted prior to an external
radio transaction and remains active for the duration of the transaction.
Broadcom Corporation
Page 46
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 8: 196-Ball FBGA Signal Descriptions (Cont.)
Type Description
Ball
Signal Name
Number
Bluetooth UART
P4
BT_UART_TXD
O
Bluetooth UART Serial Output. Serial data output for the HCI UART
Interface.
L7
BT_UART_RXD
I
Bluetooth UART Series Input. Serial data input for the HCI UART Interface.
N6
BT_UART_RTS_N
O
Bluetooth UART Request to Send. Active-low request to send signal for the
HCI UART interface.
P5
BT_UART_CTS_N
I
Bluetooth UART Clear to Send. Active-low clear to send signal for the HCI
UART interface.
Bluetooth Test Mode
N8
K9
BT_TM0
BT_TM1
I
I
TM0 and TM1 are used for XTAL_PU polarity.
Valid settings are TM[1:0] = 00 for high assertion and 01 for low assertion.
See XTAL_PU signal description for more details.
Bluetooth test mode pin
L8
J8
BT_TM2
BT_TM6
I
I
TM6 is pulled low for the 52-MHz Xtal or TCXO clock and pulled high for all
other frequencies.
Bluetooth
L4
N5
N9
BT_SDA
I/O Bluetooth BSC data
I/O Bluetooth BSC clock
BT_SCL
BT_RST_N
I
Low asserting reset for Bluetooth core. This pin must be driven high or low
(not left floating).
This pin needs 100 ms delay from BT_REG_ON or WL_REG_ON while the
BCM4325 is powered up. See Section 22: “Power-Up Sequence and
Timing” for more details.
K14
BT_RFIOP
O
RF I/O Tuning Port.
For Class 2 operation, connect directly to ground. Trace lengths from the
ball to ground must be kept short (parasitic inductance < 0.5 nH). If trace
lengths need to be longer due to board constraints, add 1.8 pF capacitor to
GND. For Class 1 operation, connect to external PA input.
J14
E3
BT_RFION
O
I
RF I/O Antenna Port.
For Class 2 operation, connect to antenna or BPF. For Class 1 operation,
connect to T/R switch Receive pin.
BT_REG_ON
Used by PMU (along with WL_REG_ON) to decide whether or not to power
down internal BCM4325 regulators. If BT_REG_ON and WL_REG_ON are
low, the regulators will be disabled. BT_REG_ON needs about 70 μs delay
(approx. two 32 kHz clock cycles) after VBAT and VDDIO is up. See Section
22: “Power-Up Sequence and Timing” for details.
Bluetooth PCM
M5
L5
K5
J7
BT_PCM_SYNC
I/O PCM sync signal, can be master (output) or slave (input)
I/O PCM data output
BT_PCM_OUT
BT_PCM_IN
I/O PCM data input
BT_PCM_CLK
I/O PCM clock, can be master (output) or slave (input)
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 47
BCM4325
Preliminary Data Sheet
6/30/09
Table 8: 196-Ball FBGA Signal Descriptions (Cont.)
Type Description
Ball
Number
Signal Name
Bluetooth GPIO
J9
BT_GPIO_0
I/O Bluetooth general purpose interface pins.
These pins are high-impedance on power up and reset. Subsequently, they
become an input or output through software control. See Table 15 on
page 68 and Table 17 on page 71 for more information.
H9
K10
M6
K6
K7
L6
BT_GPIO_1
BT_GPIO_2
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5
BT_GPIO_6
BT_GPIO_7
K8
Miscellaneous
D2
WL_REG_ON
I
I
This signal is used by PMU (along with BT_REG_ON) to decide whether or
not to power down the internal BCM4325 regulators. If BT_REG_ON and
WL_REG_ON are low, the regulators will be disabled. Also note that if
WL_RST_N is low (regardless of BT_RST_N state), the WLAN core will be
powered off. WL_REG_ON needs about 70 μs delay (approx. two 32 kHz
clock cycles) after VBAT and VDDIO is up. See Section 22: “Power-Up
Sequence and Timing” for more details.
A4
WL_RST_N
Low Asserting Reset for WLAN Core. This pin must be driven high or low
(not left floating). See Section 22: “Power-Up Sequence and Timing” for
more details.
P8
P9
K2
OSCIN
I
XTAL oscillator input
XTAL oscillator output
OSCOUT
XTAL_PU
O
O
The BCM4325 asserts this signal when it wants the host to turn on the
crystal circuit/reference clock (e.g., TCXO).
The XTAL_PU assertion polarity is programmable based on BT_TM0 and
BT_TM1. If BT_TM0 and BT_TM1 connect to ground, XTAL_PU is high
asserting (i.e., the BCM4325 drives XTAL_PU high when it wants the clock
turned on). If TM0 connects to VDDIO and BT_TM1 connects to ground,
XTAL_PU is low asserting.
Bluetooth Supplies
M13
L14
BT_VDDVCO
BT_VDDTF
I
I
1.25V Bluetooth VCO power supply
Bluetooth internal PA power supply.
For Class3 Pout < 0 dBm:
Connect it to 1.25V.
For Class2 0 dBm < Pout<3 dBm: Connect it to 1.5V.
For Class1 Pout > 3 dBm:
Connect it to 2.5V.
K12
P14
G8
BT_VDDRF
BT_VDDPLL
BT_VDDO
I
I
I
1.25V Bluetooth RF power supply
1.25V Bluetooth PLL power supply
Bluetooth digital I/O supply (1.8V to 3.3V)
N2
L13
J11
N4
BT_VDDIFIFP
BT_VDDC
I
I
1.25V Bluetooth IF and IF PLL power supply
1.25V Bluetooth baseband core supply
Broadcom Corporation
Page 48
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 8: 196-Ball FBGA Signal Descriptions (Cont.)
Type Description
Ball
Signal Name
Number
WLAN Supplies
H12
D12
E13
H13
A11
B13
G12
J12
J13
K11
E10
D7
WRF_VDDVCO_1P2
WRF_VDDTX_1P2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1.25V supply for WLAN PLL
1.25V supply for WLAN transmitters
1.25V supply tor WLAN receivers
1.25V supply for WLAN PLL
3.3V for the internal power amplifiers
3.3V for the internal power amplifiers
1.25V supply for WLAN LO generator
1.25V supply for WLAN PLL
1.25V supply for WLAN CAB
1.25V supply for WLAN PLL
1.25V supply for WLAN Baseband PLL
1.25V supply for DAC
WRF_VDDRX_1P2
WRF_VDDPFDCP_1P2
WRF_VDDPAG_3P3
WRF_VDDPAA_3P3
WRF_VDDLO_1P2
WRF_VDDD_1P2
WRF_VDDCAB_1P2
WRF_VDDA_1P2
WRF_BBPLL_VDD_1P2
WRF_AFE_AVDD_TXDAC
WRF_AFE_AVDD_RXADC
WRF_AFE_AVDD_AUX
B9
1.25V supply for ADC
D10
1.25V supply for AUX ADC
Miscellaneous Supplies
J1
VDDIO_SD
I
I
SDIO I/O supply (1.8V to 3.3V)
RF I/O supply (1.8V to 3.3V)
L3
C6
F10
F9
VDDIO_RF
VDDIO_RF
VDDIO
I
I
RF I/O supply (1.8V to 3.3V)
H6
F4
Digital I/O supply (1.8V to 3.3V)
G6
G9
H10
H4
L10
H5
VDDC
I
1.25V digital supply for core
VDD_XTAL
I
I
1.25V XTAL Power Supply
2.5V OTP Power Supply
OTP_VDD25
FM Receiver Supplies
M8
FM_ADVDD
FM_VDDVCO
FM_VDDRF
FM_VDDPLL
FM_VDDIF
I
I
I
I
I
1.25V FM supply
M10
P10
N10
P13
1.25V FM receiver VCO power supply
1.25V FM receiver RF power supply
1.25V FM receiver PLL power supply
1.25V FM receiver IF block power supply
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 49
BCM4325
Preliminary Data Sheet
6/30/09
Table 8: 196-Ball FBGA Signal Descriptions (Cont.)
Type Description
Ball
Number
Signal Name
Ground
E4
VSS
I
Ground
E8
F8
G7
L9
FM_ADVSS
BTFM_VSS
I
I
Ground
Ground
K13
M12
M14
N11
N14
J10
M4
BT_VSSC_0
I
Ground
P2
AVSS1_LDO
AVSS
I
I
Ground
Ground
A13
B11
B12
B14
C11
C12
C13
C14
D13
F12
G13
H14
G10
D5
LV_TESTMODE
TEST_SE
I
I
Connect to Ground
C5
Scan enable input. Connect to Ground
Broadcom Corporation
Page 50
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 8: 196-Ball FBGA Signal Descriptions (Cont.)
Type Description
Ball
Signal Name
Number
No Connect
H11
G11
F13
E11
F11
D9
WRF_GPIO_OUT2
WRF_GPIO_OUT1
WRF_PA_100UA
WRF_AFE_TEST_QP
WRF_AFE_TEST_QN
WRF_AFE_TEST_OPQ
WRF_AFE_TEST_OPI
WRF_AFE_TEST_ONQ
WRF_AFE_TEST_ONI
WRF_AFE_TEST_IP
WRF_AFE_TEST_IN
WRF_AFE_IQADC_VREF
GMODE_RX_PU
O
O
O
I
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
I
O
O
O
O
I
C8
D8
C9
D11
B10
E12
F7
I
O
I/O No connect
I/O No Connect
I/O No Connect
P7
BT_COEX_OUT1
BT_COEX_OUT0
N/C
N7
N12
N13
O
O
No Connect
No Connect
N/C
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 51
BCM4325
Preliminary Data Sheet
6/30/09
339-PIN WLCSP PACKAGE
Table 9: 339-Pin WLCSP Signal Descriptions
Type Description
Pin # Signal Name
WLAN RF
14
16
17
18
15
2
WRF_GNDPAA_3P3
WRF_GNDPAA_3P3
WRF_GNDPAG_3P3
WRF_GNDPAG_3P3
WRF_GNDTX_1P2
I
I
Internal power amplifier ground
Internal power amplifier ground
Internal power amplifier ground
Internal power amplifier ground
Radio transmitter ground
I
I
I
WRF_RFOUTN_A
O
O
O
O
I
A-band PA transformer primary side ground (need short and solid ground).
WLAN 802.11a Internal Power Amplifier output (50Ω)
G-band PA transformer primary side ground (need short and solid ground).
WLAN 802.11g Internal Power Amplifier output (50Ω)
ADC Ground
5
WRF_RFOUTP_A
6
WRF_RFOUTN_G
9
WRF_RFOUTP_G
10
12
23
26
WRF_AFE_PAD_AVSS_RXADC
WRF_AFE_PAD_AVSS_TXDAC
WRF_AFE_TSSI_A
I
DAC Ground
I
Transmit signal strength indicator for external 802.11a Power Amplifier
WRF_RFINN_A2_XFMR
O
Ground of the primary side of the A-band RX transformer #2. Need
short and solid ground
30
31
32
36
37
38
39
40
42
46
WRF_AFE_TSSI_G
WRF_RFINP_A2
I
I
Transmit signal strength indicator for external 802.11g Power Amplifier
WLAN 802.11a Internal LNA #2 RX input (50Ω)
WLAN directional coupler input for 802.11a (50Ω)
WLAN 802.11a Internal LNA RX Positive input (100Ω)
WLAN directional coupler input for 802.11g (50Ω)
WLAN Baseband PLL Ground
WRF_EXTCOUPLE_AIN
WRF_RFINP_A1
I
I
WRF_EXTCOUPLE_GIN
WRF_BBPLL_GND_1P2
WRF_GNDLO_1P2
I
I
I
WLAN LO Generator Ground
WRF_RFINN_A1_XFMR
WRF_GNDRX_1P2
I
WLAN 802.11a Internal LNA RX Negative input (100Ω)
WLAN RX Ground
I
WRF_RFINN_G2_XFMR
O
Ground of the primary side of the G-band RX transformer #2. Need
short and solid ground
48
49
51
52
WRF_RFINP_G2
I
I
WLAN 802.11g Internal LNA #2 RX input (50Ω)
WLAN 802.11g and BT Shared LNA RX input (50Ω)
WLAN PLL Ground
WRF_RFINP_G1
WRF_GNDVCO_1P2
WRF_RFINN_G1_XFMR
I
O
Ground of the primary side of the Shared RX transformer. Need short and
solid ground
53
55
57
60
61
WRF_GNDD_1P2
WRF_GNDPFDCP_1P2
WRF_GNDA_1P2
WRF_GNDCAB_1P2
WRF_EXTREFIN
I
I
I
I
I
WLAN PLL Ground
WLAN PLL Ground
WLAN PLL Ground
WLAN CAB Ground
32.768 kHz LPO clock input. Used for low-power mode timing. This pin
needs be driven high or low (not left floating).
62
WRF_RES_EXT
I
I
I
Connect to external 15 kΩ (1% tolerance) resistor to ground.
Disables WLAN radio when low
180 WRF_DISABLE_N
178 WL_RST_N
Low asserting reset for WLAN core. This pin must be driven high or low (not
left floating). See Section 22: “Power-Up Sequence and Timing”.
Broadcom Corporation
Page 52
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
Integrated LDOs
145 VIN_CLDO
146
I
O
I
1.5V input for CLDO, 200 mA
Note: If CLDO is not used, these pins must be connected to ground.
147 VOUT_CLDO
148
1.25V output for CLDO, 200 mA
149 VIN_LNLDO1
150
1.5V input for LNLDO1, 130 mA
Note: If LNLDO1 is not used, these pins must be connected to ground.
3.3V or 1.5V input (which could be the output of CBUCK), 80 mA current.
Note: If LNLDO2 is not used, this pin must be connected to ground.
1.5V/3.3V Programmable input for LNLDO4
155 VIN_LNLDO2
I
158 VIN_LNLDO4
I
Note: If LNLDO4 is not used, this pin must be connected to ground.
1.25V output for LNLDO1, 130 mA
151 VOUT_LNLDO1
152
O
O
156 VOUT_LNLDO2
1.25V output for LNLDO2, 80 mA. It can be programmed to output 2.5V
after reset (LNLDO2 is off by default. Software can program it to 1.25V or
2.5V before enabling it).
159 VOUT_LNLDO4
160 AVDD2P5_LDO
162 VREF_LDO
O
I
1.25V/2.5V programmable output for LNLDO4, 80 mA
2.5V supply for internal LDO. Connect to SR_AVDD2P5
Vref bypass. Connect to external capacitor.
Ground
O
I
153 AVSS1_LDO
161 AVSS2_LDO
I
Ground for band-gap reference
Integrated Switching Regulators
101 SR_VLX1
108
O
Core buck regulator: Output to inductor
113 SR_VLX1
100 SR_VBAT1A
107
O
I
Core buck regulator: Output to inductor
Core buck regulator: Shared battery voltage input
Note: These pins must be connected to VBAT (or an external 3.3V
supply) even if the BBOOST and CBUCK regulators are not used.
102 SR_PVSS1
103 SR_VFB1
I
I
Core buck regulator: Power switch ground
Core buck regulator: Output voltage feedback
Note: This pin should be connected to ground if CBUCK is not used.
Clean VBAT supply for LDOs and Bandgap
104 SR_VBAT1B
I
Note: This pin must be connected to VBAT (or an external 3.3V supply)
even if the BBOOST and CBUCK regulators are not used.
109 SR_PVSS1
110 SR_VSSPLDO
112 SR_VBAT1A
I
I
I
Core buck regulator: Power switch ground
Tracks battery voltage: Connect to 220 nF external capacitor to battery
Core buck regulator: Shared battery voltage input
Note: This pin must be connected to VBAT (or an external 3.3V supply)
even if the BBOOST and CBUCK regulators are not used.
114 SR_PVSS1
I
Core buck regulator: Power switch ground
115 SR_TESTSWG
I/O Connect to 2.5V VDD (which could be SR_AVDD2P5) with or without 0Ω
stuffing option.
116 SR_AVDD2P5
117 SR_AVSS
O
I
2.5V LDO output
Analog Ground
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 53
BCM4325
Preliminary Data Sheet
6/30/09
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
118 SR_VBAT1A
I
Core buck regulator: Shared battery voltage input
Note: This pin must be connected to VBAT (or an external 3.3V supply)
even if the BBOOST and CBUCK regulators are not used.
119 SR_AVSS
120 SR_VDDNLDO
122 SR_VBATBB
123
I
O
I
Analog Ground
NLDO output: Connect to 220 nF external to capacitor to ground
Buck boost regulator: Battery voltage Input
Note: These pins must be connected to VBAT (or an external 3.3V
supply) even if the BBOOST and CBUCK regulators are not used.
124 SR_VFBBB
I
I
Buck boost regulator: Voltage feedback
Note: This pin should be connected to ground if BBOOST is not used.
Buck boost regulator: Battery voltage input
126 SR_VBATBB
127
Note: These pins must be connected to VBAT (or an external 3.3V
supply) even if the BBOOST and CBUCK regulators are not used.
128
129 SR_VLX1BB
O
I
Buck boost regulator: Inductor +ve terminal
Buck boost regulator: Power switch ground
Buck boost regulator: Inductor –ve terminal
Buck boost regulator: 3.3V output
130
131
132
133 SR_PVSSB
134
135
136
137 SR_VLX2BB
O
O
138
139
140
141 SR_VOUTBB
142
143
144
SDIO Bus Interface
284 SDIO_DATA_0
I/O SDIO Data Line 0. See Table 18 on page 73 and Table 19 on page 74 for
more information.
272 SDIO_DATA_1
271 SDIO_DATA_2
270 SDIO_DATA_3
281 SDIO_CMD
285 SDIO_CLK
I/O SDIO Data Line 1. See Table 18 on page 73 and Table 19 on page 74 for
more information.
I/O SDIO Data Line 2. See Table 18 on page 73 and Table 19 on page 74 for
more information.
I/O SDIO Data Line 3. See Table 18 on page 73 and Table 19 on page 74 for
more information.
I/O SDIO Command Line. See Table 18 on page 73 and Table 19 on page 74
for more information.
I
SDIO Clock. See Table 18 on page 73 and Table 19 on page 74 for more
information.
Broadcom Corporation
Page 54
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
WLAN UART
247 WL_UART_RX0
I
Serial Input for WLAN UART. Connect to RS-232 DTE for exchanging data
with other serial devices. If not used it may be left unconnected.
259 WL_UART_TX0
260 WL_UART_TX1
I/O Serial Output for WLAN UART. Connect to RS-232 DTE for exchanging
data with other serial devices. If not used it may be left unconnected.
I/O Serial Output for second WLAN UART. Connect to RS-232 DTE for
exchanging data with other serial devices. If not used it may be left
unconnected.
275 WL_UART_RX1
I
Serial Input for second WLAN UART. Connect to RS-232 DTE for
exchanging data with other serial devices. If not used it may be left
unconnected.
JTAG Interface (test only)
190 TDI
I
For normal operation, connect as described in the JTAG specification (IEEE
Std 1149.1). Otherwise, if JTAG is not used, these pins can be left
unconnected (NC) as they have internal pull-up resistors.
171 TDO
191 TMS
O
I
For normal operation, connect as described in the JTAG specification (IEEE
Std 1149.1). Otherwise, if JTAG is not used, this pin can be left NC.
For normal operation, connect as described in the JTAG specification (IEEE
Std 1149.1). Otherwise, if JTAG is not used, these pins can be left NC as
they have internal pull-up resistors.
184 TCK
I
I
I
For normal operation, connect as described in the JTAG specification (IEEE
Std 1149.1). Otherwise, if JTAG is not used, these pins can be left NC as
they have internal pull-up resistors.
172 JTAG_TRST_N
177 TAP_SEL
For normal operation, connect as described in the JTAG specification (IEEE
Std 1149.1). Otherwise, if JTAG is not used, these pins can be left NC as
they have internal pull-up resistors.
WLAN JTAG tap select: Drive low to connect the JTAG interface with the
main tap controller; drive high to connect with the ARM tap controller. This
pin has an internal pull-down. For normal operation the pin can be left as
NC.
SPROM
233 SPROM_DIN
246 SPROM_CS
I
SPROM Data In. Must be connected to DOUT signal of the SPROM.
I/O SPROM Chip Select. Must be connected to the chip select input of the
SPROM (typically called CS). This pin has an internal pull-down.
286 SPROM_CLK
I/O SPROM Data Clock. Must be connected to the serial clock input of the
SPROM (typically called SK).
287 SPROM_DOUT
I/O SPROM Data Out. Must be connected to DIN signal of the SPROM.
SFLASH
206 SFLASH_Q
214 SFLASH_D
228 SFLASH_C
229 SFLASH_S
I
Data input from serial flash (active low)
Output data to serial flash
O
O
O
Serial flash clock
Serial flash chip select (active low)
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 55
BCM4325
Preliminary Data Sheet
6/30/09
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
RF Control Lines
168 RF_SW_CTRL_P_0
O
RF Switch Control Line. Connect to the RX port (for both WLAN and BT) of
the front-end switch.
181 RF_SW_CTRL_P_1
170 RF_SW_CTRL_P_2
197 RF_SW_CTRL_P_3
164 RF_SW_CTRL_N_0
174 RF_SW_CTRL_N_1
176 RF_SW_CTRL_N_2
189 RF_SW_CTRL_N_3
169 WRF_AFE_DIGIT_TEST1
182 AMODE_TX_PU
O
O
O
O
O
O
O
Programmable RF switch control line
Programmable RF switch control line
Programmable RF switch control line
RF switch control line. Connect to the BT TX port of the front-end switch.
RF switch control line. Connect to the WLAN TX port of the front-end switch.
Programmable RF switch control line
Programmable RF switch control line
I/O BT/WLAN external LNA power up control
O
O
O
O
O
802.11a external PA control
196 AMODE_RX_PU
802.11a external LNA power supply control
802.11a external LNA gain control
802.11g external PA control
188 AMODE_EXT_LNA_GAIN
187 GMODE_TX_PU
175 GMODE_EXT_LNA_GAIN
BT/WLAN external LNA gain control
WLAN GPIO
213 WL_GPIO_0
240 WL_GPIO_1
239 WL_GPIO_2
238 WL_GPIO_4
237 WL_GPIO_5
251 WL_GPIO_6
225 WL_GPIO_7
250 WL_GPIO_8
236 WL_GPIO_9
249 WL_GPIO_10
262 WL_GPIO_11
248 WL_GPIO_12
224 WL_GPIO_13
235 WL_GPIO_14
261 WL_GPIO_15
I/O WLAN general purpose interface pins.
These pins are high impedance on power up and reset. Subsequently, they
become an input or output under software control. Each pin has a
programmable pull-up/down, see Table 14 on page 67 and Table 18 on
page 73 for more information.
Broadcom Corporation
Page 56
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
FM Receiver
76
75
83
90
91
FM_AUDIO_OUT1
FM_AUDIO_OUT2
FM_CVAR
O
O
I
FM analog audio output channel 1
FM analog audio output channel 2
Bypass node for FM VCO
FM_RXN
I
FM radio RF antenna port
FM_RXP
I
FM radio RF antenna port
External Coexistence
199 ERCX_PRISEL
207 ERCX_STATUS
O
I
External Radio Coexistence. Priority Select.
Coexistence status from external radio. Used to signal external radio
priority status and receive/transmit direction.
215 ERCX_RF_ACTIVE
219 ERCX_TX_FREQ
I
I
Indicates external radio is active. This pin is asserted prior to an external
radio transaction and remains active for the duration of the transaction.
Transmit frequency overlap signal from the external radio. Used to indicate
that the external radio is about to transmit on a restricted channel defined
by the coexistence mechanism.
230 ERCX_TXCONF
O
External Radio Coexistence. Transmit Confirmation.
Bluetooth UART
269 BT_UART_RXD
321 BT_UART_TXD
I
Bluetooth UART Serial Input. Serial data input for the HCI UART Interface.
O
Bluetooth UART Serial Output. Serial data output for the HCI UART
Interface.
342 BT_UART_CTS_N
291 BT_UART_RTS_N
I
Bluetooth UART Clear to Send. Active-low clear to send signal for the HCI
UART interface.
O
Bluetooth UART Request to Send. Active-low request to send signal for the
HCI UART interface.
Bluetooth Test Mode
309 BT_TM0
288 BT_TM1
I
I
M0 and TM1 are used for XTAL_PU polarity. Valid settings are TM[1:0] =
00 for high assertion; and 01 for low assertion.
See XTAL_PU signal description for more details.
Bluetooth test mode pin
316 BT_TM2
325 BT_TM6
I
I
TM6 is pulled low for the 52 MHz Xtal or TCXO clock and pulled high for all
other frequencies.
Bluetooth
63
66
BT_RFION
BT_RFIOP
O
O
RF I/O antenna port. For Class 2 operation, connect to antenna or BPF.
RF I/O tuning port. For Class 2 operation, connect directly to ground. Trace
lengths from the ball to ground must be kept short (parasitic inductance <
0.5 nH). If trace lengths need to be longer due to board constraints, add a
0.9pF capacitor to GND.
97
BT_RST_N
I
Low asserting reset for Bluetooth core. This pin needs be driven high or low
(not left floating).
This pin needs 100 ms delay from BT_REG_ON or WL_REG_ON while
BCM4325 is powered up. See Section 22: “Power-Up Sequence and
Timing” for more details.
336 BT_SCL
303 BT_SDA
308 BT_XCS_N
I/O Bluetooth BSC Clock
I/O Bluetooth BSC Data
O
Active low chip select for external code space in Flash memory
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 57
BCM4325
Preliminary Data Sheet
6/30/09
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
276 BT_XOE_N
324 BT_XWE_N
299 BT_XA_1
317 BT_XA_2
289 BT_XA_3
332 BT_XA_4
310 BT_XA_5
326 BT_XA_6
278 BT_XA_7
290 BT_XA_8
311 BT_XA_9
327 BT_XA_10
334 BT_XA_11
301 BT_XA_12
312 BT_XA_13
335 BT_XA_14
279 BT_XA_15
329 BT_XA_16
265 BT_XA_17
263 BT_XA_18
343 BT_XD_0
313 BT_XD_1
292 BT_XD_2
280 BT_XD_3
293 BT_XD_4
344 BT_XD_5
337 BT_XD_6
314 BT_XD_7
304 BT_XD_8
294 BT_XD_9
305 BT_XD_10
345 BT_XD_11
331 BT_XD_12
315 BT_XD_13
346 BT_XD_14
347 BT_XD_15
322 BT_VSSC_0
323
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Active low output enable output for dataspace
Active low write enable output for dataspace
Address bit 1 for Bluetooth Flash ROM/External SRAM
Address bit 2 for Bluetooth Flash ROM/External SRAM
Address bit 3 for Bluetooth Flash ROM/External SRAM
Address bit 4 for Bluetooth Flash ROM/External SRAM
Address bit 5 for Bluetooth Flash ROM/External SRAM
Address bit 6 for Bluetooth Flash ROM/External SRAM
Address bit 7 for Bluetooth Flash ROM/External SRAM
Address bit 8 for Bluetooth Flash ROM/External SRAM
Address bit 9 for Bluetooth Flash ROM/External SRAM
Address bit 10 for Bluetooth Flash ROM/External SRAM
Address bit 11 for Bluetooth Flash ROM/External SRAM
Address bit 12 for Bluetooth Flash ROM/External SRAM
Address bit 13 for Bluetooth Flash ROM/External SRAM
Address bit 14 for Bluetooth Flash ROM/External SRAM
Address bit 15 for Bluetooth Flash ROM/External SRAM
Address bit 16 for Bluetooth Flash ROM/External SRAM
Address bit 17 for Bluetooth Flash ROM/External SRAM
Address bit 18 for Bluetooth Flash ROM/External SRAM
I/O Bidirectional data bus bit 0 for Flash ROM
I/O Bidirectional data bus bit 1 for Flash ROM
I/O Bidirectional data bus bit 2 for Flash ROM
I/O Bidirectional data bus bit 3 for Flash ROM
I/O Bidirectional data bus bit 4 for Flash ROM
I/O Bidirectional data bus bit 5 for Flash ROM
I/O Bidirectional data bus bit 6 for Flash ROM
I/O Bidirectional data bus bit 7 for Flash ROM
I/O Bidirectional data bus bit 8 for Flash ROM
I/O Bidirectional data bus bit 9 for Flash ROM
I/O Bidirectional data bus bit 10 for Flash ROM
I/O Bidirectional data bus bit 11 for Flash ROM
I/O Bidirectional data bus bit 12 for Flash ROM
I/O Bidirectional data bus bit 13 for Flash ROM
I/O Bidirectional data bus bit 14 for Flash ROM
I/O Bidirectional data bus bit 15 for Flash ROM
I
Ground
Broadcom Corporation
Page 58
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
Bluetooth PCM
268 BT_PCM_CLK
302 BT_PCM_OUT
341 BT_PCM_IN
I/O PCM clock, can be master (output) or slave (input).
I/O PCM data output
I/O PCM data input
328 BT_PCM_SYNC
I/O PCM sync signal, can be master (output) or slave (input).
Bluetooth GPIO
264 BT_GPIO_0
252 BT_GPIO_1
298 BT_GPIO_2
319 BT_GPIO_3
340 BT_GPIO_4
333 BT_GPIO_5
318 BT_GPIO_6
339 BT_GPIO_7
I/O Bluetooth general purpose interface pin.
These pins are high-impedance on power up and reset. Subsequently, they
become an input or output through software control. See Table 15 on
page 68 and Table 17 on page 71 for more information.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Miscellaneous
95
96
OSCIN
I
XTAL oscillator input
XTAL oscillator output
OSCOUT
O
O
274 XTAL_PU
The BCM4325 asserts this signal when it wants the host to turn on the
crystal circuit/ reference clock like TCXO. Note that the XTAL_PU assertion
polarity is programmable based on BT_TM0 and BT_TM1. If BT_TM0 and
BT_TM1 connect to ground, XTAL_PU is high asserting (i.e., the BCM4325
drives XTAL_PU high when it wants the clock turned on). If TM0 connects
to VDDIO and BT_TM1 connects to ground, XTAL_PU is low asserting.
121 WL_REG_ON
I
I
Used by PMU (along with BT_REG_ON) to decide whether or not to power
down internal BCM4325 regulators. If both BT_REG_ON and
WL_REG_ON are low, the regulators will be disabled. Also note that if
WL_RST_N is low (regardless of BT_RST_N state) the WLAN core will be
powered off. WL_REG_ON needs about 70 μs delay (approx. two 32-kHz
clock cycles) after VBAT and VDDIO is up. See Section 22: “Power-Up
Sequence and Timing”.
123 BT_REG_ON
Used by PMU (along with WL_REG_ON) to decide whether or not to power
down internal BCM4325 regulators. If BT_REG_ON and WL_REG_ON are
low, the regulators will be disabled. BT_REG_ON needs about 70 μs delay
(approx. two 32-kHz clock cycles) after VBAT and VDDIO is up. See
Section 22: “Power-Up Sequence and Timing” for more details.
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 59
BCM4325
Preliminary Data Sheet
6/30/09
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
Bluetooth Supplies
64
68
BT_VDDRF
BT_VDDTF
I
I
1.25V Bluetooth RF power supply
Bluetooth Internal PA power supply.
For Class3 Pout < 0 dBm:
Connect to 1.25V
For Class2 0 dBm < Pout < 3 dBm: Connect to 1.5V
For Class1 Pout > 3 dBm: Connect to 2.5V
70
73
77
BT_VDDIF
I
I
I
I
I
1.25V Bluetooth IF block power supply
1.25V Bluetooth VCO power supply
BT_VDDVCO
BT_VDDPLL
1.25V Bluetooth PLL power supply
231 BT_VDDO
242 BT_VDDO
243
Bluetooth Digital I/O supply (from 1.8V to 3.3V)
Bluetooth Digital I/O supply (1.8V to 3.3V)
266 BT_VDDC
267
I
1.25V Bluetooth baseband core supply
320
338 BT_VDDO
330 BT_VDDC
I
I
Bluetooth Digital I/O supply (1.8V to 3.3V)
1.25V Bluetooth baseband core supply
WLAN Supplies
3
WRF_VDDPAA_3P3
I
I
3.3V for the internal power amplifiers
3.3V for the internal power amplifiers
4
7
WRF_VDDPAG_3P3
8
11
13
27
29
33
41
43
50
54
56
58
59
WRF_AFE_AVDD_RXADC
WRF_AFE_AVDD_TXDAC
WRF_VDDTX_1P2
I
I
I
I
I
I
I
I
I
I
I
I
1.25V supply for ADC
1.25V supply for DAC
1.25V supply for WLAN transmitters
1.25V supply for AUX ADC
WRF_AFE_AVDD_AUX
WRF_BBPLL_VDD_1P2
WRF_VDDRX_1P2
1.25V supply for WLAN baseband PLL
1.25V supply tor WLAN receivers
1.25V supply for WLAN LO generator
1.25V supply for WLAN PLL
1.25V supply for WLAN PLL
1.25V supply for WLAN PLL
1.25V supply for WLAN PLL
1.25V supply for WLAN CAB
WRF_VDDLO_1P2
WRF_VDDVCO_1P2
WRF_VDDD_1P2
WRF_VDDPFDCP_1P2
WRF_VDDA_1P2
WRF_VDDCAB_1P2
FM Receiver Supplies
72
89
92
93
94
FM_ADVDD
FM_VDDIF
I
I
I
I
I
1.25V FM supply
1.25V FM receiver IF block power supply
FM receiver power supply
FM_VDDRX
FM_VDDVCO
FM_VDDPLL
1.25V FM receiver VCO power supply
1.25V FM receiver PLL power supply
Broadcom Corporation
Page 60
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
Miscellaneous Supplies
86
VDD_XTAL
I
I
1.25V XTAL power supply
1.25V digital supply
200 VDD
201
202
203
217
220
221
232
211
244
306
210 VDDIO
I
Digital I/O supply (1.8V to 3.3V)
216
223
226
227
257 VDDIO_SD
I
I
SDIO I/O supply (1.8V to 3.3V)
RF I/O supply (1.8V to 3.3V)
296
297
185 VDDIO_RF
165
193
194
205
198
234 OTP_VDD25
167 PACKAGEOPTION_1
I
I
2.5V OTP power supply
Connect to VDDIO_RF (1.8V to 3.3V)
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 61
BCM4325
Preliminary Data Sheet
6/30/09
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
Ground
65
67
69
71
74
78
79
82
84
85
88
98
BT_VSSRF
BT_VSSPA
BT_VSSIF
I
I
I
I
I
I
I
I
I
I
I
Bluetooth RF ground
Bluetooth internal PA ground
Bluetooth IF block ground
Ground
FM_ADVSS
FM_VSSVCO
BT_VSSVCO
BT_VSSPLL
FM_VSSRX
FM_VSSPLL
VSS_XTAL
FM_VSSIF
SR_VFB2
FM receiver VCO ground
Bluetooth VCO ground
Bluetooth PLL ground
FM receiver ground
FM receiver PLL ground
XTAL ground
FM IF block ground
Connect to ground
Connect to ground
Ground
I
282 Ground
I
I
204 VSS
245
192
179 PACKAGEOPTION_3
I
I
I
Connect to ground
Connect to ground
Ground
173 PACKAGEOPTION_2
208 VSS
209
212
218
222
253 BT_VSSC_0
254
I
Ground
255
256 VSS
I
I
I
I
I
Ground
241 BT_VSSC_0
163 PACKAGEOPTION_0
183 LV_TESTMODE
166 TEST_SE
Ground
Connect to ground
Connect to ground
Scan Enable Input. Connect to ground.
Broadcom Corporation
Page 62
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 9: 339-Pin WLCSP Signal Descriptions (Cont.)
Type Description
Pin # Signal Name
No Connect
19
20
21
22
24
25
28
34
35
44
45
47
80
81
87
99
WRF_AFE_TEST_IN
WRF_AFE_TEST_OPI
WRF_AFE_TEST_ONQ
WRF_AFE_TEST_IP
WRF_AFE_TEST_ONI
WRF_AFE_TEST_OPQ
WRF_AFE_IQADC_VREF
WRF_AFE_TEST_QP
WRF_AFE_TEST_QN
WRF_GPIO_OUT1
I
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
O
O
I
O
O
O
I
I
O
O
O
O
WRF_GPIO_OUT2
WRF_PA_100UA
NO CONNECT (NC)
DUMMY_BUMP
SR_VLX2
N/A No Connect
O
O
O
No Connect
No Connect
No connect
106 SR_VLX2
186 GMODE_RX_PU
273 WRF_AFE_DIGIT_TEST0
195 WRF_AFE_DIGIT_TEST2
300 BT_COEX_OUT1
277 BT_COEX_OUT0
I/O No Connect
I/O No Connect
I/O No Connect
I/O No Connect
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 63
BCM4325
Preliminary Data Sheet
6/30/09
PIN VOLTAGE DOMAINS
Table 10: BT_VDDO Domain (1.8V to 3.3V)
FBGA Pin#
Signal
WLCSP Pin #
Type
BT_REG_ON
BT_GPIO_1
BT_PCM_CLK
BT_TM6
E3
H9
J7
J8
J9
K10
K5
K6
K7
K8
K9
L4
L5
L6
N8
L8
M5
M6
N5
N6
N7
L7
N9
P4
P5
P7
–
121
252
268
325
264
298
341
340
333
339
288
303
302
318
309
316
328
319
336
291
277
269
97
I
I/O
I/O
I
BT_GPIO_0
BT_GPIO_2
BT_PCM_IN
BT_GPIO_4
BT_GPIO_5
BT_GPIO_7
BT_TM1
I/O
I/O
I/O
I/O
I/O
I/O
I
BT_SDA
I/O
I/O
I/O
I
BT_PCM_OUT
BT_GPIO_6
BT_TM0
BT_TM2
I
BT_PCM_SYNC
BT_GPIO_3
BT_SCL
I/O
I/O
I/O
I/O
I/O
I/O
I
BT_UART_RTS_N
BT_COEX_OUT0
BT_UART_RXD
BT_RST_N
BT_UART_TXD
BT_UART_CTS_N
BT_COEX_OUT1
BT_XCS_N
321
342
300
308
276
324
Note
Note
I/O
I/O
I/O
O
BT_XOE_N
–
O
BT_XWE_N
BT_XA[18:1]
BT_XD[15:0]
–
O
–
O
–
I/O
Note: For FBGA pin numbers see Table 8: “196-Ball FBGA Signal Descriptions,” on page 43.
Note: For WLCSP pin numbers, see Table 9: “339-Pin WLCSP Signal Descriptions,” on page 52.
Broadcom Corporation
Page 64
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 11: VDDIO Domain (1.8V to 3.3V)
FBGA Pin#
Signal
WLCSP Pin#
Type
WL_RST_N
A4
D2
F3
G2
G3
G4
G5
H1
H3
H7
H8
J2
J4
J5
J6
K3
K12
K2
–
178
125
207
251
240
215
213
287
247
219
233
239
259
225
246
286
61
I
WL_REG_ON
ERCX_STATUS
WL_GPIO_6
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
WL_GPIO_1
ERCX_RF_ACTIVE
WL_GPIO_0
SPROM_DOUT
WL_UART_RX0
ERCX_TX_FREQ
SPROM_DIN
WL_GPIO_2
WL_UART_TX0
WL_GPIO_7
SPROM_CS
SPROM_CLK
WRF_EXTREFIN
XTAL_PU
274
260
275
206
214
228
229
238
237
250
236
249
262
248
224
235
261
199
230
O
WL_UART_TX1
WL_UART_RX1
SFLASH_Q
I/O
I
–
–
I
SFLASH_D
–
O
SFLASH_C
–
O
SFLASH_S
–
O
WL_GPIO_4
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
WL_GPIO_5
–
WL_GPIO_8
–
WL_GPIO_9
–
WL_GPIO_10
WL_GPIO_11
WL_GPIO_12
WL_GPIO_13
WL_GPIO_14
WL_GPIO_15
ERCX_PRISEL
ERCX_TXCONF
–
–
–
–
–
–
–
–
O
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 65
BCM4325
Preliminary Data Sheet
6/30/09
Table 12: VDDIO_RF Domain (1.8V to 3.3V)
FBGA Pin#
Signal
WLCSP Pin#
Type
RF_SW_CTRL_N_3
AMODE_TX_PU
RF_SW_CTRL_N_0
WRF_DISABLE_N
JTAG_TRST_N
RF_SW_CTRL_P_3
RF_SW_CTRL_N_1
RF_SW_CTRL_P_0
GMODE_TX_PU
TDO
A5
A6
A7
A8
B4
B5
B6
B7
B8
C4
C5
C7
D4
D5
D6
E5
E6
E7
F5
F6
F7
–
189
182
164
180
172
197
174
168
187
171
166
169
191
183
175
190
177
181
184
196
186
170
176
188
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
TEST_SE
WRF_AFE_DIGIT_TEST1
TMS
I/O
I
LV_TESTMODE
GMODE_EXT_LNA_GAIN
TDI
I
I/O
I
TAP_SEL
I
RF_SW_CTRL_P_1
TCK
I/O
I
AMODE_RX_PU
GMODE_RX_PU
RF_SW_CTRL_P_2
RF_SW_CTRL_N_2
AMODE_EXT_LNA_GAIN
I/O
I/O
O
–
O
–
O
Table 13: VDDIO_SD Domain (1.8V to 3.3V)
FBGA Pin#
Signal
WLCSP Pin#
Type
SDIO_CMD
K4
L2
H2
J3
P6
K1
–
281
284
272
271
270
285
273
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SDIO_CLK
WRF_AFE_DIGIT_TEST0
Broadcom Corporation
Page 66
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
WLAN GPIO SIGNALS AND STRAPPING OPTIONS
The pins listed in Table 14 are sampled at Power-On Reset (POR) to determine the various operating modes. Sampling
occurs within a few milliseconds following an internal POR or deassertion of the external POR. After POR, each pin assumes
the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up
(PU) or pull-down (PD) resistor that determines the default mode.
To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 14: WLAN GPIO Functions and Strapping Options
Pin Name
FBGA WLCSP Default Function
Description
Pin #
Pin #
WL_GPIO_0
WL_GPIO_1
WL_GPIO_2
WL_GPIO_4
WL_GPIO_5
WL_GPIO_6
WL_GPIO_7
G5
G3
J2
–
213
240
239
238
237
251
225
–
GPIO
GPIO
GPIO
GPIO
GPIO
WL_GPIO[2:0] can be used to set out-of-band signals like
WL_WAKE_N, WL_HOST_WAKE_N, and WL_STANDBY.
–
–
–
–
–
G2
J5
High
Low
GPIO[7:6]a [7:6] = 00: OTP powered ON, OTP source of Chip ID, CIS
source: Default
–
[7:6] = 01: OTP powered ON, OTP source of Chip ID, CIS
source: SROM
[7:6] = 10: OTP powered ON, OTP source of Chip ID, CIS
source: OTP
[7:6] = 11: OTP powered OFF, default chip ID, CIS source:
SROM
[7:6] = ZZ: Same as 01: OTP powered, OTP source of Chip ID,
CIS source SROM
WL_GPIO_8
–
250
High
Sets SDIO 0: SDIO in reset, ARM held in reset.
and ARM
core status
Z: Same as 1: SDIO active and ARM in reset
1: SDIO active and ARM in reset
WL_GPIO_9
WL_GPIO_10
–
–
236
249
Low
Low
Boot up
status
[10:9] = 00: Default is set to boot from SRAM and ARM held in
reset.
[10:9] = 01: ARM running (out of reset), boot from ROM.
[10:9] = 10: ARM running (out of reset), boot from flash.
[10:9] = 11: invalid.
–
WL_GPIO_11
–
262
Low
Internal
debug
option
0: Pin must be kept at 0 or Z
WL_GPIO_12
WL_GPIO_13
–
–
248
224
Low
Low
GPIO
–
Sets clock 0: External clock
that can be
used for low
power clock
Z: Same as 0
1: Internal 32 kHz LPO clock (this is only available in the WLCSP
package)
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 67
BCM4325
Preliminary Data Sheet
6/30/09
Table 14: WLAN GPIO Functions and Strapping Options (Cont.)
Pin Name
FBGA WLCSP Default Function
Description
Pin #
Pin #
WL_GPIO_14
–
235
Low
Internal
power up
mode
[15:14] = 00: Chip powers up in the lowest power mode with all
clock sources shut down except for the internal 32 kHz LPO
clock that runs the PMU controller.
[15:14] = 01: Chip powers up to ILP request.
WL_GPIO_15
–
261
High
–
[15:14] = 10: Chip powers up with the crystal oscillator turned on
(default).
[15:14] = 11: Chip powers up with PLL turned on by default.
[15:14] = ZZ: Same as 10
a. These pins select the use of SPROM, OTP or the default CIS in the SDIO core.
b. WL_GPIO_3 does not exist.
BLUETOOTH GPIO SIGNALS
Table 15: BT GPIO Signals
Pin Name
FBGA Pin#
WLCSP Pin # Type
Description
BT_GPIO_0
BT_GPIO_1
BT_GPIO_2
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5
BT_GPIO_6
BT_GPIO_7
BT_PCM_IN
BT_PCM_OUT
BT_PCM_SYNC
BT_PCM_CLK
BT_SCL
J9
264
252
298
319
340
333
318
339
314
302
328
268
336
303
277
300
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Commonly set as BT_WAKEUP
H9
K10
M6
K6
K7
L6
Commonly set as HOST_WAKEUP
GPIO
GPIO
GPIO
GPIO
GPIO
K8
K5
L5
GPIO
PCM data input
O
PCM data output
M5
J7
I/O
I/O
I
PCM sync signal, can be master (output) or slave (input)
PCM clock, can be master (output) or slave (input)
BSC clock
N5
L4
BT_SDA
I/O
O
BSC bidirectional data
BT_COEX_OUT0
BT_COEX_OUT1
N7
P7
BT_ACTIVITY
O
BT_PRIORITY_AND_STATUS
Broadcom Corporation
Page 68
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
PIN DEFAULT PULL-UP/PULL-DOWN
Table 16: Pin Default Pull-Up/Pull-Down
196-Ball FBGA Ball # 339-Pin WLCSP Pin # Default Pin State
Signal Name
For No Connect
RF_SW_CTRL_N_3
AMODE_TX_PU
RF_SW_CTRL_N_0
WRF_DISABLE_N
JTAG_TRST_N
RF_SW_CTRL_P_3
RF_SW_CTRL_N_1
RF_SW_CTRL_P_0
GMODE_TX_PU
SR_TESTSWG
TDO
A5
A6
A7
A8
B4
B5
B6
B7
B8
C2
C4
C7
D4
D6
E5
E6
E7
F3
F5
F6
F7
G2
G4
H1
H3
H7
H8
J4
J5
J6
K1
K3
–
189
182
164
180
172
197
174
168
187
115
171
169
191
175
190
177
181
207
184
196
186
251
215
287
247
219
233
259
225
246
285
286
260
275
206
228
229
230
199
No Pull Control
No Pull Control
No Pull Control
High
–
–
–
IPU
IPU
–
High
No Pull Control
No Pull Control
No Pull Control
No Pull Control
High
–
–
–
IPU
–
No Pull Control
No Pull Control
High
WRF_AFE_DIGIT_TEST1
TMS
–
IPU
–
GMODE_EXT_LNA_GAIN
TDI
No Pull Control
High
IPU
IPD
–
TAP_SEL
Low
RF_SW_CTRL_P_1
ERCX_STATUS
TCK
No Pull Control
No Pull Control
High
–
IPU
–
AMODE_RX_PU
GMODE_RX_PU
WL_GPIO_6
No Pull Control
No Pull Control
High
–
–
ERCX_RF_ACTIVE
SPROM_DOUT
WL_UART_RX0
ERCX_TX_FREQ
SPROM_DIN
Low
IPD
–
No Pull Control
High
IPU
–
No Pull Control
No Pull Control
No Pull Control
Low
–
WL_UART_TX0
WL_GPIO_7
–
–
SPROM_CS
Low
IPD
–
SDIO_CLK
No Pull Control
No Pull Control
No Pull Control
High
SPROM_CLK
–
WL_UART_TX1
WL_UART_RX1
SFLASH_Q
–
–
IPU
–
–
No Pull Control
No Pull Control
High
SFLASH_C
–
–
SFLASH_S
–
IPU
–
ERCX_TXCONF
ERCX_PRISEL
–
No Pull Control
No Pull Control
–
–
Broadcom Corporation
Document 4325-DS04-R
Signal Descriptions
Page 69
BCM4325
Preliminary Data Sheet
6/30/09
Table 16: Pin Default Pull-Up/Pull-Down (Cont.)
196-Ball FBGA Ball # 339-Pin WLCSP Pin # Default Pin State
Signal Name
For No Connect
RF_SW_CTRL_P_2
RF_SW_CTRL_N_2
AMODE_EXT_LNA_GAIN
PACKAGEOPTION_0
PACKAGEOPTION_1
PACKAGEOPTION_2
PACKAGEOPTION_3
–
–
–
–
–
–
–
170
176
188
163
167
173
179
No Pull Control
No Pull Control
No Pull Control
No Pull Control
No Pull Control
No Pull Control
No Pull Control
–
–
–
–
–
–
–
Note: No Connect: Internal Pull Up/Down (IPU/IPD)
Broadcom Corporation
Page 70
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
INTERFACE I/O STATUS
Table 17: BT/FM Interface I/O Status
HW Default
(REG_ON High,
WL and
Internal Pull-Up
Resistor Range Down Resistor
(ohm) Range (ohm)
Internal Pull-
REG_ON Held
LOW (WL and
BT RST_N held
LOW) a
Low Power
Status / Sleep (all
supplies present)
Signal Name
I/O
On status
Power rail
Comment
BT_RST_N high;
no SW loaded) a
3.3V
1.8V
3.3V
1.8V
BT_GPIO_0, 1, 2, I/O
3, 4, 6, 7
Programmable Programmable(In, No internal pull, No internal pull,
BT_VDDO 58K to 58K to 58K to 58K to Internal pull-up/down are
(In, Out, PD, Out, PD, PU)
PU)
disabled input disabled input
63K
63K
63K
63K
programmable and can be
enabled/disabled by S/W.
BT_GPIO_5
I/O
Programmable Programmable(In, No internal pull, Output
BT_VDDO 58K to 58K to 58K to 58K to Internal pull-up/down are
(In, Out, PD, Out, PD, PU)
disabled input
63K
63K
63K
63K
programmable and can be
PU)
enabled/disabled by S/W.
BT_UART_CTS
BT_UART_RTS
I
No internal pull No internal pull,
No internal pull, No internal pull,
BT_VDDO
–
–
–
–
–
needs to be High Z disabled input disabled input
O
No internal pull No internal pull,
No internal pull, No internal pull,
BT_VDDO 58K to 58K to 58K to 58K to Pull-up required which can be
needs to be High Z disabled input disabled input
63K
63K
63K
63K
internal or external. This can
be programmed
BT_UART_RXD
BT_UART_TXD
I
No internal pull No internal pull,
No internal pull, No internal pull,
needs to be driven disabled input disabled input
low
BT_VDDO
–
–
–
–
–
O
No internal pull No internal pull,
No internal pull, No internal pull,
BT_VDDO 58K to 58K to 58K to 58K to Pull-up required which can be
needs to be High Z disabled input disabled input
63K
63K
63K
63K
internal or external. This can
be programmed
BT HOST_WAKE O
(BT_GPIO_0)
No internal pull No internal pull
No internal pull, No internal pull,
disabled input disabled input
BT_VDDO 58K to 58K to 58K to 58K to Pull-up required which can be
63K
63K
63K
63K
internal or external. This can
be programmed. Note: the
level on HOST WAKE should
be ignored by the host during
power-up.
BT WAKE
(BT_GPIO_1)
I
I
I
No internal pull No internal pull
No internal pull No internal pull
No internal pull No internal pull
No internal pull, No internal pull,
disabled input disabled input
BT_VDDO n/a
BT_VDDO n/a
BT_VDDO n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
–
–
–
BT_PCM_CLK
BT_PCM_IN
No internal pull, No internal pull,
disabled input disabled input
No internal pull, No internal pull,
disabled input disabled input
Broadcom Corporation
Document 4325-DS04-R
SignalDescriptions
Page 71
BCM4325
Preliminary Data Sheet
6/30/09
Table 17: BT/FM Interface I/O Status (Cont.)
HW Default
(REG_ON High,
WL and
Internal Pull-Up
Internal Pull-
REG_ON Held
LOW (WL and
BT RST_N held
LOW) a
Resistor Range Down Resistor
Low Power
Status / Sleep (all
supplies present)
(ohm)
1.8V
Range (ohm)
Signal Name
I/O
On status
Power rail
Comment
BT_RST_N high;
no SW loaded) a
3.3V
3.3V
1.8V
BT_PCM_OUT
BT_PCM_SYNC
BT_SCL
O
No internal pull No internal pull
No internal pull No internal pull
No internal pull No internal pull
No internal pull No internal pull
Programmable
No internal pull, No internal pull,
disabled input disabled input
BT_VDDO n/a
BT_VDDO n/a
BT_VDDO n/a
BT_VDDO n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
–
–
–
–
–
I
No internal pull, No internal pull,
disabled input disabled input
n/a
n/a
n/a
I/O
I/O
O
No internal pull, No internal pull,
disabled input disabled input
BT_SDA
No internal pull, No internal pull,
disabled input disabled input
XTAL_PU
High-Z
Output
VDDIO
58K to 58K to 58K to 58K to
63K 63K 63K 63K
Default: BCM4325 drives to the
asserted state when it needs the
clock. Otherwise, the pin is pulled
to the deasserted state. Polarity is
set by the BT_TM0 pin
Polarity set by the
BT_TM0 pin.
a. REG_ON Held LOW = Both WL_REG_ON and BT_REG_ON held low. REG_ON is WL_REG_ON OR'd internal to the 4325 with BT_REG_ON.
Broadcom Corporation
Page 72
Signal Descriptions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 18: WLAN Interface I/O Status
HW Default
(REG_ON High,
WL and
BT_RST_N high;
no SW loaded) b
Internal Pull-Up
Resistor Range Down Resistor
(ohm) Range (ohm)
Internal Pull-
REG_ON Held
LOW (WL and
BT RST_N held
LOW) b
Low Power
Status / Sleep
(all supplies
present)
Signal Name
I/O
On Status
Power rail
Comment
3.3V
1.8V
3.3V
1.8V
WRF_EXTREFIN I
No internal pull. No internal pull. High-Z
Must be driven. Must be driven.
No internal pull.
Needs to be driven.
VDDIO
VDDIO/
n/a
n/a
n/a
n/a
–
–
WL_REG_ON
WL_RST_N
BT_RST_N
BT_REG_ON
WL_GPIO
I
No internal pull. No internal pull. No internal pull, No internal pull.
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
must be driven Needs to be driven. BT_VDDO
Low
Must be driven. Must be driven.
I
No internal pull. No internal pull. No internal pull, No internal pull.
VDDIO
n/a
n/a
n/a
n/a
n/a
n/a
–
–
–
must be driven Needs to be driven.
Low
Must be driven. Must be driven.
I
No internal pull. No internal pull. No internal pull, No internal pull.
BT_VDDO n/a
must be driven Needs to be driven.
Low
Must be driven. Must be driven.
I
No internal pull. No internal pull. No internal pull, No internal pull.
VDDIO/
n/a
must be driven Needs to be driven. BT_VDDO
Low
Must be driven. Must be driven.
I/O
Programmable Programmable High-Z, No pull High-Z
VDDIO
58K to 58K to 58K to 58K to
Internal pull-up/down are
programmable and can be
enabled/disabled by S/W.
(In, Out, PD, PU) (In, Out, PD, PU)
63K
63K
63K
63K
No pull
SDIO Data [3:0] a I/O
Pull-up
Pull-up
Pull-up
Pull-up
High-Z, No pull Pull-up
High-Z, No pull Pull-up
VDDIO_SD 15K to 30K to n/a
35K 82K
n/a
PD not available, PU by
default, can be disabled by
SW.
SDIO CMD a
SDIO_CLK
I/O
I
VDDIO_SD 15K to 30K to n/a
n/a
n/a
PD not available, PU by
default, can be disabled by
SW.
35K
82K
No internal pull. No internal pull. High-Z
Must be driven. Must be driven.
High-Z
VDDIO_SD n/a
n/a
n/a
–
a. Section 6 of the SDIO physical layer specification states that the SDIO host must provide a 10k to 100k ohm pull-up resistor on each CMD and DAT(3:0) signal line. To properly operate the
BCM4325, this requirement must be met by either programming internal PU resistors on the host or device side or adding discrete resistors.
b. REG_ON Held LOW = Both WL_REG_ON and BT_REG_ON held low. REG_ON is WL_REG_ON OR’d with BT_REG_ON in the BCM4325.
Broadcom Corporation
Document 4325-DS04-R
SignalDescriptions
Page 73
BCM4325
Preliminary Data Sheet
6/30/09
SDIO PIN DESCRIPTION
Table 19: SDIO Pin Description
SD 1-Bit Mode
SD 4-Bit Mode
SPI Mode
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SDIO_CLK
Data line 0
DATA
IRQ
Data line
Interrupt
DO
IRQ
NC
Data output
Interrupt
Data line 1 or Interrupt
Data line 2 or Read Wait
Data line 3
RW
Read Wait
Not used
Clock
Not used
Card select
Clock
N/C
CS
Clock
CLK
CMD
SCLK
DI
SDIO_CMD
Command line
Command line
Data input
CLK
CMD
SD Host
BCM4325
DAT [3:0]
Figure 13: Signal Connections to SDIO Card (SD 4-Bit Mode)
CLK
CMD
SD Host
DATA
IRQ
BCM4325
RW
Figure 14: Signal Connections to SDIO Card (SD 1-Bit Mode)
SCLK
DI
SD Host
DO
IRQ
CS
BCM4325
Figure 15: Signal Connections to SDIO Card (SPI Mode)
Broadcom Corporation
Page 74
SDIO Pin Description
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 16: Operating Conditions and DC
Characteristics
ABSOLUTE MAXIMUM RATINGS
Caution! These specifications indicate levels where permanent damage to the device can occur. Functional
operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended
periods can adversely affect long-term reliability of the device.
Table 20: Absolute Maximum Ratings
Rating
Symbol
Value
Unit
DC supply voltage for VBATT
DC supply voltage for I/O
VBATT
–0.5 to 6.5
–0.5 to 4.1
–0.5 to 4.1
V
V
V
VDDIO
DC supply voltage for WLAN PAs
VDDPAG
VDDPAA
VDDTF
DC supply voltage for BT PA
DC supply voltage for RF
–0.5 to 2.9
–0.5 to 1.32
–0.5 to 1.32
–0.5
V
All 1.25V analog
VDDC
V
DC supply voltage for core
V
Maximum undershoot voltage for I/O
Maximum junction temperature
Vundershoot
Tj
V
125
°C
ELECTROSTATIC DISCHARGE SPECIFICATIONS
Use extreme caution to avoid damage due to electrostatic discharge (ESD). Proper use of wrist and heel grounding straps
to discharge static electricity is required when handling microprocessor devices. When storing a device, place it in antistatic
packaging.
Table 21: ESD Specifications
Pin Type
Symbol
Condition
ESD Rating
Unit
ESD, Handling Reference:
NQY00083, Section 3.4, Group D9,
Table B
ESD_HAND_HBM
Human Body Model Contact
Discharge per JEDEC EID/
JESD22-A114
+1500
V
Either HBM or MM to be tested.
CDM to be tested
ESD_HAND_MM
ESD_HAND_CDM
Machine Model Contact
+50
V
V
ChargedDeviceModelContact +200
Discharge per JEDEC EIA/
JESD22-C101
Broadcom Corporation
Document 4325-DS04-R
Operating Conditions and DC Characteristics
Page 75
BCM4325
Preliminary Data Sheet
6/30/09
ENVIRONMENTAL RATINGS
Table 22: Environmental Ratings
Characteristic
Value
Units
Conditions/Comments
Ambient Temperature (TA)
Storage Temperature
Relative Humidity
–30 to 85
oC
oC
%
Operation
–
–40 to 125
Less than 60
Less than 85
Storage
Operation
%
RECOMMENDED OPERATING CONDITIONS
Table 23: Recommended Operating Conditions and DC Characteristics
Value
Element
Symbol
Unit
Minimum
Typical
Maximum
DC supply voltage for VBATT a
DC supply voltage for I/O a
DC supply voltage for WLAN PAsa
VDDBATT
VDDIO
2.3
3.3
5.5
V
V
V
1.62
3.3 or 1.8
3.3
3.63
3.63
WRF_VDDPAG 2.97
WRF_VDDPAA
VDDTF
2.38
DC Supply for BT PAa:
Class1
2.5
1.5
1.25
1.25
–
2.63
1.6
V
V
V
V
V
V
V
V
V
V
Class2
1.4
Class3
1.19
1.31
1.31
0.8
DC supply voltage for core a
Input low voltage (VDDIO = 3.3V)
Input high voltage (VDDIO = 3.3V)
Input low voltage (VDDIO = 1.8V)
Input high voltage (VDDIO = 1.8V)
Output low voltage
VDDC
VIL
1.19
–
VIH
2.0
–
–
VDDIO
0.6
VIL
–
VIH
1.1
–
–
VDDIO
0.4
VOL
VOH
–
Output high voltage
VDDIO –
0.4V
–
Input low current
IIL
–
–
–
–
–
0.3
0.3
–
–
μA
μA
Input high current
IIH
–
Output low current (VDDIO = 3.3V, VOL = 0.4V)
Output high current (VDDIO = 3.3V, VOH = 2.9V)
SDIO input/output current
IOL
IOH
Isdio
3.0
3.0
12
mA
mA
mA
–
–
a. Caution: Functional operation is not guaranteed outside specified limits. Operation outside these limits for extended periods
may adversely affect the long-term reliability of the device.
Broadcom Corporation
Page 76
Environmental Ratings
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
BLUETOOTH AND FM CURRENT CONSUMPTION
Note: WLAN_RST_N is low for all measurements.
Note: For Class 1, VDDTF is supplied 2.5V externally separate from VBATT. For FM, the Bluetooth is in reset.
The current consumption numbers are measured based on typical output power specified in the
Table 27: “Bluetooth Transmitter RF Specifications,” on page 81.
Table 24: Bluetooth and FM Current Consumption
Class 1
Vbat=3.6V and Vddio=3.3V
VDDTF
Class 2
Test
Item
Vbat=3.6V and Vddio=3.3V
Operating Mode
Unit
VBAT
VDDIO
VBAT
VDDIO
=2.5V
1
Sleep
0.18
0.41
0.30
0.41
0.61
0.50
0.41
0.41
1.01
0.001
0.004
0.002
0.004
0.01
0.005
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
mA
mA
mA
mA
mA
mA
mA
mA
mA
2
Standard 1.28s Inquiry Scan
Standard 2.56s Inquiry Scan
R1 Standard Page Scan
Standard page and 1.28s Inquiry Scan
Standard page and 2.56s Inquiry Scan
500 ms Sniff Master
–
–
–
–
–
–
–
–
3
4
5
6
0.005
0.06
7
8
500 ms Sniff Slave
0.06
13
500 ms Sniff Master Page and
1.28s Inquiry Scan
0.06
17
18
19
22
23
24
25
DM1/DH1 Master
DM3/DH3 Master
DM5/DH5 Master
HV3 Master a
18.10
19.20
19.28
10.54
9.50
22.24
26.84
25.08
7.42
–
–
23.26
25.10
24.78
12.31
–
–
mA
mA
mA
mA
mA
mA
mA
–
–
–
–
–
–
FM I2S Audio
–
–
FM Analog Audio
BT_Reset + WL_Reset
11.00
0.02
–
–
–
–
0.001
0.005
–
0.005
a. Includes sniff.
Broadcom Corporation
Document 4325-DS04-R
Recommended Operating Conditions
Page 77
BCM4325
Preliminary Data Sheet
6/30/09
WLAN CURRENT CONSUMPTION
Note: BT_RST_N is low for all measurements.
Table 25: WLAN Current Consumption using Power Topology #1 (Vbatt with Buck-Boost) a
VBATT = 3.6V, VDDIO = 3.3V
Typical Units
Operational State
Leakage (WLAN and BT/FM in reset) b, c, d
Sleep with Buck-Boost in burst mode (driver controlled)
Sleep with Buck-Boost shutdown (driver controlled)
Idle between beacons
20
uA
250
160
152
1.3
553
78
uA
uA
uA
IEEE PS@DTIM = 100 ms
mA
uA
IEEE PS@DTIM = 300 ms
Beacon reception
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rx 1 Mbps
79
Rx 11 Mbps
79
Rx 6 Mbps
81
Rx 54 Mbps
83
TX 1 Mbps, 18 dBm at chip Tx output e
TX 1 Mbps, 21 dBm at chip Tx output e
TX 11 Mbps, 18 dBm at chip Tx output e
TX 11 Mbps, 21 dBm at chip Tx output e
TX 6 Mbps, 17 dBm at chip Tx output e
TX 6 Mbps, 20 dBm at chip Tx output e
TX 54 Mbps, 17 dBm at chip Tx output e
TX 54 Mbps, 20 dBm at chip Tx output e
245
288
249
295
240
276
241
277
a. For details, refer to the BCM4325 Power Supply Topologies application note (document number 4325-AN60X-R).
b. Additional leakage current may occur at the board level, depending on factors such as the power topology and external PU/
PD resistors, etc.
c. All measurements include VDDIO current with VDDIO = 3.3V.
d. All measurements exclude current drawn by the external 32.768 KHz oscillator, which is required for operation.
e. Chip Tx output power is based on Broadcom reference board measurements and backward calculation from antenna test
port.
Broadcom Corporation
Page 78
Recommended Operating Conditions
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 17: Bluetooth RF Specifications
Note: Unless otherwise stated, all specifications in this section apply to the operating temperature and voltage
ranges specified in Table 20 and Table 22 on page 76 and Table 23 on page 76. Functional operation outside
these limits is not guaranteed.
Table 26: Bluetooth Receiver RF Specifications
Parameter
General
Conditions
Minimum Typical d Maximum Unit
Frequency range
RX sensitivity a
–
2402
–
–
2480
–84.0
–84.0
–80.0
–
MHz
dBm
dBm
dBm
dBm
dBm
GFSK, 0.1% BER, 1 Mbps
–88.0
–90.0
–85.0
–
π/4-DQPSK, 0.01% BER, 2 Mbps –
8-DPSK, 0.01% BER, 3 Mbps
–
Input IP3
–
–
–16
–
Maximum input
–
–20.0
Interference Performance
C/I cochannel
GFSK, 0.1% BER
GFSK, 0.1% BER
GFSK, 0.1% BER
GFSK, 0.1% BER
GFSK, 0.1% BER
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
11.0
0.0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I ≥ 3-MHz adjacent channel
C/I image channel
–30.0
–40.0
–9.0
–20.0
13.0
0.0
C/I 1 MHz adjacent to image channel GFSK, 0.1% BER
C/I co-channel
π/4-DQPSK, 0.1% BER
π/4-DQPSK, 0.1% BER
π/4-DQPSK, 0.1% BER
8-DPSK, 0.1% BER
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I ≥ 3 MHz adjacent channel
C/I image channel
–30.0
–40.0
–7.0
–20.0
21.0
5.0
π/4-DQPSK, 0.1% BER
C/I 1 MHz adjacent to image channel π/4-DQPSK, 0.1% BER
C/I cochannel
8-DPSK, 0.1% BER
8-DPSK, 0.1% BER
8-DPSK, 0.1% BER
8-DPSK, 0.1% BER
8-DPSK, 0.1% BER
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I > = 3 MHz adjacent channel
C/I Image channel
–25.0
–33.0
0.0
C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER
–13.0
Out-of-Band Blocking Performance (CW)
30 MHz – 2000 MHz
2000 – 2399 MHz
0.1% BER
0.1% BER
0.1% BER
0.1% BER
–
–
–
–
–10.0
–27
–
–
–
–
dBm
dBm
dBm
dBm
2498 – 3000 MHz
–27
3000 MHz – 12.75 GHz
–10.0
Broadcom Corporation
Document 4325-DS04-R
Bluetooth RF Specifications
Page 79
BCM4325
Preliminary Data Sheet
6/30/09
Table 26: Bluetooth Receiver RF Specifications (Cont.)
Minimum Typical d Maximum Unit
Parameter
Conditions
Out-of-Band Blocking Performance, Modulated Interferer b
824 – 849 MHz, CDMA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–10
–2
–
–
–
–
–
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
824 – 849 MHz, EDGE/GSM
880 – 915 MHz, EDGE/GSM
1710 – 1785 MHz, EDGE/GSM
1850 – 1910 MHz, EDGE/GSM
1850 – 1910 MHz, CDMA
1850 – 1910 MHz, WCDMA
1920 – 1980 MHz, WCDMA
776 – 794 MHz, CDMA
–2
–5
–5
–15
–20
–20
–10
Spurious Emissions c
30 MHz – 1 GHz
–
–
–
–
–80
–51
–57
–47
dBm
dBm
1 GHz – 12.75 GHz
Cell-band Noise Floor
824 – 850 MHz, EDGE/GSM
880 – 915 MHz, EDGE/GSM
1710 – 1785 MHz, EDGE/GSM
1850 – 1910 MHz, EDGE/GSM
1920 – 1980 MHz, WCDMA
–
–
–
–
–
–
–
–
–
–
–145
–145
–145
–145
–145
–
–
–
–
–
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
a. The receiver sensitivity is measured at a BER of 0.1% on the device interface.
b. Bluetooth reference level of –82 dBm.
c. Includes baseband-radiated emissions.
d. Typical operating conditions are 1.25V operating voltage and 25°C ambient temperature.
Note: The maximum value represents the actual Bluetooth specification required for Bluetooth qualification as
defined in the version 2.1 specification.
Broadcom Corporation
Page 80
Bluetooth RF Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 27: Bluetooth Transmitter RF Specifications a
Parameter
General
Minimum
Typical
Maximum
Unit
Frequency range
2402
–
2480
MHz
dBm
dBm
dBm
dBm
dB
Class1, TX max powerBT_VDDTF = 2.5V (max. up to 3.1V)
Class2, TX max powerBT_VDDTF = 1.5V
Class1, TX min powerBT_VDDTF = 2.5V (max. up to 3.1V)
Class2, TX min powerBT_VDDTF = 1.5V
Gain step
4.5
0
7.5
4b
–
–
–
–
6
–
–18
–20
4
–
2
In-Band Spurious Emissions
+500 kHz
–
–
–
–
–
–
–
–
–20.0
–26.0
–40.0
–60.0
dBc
dBc
dBm
dBm
1.0 MHz < |M – N| < 1.5 MHz
1.5 MHz < |M – N| < 2.5 MHz
|M – N| ≥ 2.5 MHz
Out-of-Band Spurious Emissions
30 MHz to 1 GHz
–
–
–
–
–
–
–
–
–36.0 c, d
–30.0 a
–37.0
dBm
dBm
dBm
dBm
1 GHz to 12.75 GHz
1.8 GHz to 1.9 GHz
5.15 GHz to 5.3 GHz
–37.0
GPS Band Spurious Emissions
Without SAW filter
–
–150
–
dBm/Hz
Out-of-Band Noise Floor
746 MHz to 764 MHz
–
–
–
–
–
–
–145
–145
–145
–145
–145
–145
–
–
–
–
–
–
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
851 MHz to 894 MHz
925 MHz to 960 MHz
1805 MHz to 1880 MHz
1930 MHz to 1990 MHz
2110 MHz to 2170 MHz
a. The RF characteristics are measured at the device interface.
b. Actual output power can be adjusted to a lower level based on product requirements.
c. The maximum value represents the value required for Bluetooth qualification as defined in the version 2.1 specification.
d. The spurious emissions during Idle mode are the same as specified in Table 26 on page 79.
Broadcom Corporation
Document 4325-DS04-R
Bluetooth RF Specifications
Page 81
BCM4325
Preliminary Data Sheet
6/30/09
Section 18: FM Receiver Specifications
Note: Unless otherwise stated, all specifications in this section apply to the operating temperature and voltage
ranges specified in Table 20 and Table 22 on page 76 and Table 23 on page 76. Functional operation outside
these limits is not guaranteed.
Table 28: FM Receiver Specifications
Parameter
Conditions
Minimum Typical Maximum Units
RF Parameters
Operating frequency
Frequencies inclusive
76
–
–
108
MHz
dBm
Sensitivity, V
RF
FM only, fmod = 1kHz
–105
–102
Δf = 22.5 kHz (S+N)/N=26 dB
BAF = 300 Hz to 15 kHz
A-weighted de-emphasis = 50 μs, fIN = 76 to
108 MHz
RDS. For an RDS deviation of 1.2 kHz. 95% of
blocks decoded with no errors, over a sample of
5000 blocks. b
–
23
19
–
28
24
–
dBuV
dBuV
dB
RDS. For an RDS deviation of 2 kHz. 95% of blocks –
decoded with no errors, over a sample of 5000
blocks. b
Receiver adjacent channel At 200 kHz. fIN = 76 to 108 MHz, Measured for
16
selectivity
40 dB SNR at the audio output.
At 300 kHz (as above)
25
–
–
–
–
dB
dB
Image response (assuming At fwanted 2f IF depending on LO injection relative 25
image frequency ≥
300 kHz), mono
to Fwanted. Should be 40 dB SNR at the audio output
Image response (assuming
image frequency ≥
0
–
–
–
–
–
–
–
–
dB
dB
dB
dB
300 kHz), stereo
Min S/N for in band blocking Wanted level set to –90 dBm, Δf = 75 kHz, Interferer 35
for offsets > 400 KHz and < level set to –55 dBm, Δf = 40 kHz,
1 MHz, mono
1-kHz tone, AGC on
Min S/N for in band blocking Wanted level set to –72 dBm, Δf = 75 kHz,
for offsets > 400 KHz and < 1-kHz tone. Interferer level set to –37 dBm
1 MHz, stereo
35
Intermediate S/N in the
Overall third-order intercept point, for tones 400 40
presence of intermodulation and 800 kHz, 4 and 8 MHz. Reference level is –
82 dBm, tone levels set at –50 dBm.
fIN = 76 to 108 MHz. AGC enabled
AM suppression, mono
AM suppression, stereo
Vin = –90 dBm, fmod = 1 kHz, Δf = 22.5 kHz,
m = 0.3, BAF = 300 Hz to 15 kHz, L = R,
de-emphasis = 75 μs
40
40
–
–
–
–
dB
dB
Vin = –47 dBm, fmod = 1 kHz, Δf = 22.5 kHz,
m = 0.3, BAF = 300 Hz to 15 kHz, L = R,
de-emphasis = 75 μs
Broadcom Corporation
Page 82
FM Receiver Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 28: FM Receiver Specifications (Cont.)
Conditions Minimum Typical Maximum Units
Parameter
Intermediate S/N
Vin = –90 dBm, fmod = 1 kHz, Δf = 22.5 kHz,
m = 0.3, BAF = 300 Hz to 15 kHz A-weighted,
MONO, de-emphasis = 50 μs
45
–
–
dB
RF Input
RF input impedance
Single-ended input with optional external matching –
circuitry
50
–
Ω
RF input level
Maximum on-channel input level 76–108 MHz.
–
–
–
–
–10
–6
dBm
dB
RF input impedance return With external matching circuitry
loss
RF conducted emissions
Local oscillator breakthrough measured on the
reference port
–
–
–
–
–
–
–
–
–
–
–55
–90
0
dBm
dBm
dBm
dBm
dBm
925–960 MHz, 1805 –1880 MHz and 1930–
1990 MHz
RF blocking levels at the FM 824–915 MHz, GSM 200 kHz BW,
antenna input. (Assumes
presence of an external
matching circuit.)
CDMA 1.2 MHz BW
1710–1980 MHz, GSM 200 kHz BW,
CDMA 1.2 MHz BW, WCDMA 4 MHz BW
–5
2.4–2.4835 GHz, BT 1 MHz BW,
WLAN 20 MHz BW
–20
PLL
Frequency step
Settling time
Channel offset
–
–
–
5
50
–
kHz
ms
Single frequency switch in any direction to a
frequency within the bands 88–108 MHz or 76–
90 MHz. Time measured to within 5 kHz of the final
frequency.
Sweep time
Total time for an automatic search to sweep from
88–108 MHz or 76–90 MHz (and reverse direction)
assuming no channels found.
–
8
–
sec
Soft Mute
Soft mute start level a
Mute attenuation = 3 dB
3
5
10
30
uV
dB
Soft mute attenuation
Vin = 1 μV, Δf = 22.5 kHz, L = R fmod = 1 kHz,
BAF = 300 Hz to 15 kHz, de-emphasis = 75 μs
10
20
General Audio
Audio output level
Vin = 1 mV, Δf = 22.5 kHzp fmod = 1 kHz, L = R,
de-emphasis = 75 μs. Δf Pilot = 6.75 kHzp,
Rload > 30 kΩ
60
75
–
90
mV,
rms
Maximum audio output level Vin = 1 mV, Δf = 100 kHzp fmod = 1 kHz, L = R, de- –
emphasis = 75 μs. Δf Pilot = 6.75 kHzp,
360
mV,
rms
Rload > 30 kΩ
Audio output level difference Vin = 1 mV, Δf = 22.5 kHz, fmod = 1 kHz, L = R,
de-emphasis = 75 μs
–1
–
1
–
–
dB
dB
dB
Max signal plus noise to
noise ratio (S+N)/N, mono de-emphasis = 50 μs, L = R, BAF = 300 Hz to
Vin = 1 mV, Δf = 22.5 kHz, fmod = 1 kHz,
53
48
57
53
15 kHz (A-Weighted) fIN = 76 to 108 MHz
Max signal plus noise to
noise ratio (S+N)/N, stereo
Broadcom Corporation
Document 4325-DS04-R
FM Receiver Specifications
Page 83
BCM4325
Preliminary Data Sheet
6/30/09
Table 28: FM Receiver Specifications (Cont.)
Parameter
Conditions
Minimum Typical Maximum Units
Total harmonic distortion,
mono
Vin = 1 mV, Δf = 75 kHz, L = R, fmod = 400 Hz, de- –
emphasis = 50 μs.
0.4
0.4
0.5
0.9
–
0.8
0.8
1.0
1.5
–60
%
Vin = 1 mV, Δf = 75 kHz, L = R, fmod = 1 kHz,
de-emphasis = 50 μs.
–
%
Vin = 1 mV, Δf = 100 kHz, L = R, fmod = 1 kHz, de- –
emphasis = 50 μs.
%
Total harmonic distortion,
stereo
Vin = 1 mV, Δf = 75 kHz, L = R, fmod = 3 kHz,
de-emphasis = 50 μs.
–
%
Audio spurious products
Vin = 1 mV, Δf = 22.5 kHz, fmod = 1 kHz,
de-emphasis = 50 μs, L = R, BAF = 300 Hz to
15 kHz (A-Weighted), fIN = 76 to 108 MHz,
With respect to 1 kHz tone.
–
dBc
Audio bandwidth, upper
(–3 dB point)
Vin = 1 mV, Δf = 22.5 kHz, for both 50 and 75 μs
15
–
–
–
–
–
KHz
Hz
de-emphasis, pre-emphasis applied.
Audio bandwidth, lower
(–3 dB point)
20
0.5
Deviation of the audio
response from an ideal
de-emphasis curve
100 Hz to 13 kHz, Vin = 1 mV, Δf = 22.5 kHz, for
both 50 and 75 μs de-emphasis, pre-emphasis
applied.
–
dB
De-emphasis time constant With respect to 50 and 75 μs.
–
–
–
5
–
%
tolerance
Audio output impedance
When FM function is disabled, or when left or right 50
channels are hard-muted via the bus.
KΩ
Audio output impedance
Left and right AC_mute
When FM function is enabled and in any of the
following modes: autosearch, AC-muted by
software, or RF soft-mute is active.
–
50
–
–
–
–
Ω
60
80
dB
dB
Right audio output hard
muting attenuation
–
Left audio output hard
muting attenuation
80
–
–
dB
Pause Detection
Audio level at which a pause Relative to 1 kHz tone, 22.5 kHz deviation, 50 μs
–
–
–
–
is detected
de-emphasis
Four values in 3 dB steps
Four values
–21
20
–
–
–12
40
dB
ms
Audio pause duration
Stereo Decoder
Stereo channel separation SNC OFF, increasing RF input, switched from mono 27
to stereo Δf = 75 kHz, fmod = 1 kHz, 30 μV input
30
–
–
–
dB
dB
level, R = 0, L = 1 including 9% pilot
Pilot suppression
Measured at audio outputs. Δf = 75 kHz,
fmod = 1 kHz, de-emphasis = 75 μs
46
a. Start level is configurable.
b. RDS sensitivity range is only from 87.5 MHz to 108 MHz.
Broadcom Corporation
Page 84
FM Receiver Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 19: WLAN RF Specifications
INTRODUCTION
The BCM4325 includes an integrated dual-band direct conversion radio that supports either the 2.4 GHz IEEE 802.11g band
or the 5 GHz IEEE 802.11a band. The BCM4325 does not provide simultaneous 2.4 GHz and 5 GHz operation. This section
describes the RF characteristics of the 2.4 GHz and 5 GHz portions of the radio.
Note: Unless otherwise stated, all specifications in this section apply to the operating temperature and voltage
ranges specified in Table 20 and Table 22 on page 76 and Table 23 on page 76. Functional operation outside these
limits is not guaranteed.
CELLULAR BLOCKING
WLAN and cellular transceivers have separate antennas. The isolation between the antennas is 20 dB in all cases (for
example, the maximum EGSM900 signal power at the WLAN RF port is +13 dBm).
Table 29: Blocking Signals from Embedded Cellular Transmitter at Cellular Antenna Port
System
Frequency (MHz)
Maximum Power Output
Modulation
GSM
824–849
+33 dBm
+27
GMSK
EDGE
QPSK
GMSK
EDGE
GMSK
EDGE
GMSK
EDGE
QPSK
QPSK
–
CDMA
824–849
880–915
+25
EGSM900
+33
+27
DCS1800
PCS1900
1710–1785
1850–1910
+30
+26
+30
+26
CDMA
1850–1910
1920–1980
2400–2500
+24
WDCMA FDD
+21
Wideband noise from
cellular TX
–150 dBm/Hz
Note: GMSK and EDGE transmissions have duty cycle of 1/8 or 1/4. Nominal repetition rate of transmission is about 217
Hz. QPSK transmissions for (W)CDMA have a duty cycle of 1.
Broadcom Corporation
Document 4325-DS04-R
WLAN RF Specifications
Page 85
BCM4325
Preliminary Data Sheet
6/30/09
WLAN RECEIVER BLOCKING PERFORMANCE
The total contribution of out-of-band signals from a cellular band transmitter and wideband noise falling on the WLAN band
does not reduce the sensitivity of the WLAN receiver more than 1 dB compared to the performance without interference.
Only one cellular transmitter is active at a time.
The cited specifications assume the use of an external cellular blocking filter that has the following characteristics:
•
•
•
•
•
•
•
•
•
(NdBa) TiO3 (Er = 88/TCf = 0 10 ppm/K) with a coating of copper (10 μm thick) and tin (>5 μm thick)
Operating temperature = –30°C to +85°C
Center frequency = 2.450 GHz
Insertion loss = 0.7 dB (typical), 1.0 dB (maximum)
Pass band (2400–2500) = 100 MHz (minimum)
Amplitude ripple (peak-to-peak) = 0.4 dB (typical), 0.8 dB (maximum)
SWR = 1.5 (typical), 2.0 (maximum)
Impedance = 50Ω (typical)
Attenuation:
-
-
-
-
@ DC to 880 MHz — 50 dB (minimum), 55 dB (typical)
@ 880 to 960 MHz — 45 dB (minimum), 50 dB (typical)
@ 960 to 1990 MHz — 40 dB (minimum), 45 dB (typical)
@ 1990 to 2100 MHz — 25 dB (minimum), 30 dB (typical)
2.4 GHZ BAND GENERAL RF SPECIFICATIONS
Table 30: 2.4 GHz Band General RF Specifications
Item
Condition
Minimum Typical
Maximum
Unit
TX/RX Switch Time
RX/TX Switch Time
Including TX ramp down
Including TX ramp up
–
–
5
5
10
5
μs
μs
2.4 GHZ BAND LOCAL OSCILLATOR SPECIFICATIONS
Table 31: 2.4 GHz Band Local Oscillator Specifications
Characteristic
Condition
Minimum
Typical
Maximum
Unit
VCO Frequency Range
Reference Input Frequency Range
Reference Spurs
–
–
–
–
2412
–
2484
–
MHz
MHz
–
–
–
Various a
–
–
–34
–86.5
dBc
Local Oscillator Phase Noise, single-sided from 1
to 300 kHz offset
dBc/Hz
Clock Frequency Tolerance
–
–
–
20
ppm
a. Reference supported frequencies range from 13 MHz to 52 MHz.
Broadcom Corporation
Page 86
2.4 GHz Band General RF Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
2.4 GHz BAND RECEIVER RF SPECIFICATIONS
Table 32: 2.4 GHz Band Receiver RF Specifications
Characteristic
Condition
Minimum Typical
Maximum
Unit
Cascaded Noise Figure
–
–
4
–
dB
Maximum Receive Level (when using a @ 1, 2 Mbps
–4
–
–
dBm
dBm
dBm
MHz
–
suitable external switch)
@ 5.5, 11 Mbps
–10
–10
–
–
–
@ 54 Mbps
–
–
PGA DC Rejection Servo Loop
Bandwidth
WB mode
1
–
NB mode
120 Hz
–
–
230 kHz
LPF DC Rejection Servo Loop
Bandwidth
WB mode
500
–
–
kHz
–
NB mode
120 Hz
35
230 kHz
–
Adjacent Channel Power Rejection
(DSSS at 11Mbps a)
Rx = –70 dBm b
–
dB
Maximum Receiver Gain
–
–
>100
–
dB
a. The difference between the interfering and desired signal (> 25 MHz apart) at 8% PER for 1024 octet PSDU with desired
signal level, as specified.
b. Values are measured at the input to the BCM4325. Accordingly, they include insertion losses from the integrated baluns, but
these values do not include the insertion loss of the external RF path. Reference sensitivity (10% PER for OFDM and 8%
PER for DSSS for 1000-octet PSDU) at chip input.
2.4 GHZ RECEIVER PERFORMANCE SPECIFICATIONS
Table 33: 2.4 GHz Receiver Performance Specifications
Typical Receive Sensitivity a
Rate/Modulation
1 Mbps DSSS
2 Mbps DSSS
5.5 Mbps DSSS
11 Mbps DSSS
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
–96.0 dBm
–95.0 dBm
–93.0 dBm
–90.5 dBm
–91.5 dBm
–91.0 dBm
–90.5 dBm
–89.0 dBm
–85.5 dBm
–82.5 dBm
–77.0 dBm
–75.5 dBm
a. Values are measured at the input to the BCM4325. Accordingly, they include insertion losses from the integrated baluns, but
these values do not include the insertion loss of the external RF path. Reference sensitivity (10% PER for OFDM and 8%
PER for DSSS for 1000-octet PSDU) at chip input.
Broadcom Corporation
Document 4325-DS04-R
2.4 GHz Band Receiver RF Specifications
Page 87
BCM4325
Preliminary Data Sheet
6/30/09
2.4 GHZ BAND TRANSMITTER RF SPECIFICATIONS
Table 34: 2.4 GHz Band Transmitter RF Specifications
Characteristic
Condition
Minimum Typical Maximum Unit
RF Output Frequency Range
Output Power (EVM Compliant)
Gain Flatness
–
2400
–
–
2500
+22 c
2
MHz
dBm
dB
Maximum gain
–
Maximum gain
–
–
Output IP3
Maximum gain
–
37
27
–
–
dBm
dBm
dBr
dBr
dBr
dBr
dBc
dBr
dBr
–
Output P1dB
–
–
–
–
Carrier Suppression
15
–
–
TX Spectrum mask @ maximum gain fc – 22 MHz < f < fc – 11 MHz
–
–30
–30
–50
–26
–35
–40
35%
5%
CCK
fc + 11 MHz < f< fc + 22 MHz
f < fc – 22 MHz; and f > fc + 22 MHz
f < fc – 11 MHz and f > fc + 11 MHz
f < fc – 20 MHz and f > fc + 20 MHz
f < fc – 30 MHz and f > fc + 30 MHz
IEEE 802.11b mode
–
–
–
–
TX Spectrum mask
(chip output power = 16 dBm)
OFDM
–
–
–
–
–
–
TX Modulation Accuracy (EVM) at
maximum gain
–
–
IEEE 802.11g mode QAM64
54 Mbps
–
–
–
Gain Control Step Size
Amplitude Balance a
Phase Balance a
NA
–
0.25 dB
–
dB/step
dB
DC input
–1
–1.5
–
–
1
DC input
–
1.5
–
° (degrees)
Vpp
Baseband Differential Input Voltage
TX Power Ramp Up
Shaped pulse
90% of final power
10% of final power
0.6
–
–
2
μsec
TX Power Ramp Down
–
–
2
μsec
Out-of-Band Noise and Spurious Emissions
100 kHz to 1930 MHz
1930 to 2170 MHz
2170 to 2300 MHz
2300 to 2390 MHz
2484 to 2655 MHz
2655 to 4700 MHz
4700 to 12750 MHz
21 dBm at Chip Tx output b
–
–
–
–
–
–
–
–145
–135
–125
–115
–115
–125
–135
–
–
–
–
–
–
–
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
21 dBm at Chip Tx output b
21 dBm at Chip Tx output b
21 dBm at Chip Tx output b
21 dBm at Chip Tx output b
21 dBm at Chip Tx output b
21 dBm at Chip Tx output b
a. At a 3 MHz offset from the carrier frequency.
b. +21 dBm Chip Tx output power is based on Broadcom reference board level measurements and backward calculation from
antenna test port.
c. Referred to the chip output. The maximum output power at the antenna test port depends on board layout and output
matching.
Broadcom Corporation
Page 88
2.4 GHz Band Transmitter RF Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
5 GHZ BAND RECEIVER RF SPECIFICATIONS
Table 35: 5 GHz Band Receiver RF Specifications a
Characteristic
Condition
Minimum Typical
Maximum Unit
Cascaded Noise Figure
Maximum Receive Level a(5.24 GHz)
Maximum RX gain
@ 6 Mbps
–
4.5
–
–
dB
–10
–15
–
–
dBm
dBm
kHz
NA
@ 54 Mbps
WB mode
–
–
DC Rejection Servo Loop Bandwidth
(normal operation)
500
–
–
NB mode
Rx at –62 dBm d
120 Hz
–1
230 kHz
–
Adjacent Channel Power Rejection
(OFDM at 54 Mbps b)
–
dB
Alternate Adjacent Channel Power
Rejection (OFDM at 54Mbps c)
Rx at –61.5 dBm d
15
–
–
dB
Minimum RX Gain
Maximum RX Gain
IQ Amplitude Balance
IQ Phase Balance
–
–
–
–
–
–
–
–
15
–
–
–
–
dB
>100
0.5
dB
dB
1.5
Degree
Out-of-Band Blocking Performance without RF Band-Pass Filter (–1dB desensitization)
CW
CW
CW
30 – 4300 MHz
–10
–25
–25
–
–
–
–
–
–
dBm
dBm
dBm
4300 – 4800 MHz
5900 – 6400 MHz
a. With minimum RF gain.
b. The difference between the interfering and tehe desired signal (20 MHz apart) at 10% PER for 1000 octet PSDU with the
desired signal level, as specified.
c. The difference between the interfering and the desired signal (40 MHz apart) at 10% PER for 1000 octet PSDU with desired
signal level, as specified.
d. Values are measured at the input pin of the BCM4325. Accordingly, they include insertion losses from the integrated baluns
but do not include the insertion loss of the external RF path.
Broadcom Corporation
Document 4325-DS04-R
5 GHz Band Receiver RF Specifications
Page 89
BCM4325
Preliminary Data Sheet
6/30/09
5 GHZ BAND TRANSMITTER RF SPECIFICATIONS
Table 36: 5 GHz Band Transmitter RF Specifications
Characteristic
Condition
Minimum Typical Maximum Unit
RF Output Frequency Range
Gain Flatness
NA
4920
–
5805
1
MHz
dB
Maximum gain
–
–
Output IP3
Maximum gain
–
35
25
–
–
dBm
dBm
dBm
dBr
Output P1dB
Maximum gain
–
–
Output Power (EVM Compliant)
Carrier Suppression
TX Spectrum mask
(chip output power = 16 dBm)
OFDM
Minimum gain
–
–
–
–15
–
–
–
f < fc – 11 MHz and f > fc + 11 MHz
–
–26
–35
–40
–
dBc
f < fc – 20 MHz and f > fc + 20 MHz
–
–
dBr
f < fc – 30 MHz and f > fc + 30 MHz
–
–
dBr
Gain Control Step Size
I/Q Baseband 3 dB Bandwidth
Amplitude Balance
NA
–
0.25
12
–
dB/step
MHz
dB
NA
–
–
DC Input
DC Input
–0.5
–1.5
–
0.5
1.5
–
Phase Balance
–
° (degree)
Vpp
Baseband Differential Input Voltage NA
0.7
–
TX Power Ramp Up
90% of final power
10% of final power
–
2
μsec
μsec
TX Power Ramp Down
–
–
2
5 GHZ BAND LOCAL OSCILLATOR FREQUENCY GENERATOR
SPECIFICATIONS
Table 37: 5 GHz Band Local Oscillator Frequency Generator Specifications
Characteristic
Condition
Minimum
Typical
Maximum
Unit
VCO Frequency Range
Reference Input Frequency Range
Reference Spurs
–
4920
–
5805
–
MHz
–
–
–
–
–
–
various a
MHz
–
–
–30
–
dBc
Local Oscillator Integrated Phase Noise
(1–300 kHz)
4.920–5.700 GHz
5.725–5.805 GHz
–
0.7
1.4
–
degree
degree
ppm
–
Clock Frequency Tolerance
20
a. Reference supported frequencies range from 13 MHz to 52 MHz.
Broadcom Corporation
Page 90
5 GHz Band Transmitter RF Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
5 GHZ RECEIVER PERFORMANCE SPECIFICATIONS
Table 38: 5 GHz Receiver Performance Specifications
Typical Receive Sensitivity a
Rate/Modulation
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
–89.5 dBm
–89.0 dBm
–89.0 dBm
–88.5 dBm
–84.5 dBm
–81.5 dBm
–76.5 dBm
–74.5 dBm
a. Values are measured at the BCM4325 input pin. Accordingly, they include insertion losses from the integrated baluns, but do
not include the insertion loss of the external RF path. Reference sensitivity (10% PER for 1000-octet PSDU) at chip input.
Broadcom Corporation
Document 4325-DS04-R
5 GHz Receiver Performance Specifications
Page 91
BCM4325
Preliminary Data Sheet
6/30/09
Section 20: Internal Regulator Electrical
Specifications
Note: Functional operation is not guaranteed outside specified limits. Operation outside these limits for extended
periods may adversely affect the long-term reliability of the device.
CLDO
Table 39: CLDO
Specification
Notes
Minimum Typical
Maximum Unit
Input supply voltage a
–
–
1.5
1.25
–
1.98
1.35
4
Volt
Volt
%
Output voltage
Programmable in 25 mV steps 1.10
Absolute accuracy
Output current
–
–
–
–
–
–
200
15
10
–
mA
uA
LDO quiescent current
–
10
0.1
80
40
–
Leakage current through output transistor CLDO_pu=0
–
uA
Output noise
@30 kHz, 200 mA load
–
nV/rt Hz
dB
Power supply rejection (PSR)
Dropout voltage
@1 kHz, 150 mV dropout
–
–
–
–
150
–
–
mV
ms
Start-up time
–
0.5
a. For good PSRR performance, the input supply should be at least 200 mV higher than the output.
Broadcom Corporation
Page 92
Internal Regulator Electrical Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
LNLDOI (I = 1, 2, OR 4)
LNLDO4 is only available in the 339-pin CSP package.
Table 40: LNLDOi
Specification
Notes
Minimum Typical
Maximum Unit
Input supply voltage a
LNLDOi_vo_sel=0
LNLDOi_vo_sel=1
LNLDOi_vo_sel=0
LNLDOi_vo_sel=1
–
–
1.5
3.3
1.25
2.5
–
1.98
3.6
1.35
3.1
4
Volts
–
Output voltage
1.10
2.5
–
Volts
Absolute accuracy
%
Output current for LNLDO1
Output current for LNLDO2
Output current for LNLDO4
Quiescent current for LNLDO1
–
–
–
130
80
80
44
206
42
202
–
mA
mA
mA
uA
–
–
–
–
–
–
LNLDOi_vo_sel=0
LNLDOi_vo_sel=1
LNLDOi_vo_sel=0
LNLDOi_vo_sel=1
LNLDO1_pu=0
LNLDOi_vo_sel=0
LNLDOi_vo_sel=1
LNLDO1_pu=0
LNLDOi_vo_sel=0
LNLDOi_vo_sel=1
@30 kHz, 50 mA load
LNLDOi_vo_sel=0
LNLDOi_vo_sel=1
@1 kHz, 150 mV dropout
–
–
31
110
29
108
–
–
Quiescent current for LNLDO2 and 4
Leakage current for LNLDO1
–
uA
–
–
–
0.1
0.1
–
5
uA
–
9
Leakage current for LNLDO2 and 4
Output noise
–
–
–
0.1
0.1
–
2
uA
–
4
–
–
–
20
31
50
–
–
nV/rt Hz
–
–
PSRR
–
–
dB
Dropout voltage
Start-up time
150
–
–
mV
ms
–
–
0.5
a. For good PSRR performance, the input supply should be at least 200 mV higher than the output.
Broadcom Corporation
Document 4325-DS04-R
LNLDOi (i = 1, 2, or 4)
Page 93
BCM4325
Preliminary Data Sheet
6/30/09
CORE BUCK REGULATOR
Table 41: Core Buck Regulator
Specification
Notes
Minimum Typical
Maximum Units
Input supply voltage
–
–
–
2.3
2.24
–
–
5.5
Volts
MHz
PWM mode switching frequency
PWM output current
2.8
–
3.36
300
1.75
20
mA
Output voltage range
Programmable, 25 mV steps
1
–
–
1.5
–
Volts
mVp-p
mVp-p
PWM ripple voltage, static load
PWM ripple voltage, dynamic load
–
200 mA, 1 μs rise/fall current
step
–
85
Burst mode ripple voltage, static
PWM mode efficiency
Burst mode efficiency
Quiescent current
–
–
–
80
–
mVp-p
%
200 mA load current
10 mA load current
Burst Mode
80
70
–
90 b
80 b
25
–
%
–
μA
μA
μA
μs
Low Power Burst Mode
Power Down
–
–
20
–
–
1
–
Start-up time from power down
Settling time: burst to PWM mode
500
200
1000
400
Ensure light-load (<30 mA)
during mode-change
–
–
μs
Settling time: PWM to burst mode
Ensure light-load (<30 mA)
during mode-change
–
100
μs
Input supply voltage ramp-up time 1 a
Input supply voltage ramp-up time 2 a
0 to 4.3V
44
–
–
–
–
μs
μs
4.3 to 5.5V
100
a. The 0 to 4.3V and 4.3 to 5Vramp up assumes a Li-ion insertion causing a max ramp slope
b. VBAT=3.3V, Vout=1.5V, fsw=2.76 MHz, inductor DCR=160 mOhms.
Broadcom Corporation
Page 94
Core Buck Regulator
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
BUCK-BOOST REGULATOR
Table 42: Buck-Boost Regulator
Specification
Notes
Minimum Typical
Maximum Unit
Input supply voltage
–
2.3
–
–
5.5
Volts
MHz
mA
PWM mode switching frequency
PWM output current
–
1.4
–
–
–
300
3.5
40
85
80
–
Output voltage range
Programmable, 50 mV steps
–
2.25
–
3.3
–
Volts
mVp-p
mVp-p
mVp-p
%
PWM ripple voltage, static
PWM ripple voltage, dynamic load
Burst mode ripple voltage, static
PWM mode efficiency
100 mA, 1 μs rise/fall current step –
–
–
–
–
86 b
200 mA load current
70
–
Quiescent current
Burst mode
No load
–
30
–
μA
Start-up time from power down
–
500
200
1000
400
μs
μs
Settling time: Burst-to-PWM mode
Ensure light-load (<30 mA) during –
mode change
Settling time: PWM-to-Burst mode
Ensure light-load (<30 mA) during –
mode change
–
100
μs
Input supply voltage ramp-up time 1
Input supply voltage ramp up time 2
0 to 4.3V a
4.3 to 5.5V a
44
100
–
–
–
–
μs
μs
a. The 0 to 4.3V and 4.3 to 5V ramp up assumes a Li-ion insertion causing a max ramp slope.
b. VBAT=3.65V, Vout=3.3V, fsw=1.38 MHz, inductor DCR=156 mOhms.
Broadcom Corporation
Document 4325-DS04-R
Buck-Boost Regulator
Page 95
BCM4325
Preliminary Data Sheet
6/30/09
Section 21: Interface Timing and AC
Characteristics
Note: Unless otherwise stated, all specifications in this section apply to the operating temperature and voltage
ranges specified in Table 20 and Table 22 on page 76 and Table 23 on page 76. Functional operation outside
these limits is not guaranteed.
BLUETOOTH PERIPHERAL TRANSPORT UNIT TIMING SPECIFICATIONS
This section describes the Peripheral Transport Unit (PTU) timing.
The following conditions apply:
VDD = 3.3V, VSS = 0V, TA = 0 to 85 oC
BLUETOOTH UART TIMING
BT_UART_CTS_N
1
2
BT_UART_TXD
Midpoint of stop bit
Midpoint of stop bit
3
BT_UART_RXD
BT_UART_RTS_N
Figure 16: UART Timing
Table 43: UART Timing Speicifications
Reference Description
Minimum Typical Maximum Unit
1
2
Delay time, BT_UART_CTS_N low to UART_TXD valid
–
–
–
–
24
10
Baudout cycles
ns
Setup time, BT_UART_CTS_N high before midpoint of
stop bit
3
Delay time, midpoint of stop bit to BT_UART_RTS_N high –
–
2
Baudout cycles
Broadcom Corporation
Page 96
Interface Timing and AC Characteristics
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
PCM INTERFACE TIMING
Short Frame Sync, Master Mode
2
1
3
PCM_BCLK
4
5
PCM_SYNC
6
9
HIGH
IMPEDENCE
Bit 15 (Previous Frame)
Bit 15
Bit 0
PCM_OUT
PCM_IN
7
8
Bit 15 (Previous Fram e)
Bit 0
Bit 15
Figure 17: PCM (Short Frame Sync, Master Mode) Timing
Table 44: PCM (Short Frame Sync, Master Mode) Timing Specifications
Reference Description Minimum Typical Maximum Unit
1
2
3
4
PCM bit clock frequency
128
128
209
–
–
–
–
–
2048
–
kHz
ns
PCM bit clock high time
PCM bit clock low time
–
ns
Delay from BT_PCM_CLK rising edge to BT_PCM_SYNC
high
50
ns
5
6
7
Delay from BT_PCM_CLK rising edge to BT_PCM_SYNC
low
–
–
–
–
50
50
–
ns
ns
ns
Delay from BT_PCM_CLK rising edge to data valid on
BT_PCM_OUT
–
Setup time for BT_PCM_IN before BT_PCM_CLK falling
edge
50
8
9
Hold time for BT_PCM_IN after BT_PCM_CLK falling edge 10
–
–
–
ns
ns
Delay from falling edge of BT_PCM_CLK during last bit period –
to BT_PCM_OUT becoming high impedance
50
Broadcom Corporation
Document 4325-DS04-R
Bluetooth Peripheral Transport Unit Timing Specifications
Page 97
BCM4325
Preliminary Data Sheet
6/30/09
Short Frame Sync, Slave Mode
2
1
3
PCM_BCLK
PCM_SYNC
4
5
6
9
HIGH
IMPEDENCE
Bit 15 (Previous Frame)
Bit 0
Bit 15
PCM_OUT
PCM_IN
7
8
Bit 15 (Previous Frame)
Bit 0
Bit 15
Figure 18: PCM (Short Frame Sync, Slave Mode) Timing
Table 45: PCM (Short Frame Sync, Slave Mode) Timing Specifications
Reference Description
Minimum Typical
Maximum Unit
1
2
3
4
PCM bit clock frequency
128
209
209
50
–
–
–
–
2048
kHz
ns
PCM bit clock high time
PCM bit clock low time
–
–
–
ns
Setup time for BT_PCM_SYNC before falling edge of
BT_PCM_BCLK
ns
5
Hold time for BT_PCM_SYNC after falling edge of
BT_PCM_CLK
10
–
–
ns
6
7
8
9
Hold time of BT_PCM_OUT after BT_PCM_CLK falling edge
–
–
–
–
–
175
–
ns
ns
ns
ns
Setup time for BT_PCM_IN before BT_PCM_CLK falling edge 50
Hold time for BT_PCM_IN after BT_PCM_CLK falling edge 10
–
Delay from falling edge of BT_PCM_CLK during last bit period to –
BT_PCM_OUT becoming high impedance
100
Broadcom Corporation
Page 98
Bluetooth Peripheral Transport Unit Timing Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Long Frame Sync, Master Mode
2
1
3
PCM_BCLK
4
5
PCM_SYNC
6
9
HIGH
IMPEDENCE
Bit 0
Bit 1
Bit 2
Bit 15
PCM_OUT
7
8
Bit 0
Bit 1
Bit 2
Bit 15
PCM_IN
Figure 19: PCM (Long Frame Sync, Master Mode) Timing
Table 46: TPCM (Long Frame Sync, Master Mode) Timing Specifications
Reference Description Minimum Typical Maximum Unit
1
2
3
4
PCM bit clock frequency
PCM bit clock high time
PCM bit clock low time
128
209
209
–
–
–
–
–
2048
–
kHz
ns
–
ns
Delay from BT_PCM_CLK rising edge to BT_PCM_SYNC
high during first bit time
50
ns
5
6
Delay from BT_PCM_CLK rising edge to BT_PCM_SYNC low –
during third bit time
–
–
50
50
ns
ns
Delay from BT_PCM_CLK rising edge to data valid on
BT_PCM_OUT
–
7
8
9
Setup time for BT_PCM_IN before BT_PCM_CLK falling edge 50
Hold time for BT_PCM_IN after BT_PCM_CLK falling edge 10
–
–
–
–
ns
ns
ns
–
Delay from falling edge of BT_PCM_CLK during last bit period –
to BT_PCM_OUT becoming high impedance
50
Broadcom Corporation
Document 4325-DS04-R
Bluetooth Peripheral Transport Unit Timing Specifications
Page 99
BCM4325
Preliminary Data Sheet
6/30/09
Long Frame Sync, Slave Mode
2
1
PCM_BCLK
3
4
5
7
PCM_SYNC
6
10
HIGH
Bit 15
Bit 0
Bit 1
PCM_OUT
IMPEDENCE
8
9
Bit 0
Bit 1
Bit 15
PCM_IN
Figure 20: PCM (Long Frame Sync, Slave Mode) Timing
Table 47: PCM (Long Frame Sync, Slave Mode) Timing Specifications
Reference Description
Min
Typ
Max
Unit
1
2
3
4
PCM bit clock frequency
128
209
209
50
–
–
–
–
2048
kHz
ns
PCM bit clock high time
PCM bit clock low time
–
–
–
ns
Setup time for BT_PCM_SYNC before falling edge of
BT_PCM_CLK during first bit time
ns
5
6
Hold time for BT_PCM_SYNC after falling edge of BT_PCM_CLK 10
during second bit period. (BT_PCM_SYNC may go low any time
from second bit period to last bit period)
–
–
–
ns
ns
Delay from rising edge of BT_PCM_CLK or BT_PCM_SYNC
(whichever is later) to data valid for first bit on BT_PCM_OUT
–
50
7
Hold time of BT_PCM_OUT after BT_PCM_CLK falling edge
Setup time for BT_PCM_IN before BT_PCM_CLK falling edge
Hold time for BT_PCM_IN after BT_PCM_CLK falling edge
–
–
–
–
–
175
–
ns
ns
ns
ns
8
50
10
–
9
–
10
Delay from falling edge of BT_PCM_CLK or BT_PCM_SYNC
(whichever is later) during last bit in slot to BT_PCM_OUT
becoming high impedance
100
Broadcom Corporation
Page 100
Bluetooth Peripheral Transport Unit Timing Specifications
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
FM I2S TIMING
The timing illustrated in Figure 21 and Figure 22 are described in Table 48 on page 102.
Note: The times given in Figure 21 and Figure 22 are determined by the transmitter speed. The specification of
the receiver must be capable of matching the performance of the transmitter.
T
tLC 0.35T
tHC 0.35T
tRC
*
VH = 2.0 V
VL = 0.8 V
I2S_SCK
tHTR
0
tDTR £ 0.8T
I2S_SDO
I2S_WS
Notes:
T = clock period
TTR = minimum allowed clock period for transmitter
T > TTR
* tRC is only relevant for transmitters in slave mode.
Figure 21: I2S Transmitter Timing
T
tHC 0.35T
tLC 0.35T
VH = 2.0 V
VL = 0.8 V
I2S_SCK
tSR 0.2T
tHR
0
I2S_SDO
I2S_WS
Notes:
T= Clock period
TR = Minimum allowed clock period for transmitter
T > TR
Figure 22: I2S Receiver Timing
Broadcom Corporation
Document 4325-DS04-R
FM I2S Timing Page 101
BCM4325
Preliminary Data Sheet
6/30/09
Table 48: Timing for I2S Transmitters and Receiversa
Transmitter
Lower LImit Upper Limit
Receiver
Lower Limit Upper Limit
Parameter
Notes
Min
Max
Min
Max
Min
Max
Min
Max
b
Clock Period T
TTR
–
–
–
T
–
–
–
a
r
Master Mode: Clock generated by transmitter or receiverc
High t
0.35TTR
0.35TTR
–
–
–
–
–
–
0.35TTR
0.35TTR
–
–
–
–
–
–
b
b
HC
Low tLC
Slave Mode: Clock accepted by transmitter or receiverd
High t
–
–
–
0.35TTR
0.35TTR
–
–
–
–
–
–
–
–
–
0.35TTR
0.35TTR
–
–
–
–
–
–
c
c
d
HC
Low t
LC
Rise-time t
0.15TTR
RC
Transmitter
e
Delay tDTR
–
0
–
–
–
–
0.8T
–
–
–
–
–
–
–
–
–
e
d
Hold time tHTR
Receiverf
Setup time tSR
Hold time tHR
–
–
–
–
–
–
–
–
–
–
0.2TR
0
–
–
–
–
f
f
a. All timing values are specified with respect to high and low threshold levels.
b. The system clock period T must be greater than TTR and T because both the transmitter and receiver must be able to handle
r
the data transfer rate.
c. The transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason t and t are specified
HC
LC
with respect to T.
d. The transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal. So
long as the minimum periods are greater than 0.35TR, any clock that meets the requirements can be used.
e. Because the delay (tDTR) and the maximum transmitter speed (defined by TTR) are related, a fast transmitter driven by a slow
clock edge can result in tDTR not exceeding t which means tHTR becomes zero or negative. Therefore, the transmitter has to
RC
guarantee that tHTR is greater than or equal to zero, provided the clock rise-time t is not more than t
, where t
is
RCmax
RC
RCmax
not less than 0.15TTR. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge
of the clock signal and T, always giving the receiver sufficient setup time.
f. The data setup and hold time must not be less than the specified receiver setup and hold time.
Broadcom Corporation
Page 102
FM I2S Timing
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
FM I2C-COMPATIBLE TIMING
I2C_DA
t
t
f
t
t
t
t
t
t
t
BUF
SU;DAT
LOW
f
r
HD;STA
SP
r
I2C_CK
t
t
SU;STA
t
HD;STA
SU;STO
t
t
HIGH
HD;DAT
P
S
S
Sr
Table 49: FM I2C-Compatible Interface Timing
Parameter
I2C_CK clock frequency
Symbol
Minimum
Maximum Unit
f
t
t
0
400
–
kHz
μs
I2C_CK
BUF
Bus-free times between a stop and start condition
1.3
0.6
Hold time (repeated) start condition. After this period, the first clock
pulse is generated.
–
μs
HD,STA
Low period of the I2C_CK clock
High period of the I2C_CK clock
Setup time for a repeater start condition
Data hold time
t
t
t
t
t
t
t
t
1.3
0.6
0.6
0
–
μs
μs
μs
μs
μs
ns
ns
μs
LOW
HIGH
SU,STA
HD,DAT
SU,DAT
r
–
–
0.9
–
Data setup time
–
a
a
Rise time of both I2C_DA and I2C_CK signals
Fall time of both I2C_DA and I2C_CK signals
Setup time for stop condition
20 + 0.1C
20 + 0.1C
0.6
300
300
–
b
r
b
SU,STO
a. C = Total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
b
SPROM TIMING
Table 50: SPROM Timing Characteristics
Signal Name
Period
Output Max Output Min Setup
Hold
SPROM_CLK
1.92 μs
–
–
–
–
SPROM_CLK falling edge to SPROM_DOUT
SPROM_CLK falling edge to SPROM_CS
SPROM_CLK rising edge to SPROM_DIN
–
–
–
0.5 μs
0.5 μs
–
0.3 μs
0.3 μs
–
–
–
–
–
0.5 μs
–0.3 μs
Broadcom Corporation
Document 4325-DS04-R
FM I2C-Compatible Timing Page 103
BCM4325
Preliminary Data Sheet
6/30/09
JTAG TIMING
Table 51: JTAG Timing Characteristics
Period
Signal Name
Output Max Output Min Setup
Hold
TCK
125 ns
–
–
–
–
TDI
–
–
–
20 ns
20 ns
–
0 ns
0 ns
–
TMS
–
–
–
TDO
–
100 ns
–
0 ns
–
JTAG_TRST
250 ns
–
–
SDIO TIMING
This section describes the SDIO timing in both default and high-speed modes.
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tIH
tISU
SDIO_DATA Input
SDIO_DATA Output
tODLY
tODLY
(max)
(min)
Figure 23: SDIO Bus Timing (Default Mode)
Broadcom Corporation
Page 104
JTAG Timing
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Table 52: SDIO Bus Timing a Parameters (Default Mode)
Parameter
Symbol
Min
Typical
Max
Unit
b
Clock: SDIO_CLK (All values are referred to min. VIH and max. VIL )
Frequency—Data Transfer Mode
Frequency—Identification Mode
Clock Low Time
fPP
0
–
–
–
–
–
–
25
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
0
10
10
–
Clock High Time
–
ns
Clock Rise time
10
10
ns
Clock Low Time
–
ns
Inputs: CMD, DATA (referenced to SDIO_CLK)
Input Setup Time
tISU
tIH
5
5
–
–
–
–
ns
ns
Input Hold Time
Outputs: CMD, DATA (referenced to SDIO_CLK)
Output Delay time—Data Transfer Mode
Output Delay time—Identification Mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
a. Timing is based on CL ≤ 40pF load on CMD and Data.
b. min (Vih) = 0.7*Vdd and max (Vil) = 0.2*Vdd
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
SDIO_DATA Input
SDIO_DATA Output
tODLY
tOH
Figure 24: SDIO Bus Timing (High-Speed Mode)
Broadcom Corporation
Document 4325-DS04-R
SDIO Timing Page 105
BCM4325
Preliminary Data Sheet
6/30/09
Table 53: SDIO Bus Timing a Parameters (High-Speed Mode)
Symbol Min Typical Max
Parameter
Unit
b
Clock: SDIO_CLK (all values are referred to min. VIH and max. VIL )
Frequency—Data Transfer Mode
Frequency—Identification Mode
Clock Low Time
fPP
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
kHz
ns
fOD
tWL
Clock High Time
tWH
tTLH
tTHL
–
ns
Clock Rise time
3
ns
Clock Low Time
3
ns
Inputs: CMD, DATA (referenced to SDIO_CLK)
Input Setup Time
tISU
tIH
6
2
–
–
–
–
ns
ns
Input Hold Time
Outputs: CMD, DATA (referenced to SDIO_CLK)
Output Delay time—Data Transfer Mode
Output Hold time
tODLY
tOH
–
–
–
–
14
–
ns
ns
pF
2.5
–
Total System Capacitance (each line)
CL
40
a. Timing is based on CL ≤ 40pF load on CMD and Data.
b. Minimum (Vih) = 0.7*Vdd and maximum (Vil) = 0.2*Vdd
Broadcom Corporation
Page 106
SDIO Timing
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 22: Power-Up Sequence and Timing
SDIO HOST TIMING REQUIREMENT
The SDIO host must wait a minimum of 150 ms before initiating access to the BCM4325 after the VDDC (1.25V DC supply
for core) ramps up and settles. The specifics of this requirement depend on the power supply topology being used. For
example, if the topology shown in Figure 5 on page 4 is being used, reset and host access timing depends on the CLDO and
CBUCK outputs and the VDDC’s bypass network. For an additional safety margin, a longer delay should be used.
RESET AND REGULATOR CONTROL SIGNAL SEQUENCING
The BCM4325 has four signals (see Table 54) that enable or disable the Bluetooth, WLAN, and internal regulator blocks,
allowing the host to control power consumption. This section contains detailed timing diagrams of these signals and the
required power-up sequences. These timing diagrams are provided to illustrate proper sequencing of the signals in various
operational states. The timing values indicated in the diagrams are the minimum requirements. Longer delays are also
acceptable.
Table 54: Control Signal Descriptions
Signal
Description
WL_REG_ON
This signal is used by the PMU (along with BT_REG_ON) to decide whether or not to power down
the internal BCM4325 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be
disabled. If WL_RST_N is low (regardless of BT_RST_N state), the WLAN core will be powered off.
BT_REG_ON
This signal is used by the PMU (along with WL_REG_ON) to decide whether or not to power down
the internal BCM4325 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be
disabled.
WL_RST_N
BT_RST_N
Low Asserting Reset for WLAN Core This pin must be driven high or low (not left floating).
Low asserting reset for Bluetooth core. This pin must be driven high or low (not left floating)
Note: WL_REG_ON and BT_REG_ON are OR gated together in the BCM4325.
Broadcom Corporation
Document 4325-DS04-R
Power-Up Sequence and Timing Page 107
BCM4325
Preliminary Data Sheet
6/30/09
SIGNAL AND POWER-UP SEQUENCE TIMING DIAGRAMS
Note: The timing diagrams presented in this section are not to scale and are for illustrative purposes only.
The timing diagrams show the signals going high at the same time (which is true when both REG signals are controlled by
a single host GPIO). However, if two independent host GPIOs are used (one for WL_REG_ON and one for BT_REG_ON),
only one signal has to be high in order to enable the BCM4325’s regulators. Additionally, the reset requirements for the
Bluetooth core also apply to the FM core. Therefore, if FM is to be used, the Bluetooth core must be enabled.
32.768 kHz Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 sleep clock
cycles
WL_REG_ON
BT_REG_ON
WL_REG_N
BT_RST_N
100 ms
Figure 25: Power-Up Timing for WL On and BT On
32.768 kHz Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 sleep clock
cycles
WL_REG_ON
BT_REG_ON
WL_RST_N
BT_RST_N
100 ms
100 ms
Figure 26: Power-Up Timing for WL On and BT Off
Broadcom Corporation
Page 108
Reset and Regulator Control Signal Sequencing
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
32.768 kHz Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 sleep clock
cycles
WL_REG_ON
BT_REG_ON
WL_RST_N
BT_RST_N
100 ms
Figure 27: Power-Up Timing for WL Off and BT On
32.768 kHz Sleep Clock
VBAT
VDDIO
WL_REG_ON
BT_REG_ON
WL_RST_N
BT_RST_N
Figure 28: Power-Up Timing for WL Off and BT Off (VDDC Provided by BCM4325)
Broadcom Corporation
Document 4325-DS04-R
Reset and Regulator Control Signal Sequencing Page 109
BCM4325
Preliminary Data Sheet
6/30/09
32.768 kHz Sleep Clock
VBAT
90% of VH
VDDIO
100 ms
WL_REG_ON
BT_REG_ON
WL_RST_N
BT_RST_N
100 ms
Figure 29: Power-Up Timing for WL Off and BT Off (VDDC Provided Externally)
32.768 kHz Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 sleep clock
cycles
WL_REG_ON and
WL_RST_N
BT_REG_ON and
BT_RST_N
100 ms
Note:
WL_REG_ON and WL_RST_N are tied together.
BT_REG_ON and BT_RST_N are tied together.
Figure 30: Power-Up Timing for WL On and BT On (REG_ON signals are connected to RST_N signals)
Broadcom Corporation
Page 110
Reset and Regulator Control Signal Sequencing
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
32.768 kHz Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 sleep clock
cycles
WL_REG_ON and
WL_RST_N
~ 2 sleep clock
cycles
BT_REG_ON
and BT_RST_N
100 ms
Note:
WL_REG_ON and WL_RST_N are tied together.
BT_REG_ON and BT_RST_N are tied together.
Figure 31: Power-Up Timing for WL Off and BT On (REG_ON signals are connected to RST_N signals)
32.768 KHz Sleep Clock
VBATT
90% of VH
VDDIO
~ 2 sleep clock
cycles
BT_REG_ON
WL_REG_ON and WL_RST_N
BT_RST_N
100 ms
Note:
WL_REG_ON and WL_RST_N are tied together.
BT_REG_ON and BT_RST_N are separated.
Figure 32: Power-Up Timing for WL ON and BT ON (WL REG_ON signal connected to WL_RST_N, BT separated)
Broadcom Corporation
Document 4325-DS04-R
Reset and Regulator Control Signal Sequencing Page 111
BCM4325
Preliminary Data Sheet
6/30/09
32.768 kHz Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 sleep clock
cycles
WL_REG_ON
BT_REG_ON
WL_RST_N
BT_RST_N
100 ms
Figure 33: Power-Up Timing for WL OFF and BT ON (WL REG_ON signal connected to WL_RST_N, BT separated)
32.768 kHz Sleep Clock
VBAT
90% of VH
VDDIO
~ 2 sleep clock
cycles
WL_REG_ON
BT_REG_ON
WL_RST_N
BT_RST_N
100 ms 100 ms
Figure 34: Power-Up Timing for WL ON and BT OFF (WL REG_ON signal connected to WL_RST_N, BT separated)
Broadcom Corporation
Page 112
Reset and Regulator Control Signal Sequencing
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 23: Package Information
PACKAGE THERMAL CHARACTERISTICS
Table 55: Thermal Characteristics (Values in Still Air) a
Characteristic
196-Ball FBGA Package
339-WLCSP Package
θJA (°C/W)
θJB (°C/W)
θJC (°C/W)
ΨJT (°C/W)
36.3
4.9
36.7
1.23
0.06
0.27
125
10.9
0.27
125
Maximum Junction Temperature T (°C)
j
a. No heat sink, TA = 70° C. This is an estimate based on a 2-layer PCB and P = 1.2W continuous dissipation.
JUNCTION TEMPERATURE ESTIMATION AND PSIJT VERSUS THETAJC
Package thermal characterization parameter PSI-J (Ψ ) yields a better estimation of actual junction temperature (T )
T
JT
J
versus using the junction-to-case thermal resistance parameter Theta-J (θ ). The reason for this is θ assumes that all
C
JC
JC
the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated
through the bottom and sides of the package. Ψ takes into account power dissipated through the top, bottom. and sides
JT
of the package. The equation for calculating the device junction temperature is as follows:
TJ = TT + P × ΨJT
Where:
•
•
•
•
T
T
= Junction temperature at steady-state condition (°C)
= Package case top center temperature at steady-state condition (°C)
= Device power dissipation (Watts)
J
T
P
Ψ
= Package thermal characteristics; no airflow (°C/W)
JT
ENVIRONMENTAL CHARACTERISTICS
For environmental characteristics data, see “Environmental Ratings” on page 76.
Broadcom Corporation
Document 4325-DS04-R
Package Information Page 113
BCM4325
Preliminary Data Sheet
6/30/09
MISCELLANEOUS CHARACTERISTICS
Table 56: Miscellaneous Characteristics
Characteristics
Value
Units
Conditions/Comments
Moisture Sensitivity Level (MSL)
Ball Metallurgy
3
–
–
–
–
–
–
–
–
–
SnAg1.0Cu0.5
E'lytic Ti/Cu/Ni
SnCu2.5
260
Under bump Metallurgy
With bump Metallurgy
o
FBGA peak reflow temperature
C
Broadcom Corporation
Page 114
Miscellaneous Characteristics
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 24: Mechanical Information
196-BALL FBGA PACKAGE
Figure 35: 196-Ball FBGA Mechanical Information
Broadcom Corporation
Document 4325-DS04-R
Mechanical Information Page 115
BCM4325
Preliminary Data Sheet
6/30/09
339-PIN WLCSP PACKAGE
Figure 36: 339-Pin WLCSP Mechanical Information
Broadcom Corporation
Page 116
339-Pin WLCSP Package
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Section 25: WLCSP Keepout Area
This section shows the PCB keepout areas of theBCM4325 WLCSP package; there should not be any metal on these layers.
Figure 37: WLAN Section Top Metal Keepout Area
Broadcom Corporation
Document 4325-DS04-R
WLCSP Keepout Area Page 117
BCM4325
Preliminary Data Sheet
6/30/09
Figure 38: WLAN Section Second Metal Keepout Area
Broadcom Corporation
Page 118
WLCSP Keepout Area
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Figure 39: BT and FM Keepout Area
Note: The shaded area in Figure 39 is enlarged in Figure 40 on page 119.
Figure 40: BT and FM first and Second Keepout Area Enlargement
Note: Figure 40 above is an enlargement of the BT and FM keepout area; see Figure 39 on page 119 to view the
entire layer.
Broadcom Corporation
Document 4325-DS04-R
WLCSP Keepout Area Page 119
BCM4325
Preliminary Data Sheet
6/30/09
Section 26: Ordering Information
Table 57: Ordering Information
Part Number
Package
Ambient Temperature
o
o
BCM4325GKFBG
Single-band 2.4 GHz WLAN, Bluetooth 3.0 + HS, 196-ball flip-chip FBGA –30 C to +85 C
(7.5 mm x 7.5 mm x 1.05 mm, 0.50 mm pitch)
o
o
BCM4325FKFBG
BCM4325GKWBG
BCM4325FKWBG
Single-band 2.4 GHz WLAN, Bluetooth 3.0 + HS, FM Rx, 196-ball flip-chip –30 C to +85 C
FBGA (7.5 mm x 7.5 mm x 1.05 mm, 0.50 mm pitch)
o
o
Single-band 2.4 GHz WLAN, Bluetooth 3.0 + HS, 339-pin WLCSP
(6.51 mm X 5.8 mm X 0.4 mm, 0.250 mm pitch)
–30 C to +85 C
o
o
Single-band 2.4 GHz WLAN, Bluetooth 3.0 + HS, FM Rx, 339-pin WLCSP –30 C to +85 C
(6.51 mm X 5.8 mm X 0.4 mm, 0.250 mm pitch)
Broadcom Corporation
Page 120
Ordering Information
Document 4325-DS04-R
Preliminary Data Sheet
6/30/09
BCM4325
Broadcom Corporation
Document 4325-DS04-R
Ordering Information Page 121
BCM4325
Preliminary Data Sheet
6/30/09
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
Phone: 949-926-5000
Fax: 949-926-5203
Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.
Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation
does not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
Document 4325-DS04-R
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