CY14B101Q1-LHXCT中文资料_数据手册_规格书

CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

1 Mbit (128K x 8) Serial SPI nvSRAM

■ Low Power Consumption

❐ Single 3V +20%, –10% operation

❐ Average V_CCcurrent of 10 mA at 40 MHz operation

Features

■ 1 Mbit Nonvolatile SRAM

❐ Internally organized as 128K x 8

■ Industry Standard Configurations

❐ Commercial and industrial temperatures

❐ CY14B101Q1 has identical pin configuration to industry stan-

dard 8-pin NV Memory

❐ 8-pin DFN and 16-pin SOIC Packages

❐ RoHS compliant

❐ STORE to QuantumTrap nonvolatile elements initiated auto-

matically on power down (AutoStore) or by user using HSB

pin (Hardware Store) or SPI instruction (Software Store)

❐ RECALL to SRAM initiated on power up (Power Up Recall)

or by SPI Instruction (Software RECALL)

❐ Automatic STORE on power down with a small capacitor

■ High Reliability

Functional Overview

❐ Infinite Read, Write, and RECALLl cycles

❐ 200,000 STORE cycles to QuantumTrap

❐ Data Retention: 20 Years

The

Cypress

CY14B101Q1/CY14B101Q2/CY14B101Q3

combines a 1 Mbit nonvolatile static RAM with a nonvolatile

element in each memory cell. The memory is organized as 128K

words of 8 bits each. The embedded nonvolatile elements incor-

porate the QuantumTrap technology, creating the world’s most

reliable nonvolatile memory. The SRAM provides infinite read

and write cycles, while the QuantumTrap cell provides highly

reliable nonvolatile storage of data. Data transfers from SRAM to

the nonvolatile elements (STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM from the nonvolatile memory (RECALL operation).

Both STORE and RECALL operations can also be triggered by

the user.

■ High Speed Serial Peripheral Interface (SPI)

❐ 40 MHz Clock rate

❐ Supports SPI Modes 0 (0,0) and 3 (1,1)

■ Write Protection

❐ Hardware Protection using Write Protect (WP) Pin

❐ Software Protection using Write Disable Instruction

❐ Software Block Protection for 1/4,1/2, or entire Array

V_CC

V_CAP

Logic Block Diagram

Quantum Trap

128K X 8

Power Control

CS

WP

SCK

Instruction decode

Write protect

Control logic

STORE/RECALL

Control

STORE

HSB

SRAM ARRAY

HOLD

RECALL

128K X 8

Instruction

register

D0-D7

A0-A16

Address

Decoder

Data I/O register

Status register

SO

SI

Cypress Semiconductor Corporation

Document #: 001-50091 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 02, 2009

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Pinouts

Figure 1. Pin Diagram - 8-Pin DFN^{[1, 3, 2]}

8

1

2

3

CS

SO

V

1

8

CS

SO

V

CY14B101Q1

CC

CY14B101Q2

CC

7

6

5

HOLD

SCK

SI

2

HOLD

SCK

SI

7

6

5

Top View

WP

3

4

V

CAP

GND

not to scale

GND

4

Figure 2. Pin Diagram - 16-Pin SOIC

16

15

14

13

12

V

NC

WP

1

2

3

CC

NC

V

CAP

CY14B101Q3

Top View

4

5

6

SO

SI

not to scale

11

10

SCK

HOLD

NC

7

8

CS

9

GND

HSB

Table 1. Pin Definitions

Pin Name

I/O Type

Description

CS

Input

Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low

power standby mode.

SCK

Input

Serial Clock. Runs at speeds up to max 40 MHz. All inputs are latched at the rising edge of this

clock. Outputs are driven at the falling edge of the clock.

SI

SO

Input

Output

Input

Serial Input. Pin for input of all SPI instructions and data.

Serial Output. Pin for output of data through SPI.

Write Protect. Implements hardware write protection in SPI.

HOLD Pin. Suspends Serial Operation.

WP

HOLD

HSB

Input

Input/Output

Hardware STORE Busy: A weak internal pull up keeps this pin pulled high. If not used, this pin is

left as No Connect.

Output: Indicates busy status of nvSRAM when LOW.

Input: Hardware STORE implemented by pulling this pin LOW externally.

V_CAP

Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the

SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It

must never be connected to GND.

NC

GND

V_CC

No Connect

No Connect: This pin is not connected to the die.

Power Supply Ground

Power Supply Power Supply (2.7 to 3.6V)

Notes

1. HSB pin is not available in 8 DFN packages.

2. CY14B101Q1 part does not have V pin and does not support AutoStore.

CAP

3. CY14B101Q2 part does not have WP pin

Document #: 001-50091 Rev. *B

Page 2 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

SRAM Write

Device Operation

All writes to nvSRAM are carried out on the SRAM and do not

use up any endurance cycles of the nonvolatile memory. This

enables user to perform infinite write operations. A Write cycle is

performed through the SPI WRITE instruction. The WRITE

instruction is issued through the SI pin of the nvSRAM and

consists of the WRITE opcode, three bytes of address, and one

byte of data. Write to nvSRAM is done at SPI bus speed with zero

cycle delay.

CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM

memory with a nonvolatile element in each memory cell. All the

reads and writes to nvSRAM happen to the SRAM which gives

nvSRAM the unique capability to handle infinite writes to the

memory. The data in SRAM is secured by a STORE sequence

which transfers the data in parallel to the nonvolatile Quantum

Trap cells. A small capacitor (V_CAP) is used to AutoStore the

SRAM data in nonvolatile cells when power goes down providing

power down data security. The Quantum Trap nonvolatile

elements built in the reliable SONOS technology make nvSRAM

the ideal choice for secure data storage.

The device allows burst mode writes to be performed through

SPI. This enables write operations on consecutive addresses

without issuing a new WRITE instruction. When the last address

in memory is reached, the address rolls over to 0x0000 and the

device continues to write.

The 1 Mbit memory array is organized as 128K words x 8 bits.

The memory can be accessed through a standard SPI interface

that enables very high clock speeds upto 40 MHz with zero cycle

delay read and write cycles. This device supports SPI modes 0

and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.

The SPI write cycle sequence is defined explicitly in the Memory

Access section of SPI Protocol Description.

The device is enabled using the Chip Select pin ( ) and

accessed through Serial Input (SI), Serial Output (SO), and

Serial Clock (SCK) pins.

SRAM Read

CS

A read cycle is performed at the SPI bus speed and the data is

read out with zero cycle delay after the READ instruction is

performed. The READ instruction is issued through the SI pin of

the nvSRAM and consists of the READ opcode and 3 bytes of

address. The data is read out on the SO pin.

This device provides the feature for hardware and software write

protection through WP pin and WRDI instruction respectively

along with mechanisms for block write protection (1/4, 1/2, or full

array) using BP0 and BP1 pins in the status register. Further, the

HOLD pin can be used to suspend any serial communication

without resetting the serial sequence.

This device allows burst mode reads to be performed through

SPI. This enables reads on consecutive addresses without

issuing a new READ instruction. When the last address in

memory is reached in burst mode read, the address rolls over to

0x0000 and the device continues to read.

CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard

SPI opcodes for memory access. In addition to the general SPI

instructions for read and write, it provides four special

instructions which enable access to four nvSRAM specific

functions: STORE, RECALL, AutoStore Disable (ASDISB), and

AutoStore Enable (ASENB).

The SPI read cycle sequence is defined explicitly in the Memory

Access section of SPI Protocol Description.

STORE Operation

The major benefit of nvSRAM SPI over serial EEPROMs is that

all reads and writes to nvSRAM are performed at the speed of

SPI bus with zero delay. Therefore, no wait time is required after

any of the memory accesses. The STORE and RECALL

operations need finite time to complete and all memory accesses

are inhibited during this time. While a STORE or RECALL

operation is in progress, the busy status of the device is indicated

by the Hardware STORE Busy (HSB) pin and also reflected on

the RDY bit of the Status Register.

STORE operation transfers the data from the SRAM to the

nonvolatile Quantum Trap cells. The device stores data to the

nonvolatile cells using one of three STORE operations:

AutoStore, activated on device power down; Software STORE,

activated by a STORE instruction in the SPI; Hardware STORE,

activated by the HSB. During the STORE cycle, an erase of the

previous nonvolatile data is first performed, followed by a

program of the nonvolatile elements. After a STORE cycle is

initiated, further input and output are disabled until the cycle is

completed.

The Device is available in three different pin configurations that

enable the user to choose a part which fits in best in their appli-

cation. The feature summary is given in Table 2.

The HSB signal or the RDY bit in the Status register can be

monitored by the system to detect if a STORE cycle is in

progress. The busy status of nvSRAM is indicated by HSB being

pulled LOW or RDY bit being set to ‘1’. To avoid unnecessary

nonvolatile STOREs, AutoStore and Hardware STORE opera-

tions are ignored unless at least one write operation has taken

place since the most recent STORE or RECALL cycle. Software

initiated STORE cycles are performed regardless of whether a

write operation has taken place.

Table 2. Feature Summary

Feature

WP

CY14B101Q1

CY14B101Q2

CY14B101Q3

Yes

No

Yes

No

Yes

V

CAP

HSB

No

AutoStore

No

Yes

Power Up

RECALL

Yes

Hardware

STORE

No

Yes

Software

STORE

Yes

Document #: 001-50091 Rev. *B

Page 3 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

The HSB pin also acts as an open drain driver that is internally

driven LOW to indicate a busy condition, when a STORE cycle

(initiated by any means) or Power up RECALL is in progress.

Upon completion of the STORE operation, the nvSRAM remains

disabled until the HSB pin returns HIGH. Leave the HSB pin

unconnected if not used.

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which

automatically stores the SRAM data to QuantumTrap during

power down. This Store mechanism is implemented using a

capacitor (V_CAP) and enables the device to safely STORE the

data in the nonvolatile memory when power goes down.

Note CY14B101Q1/CY14B101Q2 do not have HSB pin. RDY bit

of the SPI status register may be probed to determine the Ready

or Busy status of nvSRAM

During normal operation, the device draws current from V_CCto

charge the capacitor connected to the V_CAPpin. When the

voltage on the V_CCpin drops below V_SWITCHduring power down,

the device inhibits all memory accesses to nvSRAM and

automatically performs a conditional STORE operation using the

charge from the V_CAPcapacitor. The AutoStore operation is not

initiated if no write cycle has been performed since last RECALL.

Figure 3. AutoStore Mode

Vcc

0.1uF

Note If a capacitor is not connected to V_CAPpin, Autostore must

be disabled by issuing the AutoStore Disable instruction

specified in AutoStore Disable (ASDISB) on page 12. If

AutoStore is enabled without a capacitor on V_CAPpin, the device

will attempt an AutoStore operation without sufficient charge to

complete the Store. This may corrupt the data stored in nvSRAM

and Status register. In such case, WRSR instruction needs to be

issued to update the non-volatile bits BP0, BP1, WPEN to

resume normal functionality.

Vcc

CS

V_CAP

V_SS

During power down, the memory accesses are inhibited after the

voltage on V_CCpin drops below V_SWITCH. To avoid inadvertent

writes, it must be ensured that CS is not left floating prior to this

event. Therefore, during power down the device must be

deselected and CS must be allowed to follow V_CC

.

Figure 3 shows the proper connection of the storage capacitor

(V_CAP) for AutoStore operation. Refer to DC Electrical Charac-

RECALL Operation

A RECALL operation transfers the data stored in the nonvolatile

Quantum Trap elements to the SRAM. A RECALL may be

initiated in two ways: Hardware RECALL, initiated on power up;

and Software RECALL, initiated by a SPI RECALL instruction.

teristics on page 13 for the size of the V_CAP

.

Note CY14B101Q1 does not support AutoStore operation. The

user must perform Software STORE operation by using the SPI

STORE instruction to secure the data.

Internally, RECALL is a two-step procedure. First, the SRAM

data is cleared. Next, the nonvolatile information is transferred

into the SRAM cells. All memory accesses are inhibited while a

RECALL cycle is in progress. The RECALL operation does not

alter the data in the nonvolatile elements.

Software Store Operation

Software STORE enables the user to trigger a STORE operation

through a special SPI instruction. This operation is initiated

irrespective of whether a write has been performed since last nv

operation.

Hardware Recall (Power Up)

A STORE cycle takes t_STOREto complete, during which all the

memory accesses to nvSRAM are inhibited. The RDY bit of the

Status register or the HSB pin may be polled to find the Ready

or Busy status of the nvSRAM. After the t_STOREcycle time is

completed, the SRAM is activated again for read and write

operations.

During power up, when V_CCcrosses V_SWITCH, an automatic

RECALL sequence is initiated which transfers the content of

nonvolatile memory on to the SRAM. The data would previously

have been stored on the nonvolatile memory through a STORE

sequence.

A Power Up Recall cycle takes t_FAtime to complete and the

memory access is disabled during this time. HSB pin can be

used to detect the Ready status of the device. user

Hardware STORE and HSB pin Operation

The HSB pin in CY14B101Q3 is used to control and

acknowledge STORE operations. If no STORE or RECALL is in

progress, this pin can be used to request a Hardware STORE

cycle. When the HSB pin is driven LOW, nvSRAM conditionally

initiates a STORE operation after t_DELAYduration. An actual

STORE cycle starts only if a write to the SRAM has been

performed since the last STORE or RECALL cycle. Reads and

Writes to the memory are inhibited for t_STOREduration or as long

as HSB pin is LOW.

Software RECALL

Software RECALL enables the user to initiate a RECALL

operation to restore the content of nonvolatile memory on to the

SRAM. A Software RECALL is issued by using the SPI

instruction for RECALL.

A Software RECALL takes t_RECALLto complete during which all

memory accesses to nvSRAM are inhibited. The controller must

provide sufficient delay for the RECALL operation to complete

before issuing any memory access instructions.

Document #: 001-50091 Rev. *B

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Chip Select (CS)

Disabling and Enabling AutoStore

For selecting any slave device, the master needs to pull down

the corresponding CS pin. Any instruction can be issued to a

slave device only while the CS pin is LOW. When the device is

not selected, data through the SI pin is ignored and the serial

output pin (SO) remains in a high impedance state.

If the application does not require the AutoStore feature, it can

be disabled by using the ASDISB instruction. If this is done, the

nvSRAM does not perform a STORE operation at power down.

AutoStore can be re-enabled by using the ASENB instruction.

However, these operations are not nonvolatile and if the user

needs this setting to survive power cycle, a STORE operation

must be performed following Autostore Disable or Enable

operation.

Note A new instruction must begin with the falling edge of Chip

Select (CS). Therefore, only one opcode can be issued for each

active Chip Select cycle.

Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from

the factory. In CY14B101Q1, V_CAPpin is not present and

AutoStore option is not available. The Autostore Enable and

Disable instructions to CY14B101Q1 are ignored.

Serial Clock (SCK)

Serial clock is generated by the SPI master and the communi-

cation is synchronized with this clock after CS goes LOW.

CY14B101Q1/CY14B101Q2/CY14B101Q3 enables SPI modes

0 and 3 for data communication. In both these modes, the inputs

are latched by the slave device on the rising edge of SCK and

outputs are issued on the falling edge. Therefore, the first rising

edge of SCK signifies the arrival of first bit (MSB) of SPI

instruction on the SI pin. Further, all data inputs and outputs are

synchronized with SCK.

Note If AutoStore is disabled and V_CAPis not required, leave it

open. V_CAPpin must never be connected to GND. Power Up

Recall operation cannot be disabled in any case.

Serial Peripheral Interface

SPI Overview

The SPI is a four-pin interface with Chip Select (CS), Serial Input

(SI), Serial Output (SO) and Serial Clock (SCK) pins.

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides serial

access to nvSRAM through SPI interface. The SPI bus on this

device can run at speeds up to 40 MHz

Data Transmission - SI and SO

SPI data bus consists of two lines, SI and SO, for serial data

communication. The SI is also referred to as MOSI (Master Out

Slave In) and SO is referred to as MISO (Master In Slave Out).

The master issues instructions to the slave through the SI pin,

while the slave responds through the SO pin. Multiple slave

devices may share the SI and SO lines as described earlier.

The SPI is a synchronous serial interface which uses clock and

data pins for memory access and supports multiple devices on

the data bus. A device on SPI bus is activated using a chip select

pin.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

The relationship between chip select, clock, and data is dictated

by the SPI mode. This device supports SPI modes 0 and 3. In

both these modes, data is clocked into nvSRAM on rising edge

of SCK starting from the first rising edge after CS goes active.

The 1 Mbit serial nvSRAM requires a 3-byte address for any read

or write operation. However, since the actual address is only 17

bits, it implies that the first seven bits which are fed in are ignored

by the device. Although these seven bits are ‘don’t care’,

Cypress recommends that these bits are treated as 0s to enable

seamless transition to higher memory densities.

The SPI protocol is controlled by opcodes. These opcodes

specify the commands from the bus master to the slave device.

After CS is activated the first byte transferred from the bus

master is the opcode. Following the opcode, any addresses and

data are then transferred. The CS must go inactive after an

operation is complete and before a new opcode can be issued.

The commonly used terms used in SPI protocol are given below:

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

CY14B101Q1/CY14B101Q2/CY14B101Q3 uses the standard

opcodes for memory accesses. In addition to the memory

accesses, it provides additional opcodes for the nvSRAM

specific functions: STORE, RECALL, AutoStore Enable, and

AutoStore Disable. Refer to Table 3 on page 7 for details.

SPI Master

The SPI Master device controls the operations on a SPI bus. An

SPI bus may have only one master with one or more slave

devices. All the slaves share the same SPI bus lines and master

may select any of the slave devices using the Chip Select pin.

All the operations must be initiated by the master activating a

slave device by pulling the CS pin of the slave LOW. The master

also generates the Serial Clock (SCK) and all the data trans-

mission on SI and SO lines are synchronized with this clock.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin till the next

falling edge of CS and the SO pin remains tristated.

SPI Slave

SPI slave device is activated by the master through the Chip

Select line. A slave device gets the Serial Clock (SCK) as an

input from the SPI master and all the communication is synchro-

nized with this clock. SPI slave never initiates a communication

on the SPI bus and acts on the instruction from the master.

Status Register

CY14B101Q1/CY14B101Q2/CY14B101Q3 has an 8-bit status

register. The bits in the status register are used to configure the

SPI bus. These bits are described in Table 5 on page 8.

CY14B101Q1/CY14B101Q2/CY14B101Q3 operates as a SPI

slave and may share the SPI bus with other SPI slave devices.

Document #: 001-50091 Rev. *B

Page 5 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Figure 4. System Configuration Using SPI nvSRAM

S C K

M O SI

M IS O

SC K

S I

S O

SC K

SI

S O

uC ontroller

C Y 14B 101Q x

C S

H O LD

C S

H O LD

C S 1

H O LD 1

C S 2

H O LD 2

The two SPI modes are shown in Figure 5 and Figure 6. The

status of clock when the bus master is in Standby mode and not

transferring data is:

SPI Modes

CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a

microcontroller with its SPI peripheral running in either of the

following two modes:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

■ SPI Mode 0 (CPOL=0, CPHA=0)

■ SPI Mode 3 (CPOL=1, CPHA=1)

CPOL and CPHA bits must be set in the SPI controller for either

Mode 0 or Mode 3. The device detects the SPI mode from the

status of SCK pin when the device is selected by bringing the CS

pin LOW. If SCK pin is LOW when device is selected, SPI Mode

0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3.

For both these modes, input data is latched-in on the rising edge

of Serial Clock (SCK) starting from the first rising edge after CS

goes active. If the clock starts from a HIGH state (in mode 3), the

first rising edge, after the clock toggles, is considered. The output

data is available on the falling edge of Serial Clock (SCK).

Figure 6. SPI Mode 3

Figure 5. SPI Mode 0

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

SCK

SI

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

MSB

LSB

MSB

LSB

Document #: 001-50091 Rev. *B

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Active Power and Standby Power Modes

SPI Operating Features

When Chip Select (CS) is LOW, the device is selected, and is in

the Active Power mode. The device consumes I_CCcurrent, as

specified in DC Electrical Characteristics on page 13. When Chip

Select (CS) is HIGH, the device is deselected and the device

goes into the Standby Power mode if a STORE or RECALL cycle

is not in progress. If a STORE or RECALL cycle is in progress,

device goes into the Standby Power Mode after the STORE or

RECALL cycle is completed. In the Standby Power mode, the

Power Up

Power up is defined as the condition when the power supply is

turned on and V_CCcrosses Vswitch voltage. During this time, the

Chip Select (CS) must be allowed to follow the V_CCvoltage.

Therefore, CS must be connected to V_CCthrough a suitable pull

up resistor. As a built-in safety feature, Chip Select (CS) is both

edge sensitive and level sensitive. After power up, the device is

not selected until a falling edge is detected on Chip Select (CS).

This ensures that Chip Select (CS) must have been HIGH,

before going Low to start the first operation.

current drawn by the device drops to I_SB

.

SPI Functional Description

As described earlier, nvSRAM performs a Power Up Recall

operation after power up and therefore, all memory accesses are

disabled for t_RECALLduration after power up. The HSB pin can

be probed to check the ready or busy status of nvSRAM after

power up.

The CY14B101Q1/CY14B101Q2/CY14B101Q3 uses an 8-bit

instruction register. Instructions and their opcodes are listed in

Table 3. All instructions, addresses, and data are transferred with

the MSB first and start with a HIGH to LOW CS transition. There

are, in all, 12 SPI instructions which provide access to most of

the functions in nvSRAM. Further, the WP and HOLD pins

provide additional functionality driven through hardware.

Power On Reset

A Power On Reset (POR) circuit is included to prevent

inadvertent writes. At power up, the device does not respond to

any instruction until the V_CCreaches the Power On Reset

threshold voltage (V_SWITCH). After V_CCtransitions the POR

threshold, the device is internally reset and performs an Power

Up Recall operation. The device is in the following state after

POR:

Table 3. Instruction Set

Instruction

Category

Instruction

Name

Opcode

Operation

WREN

0000 0110 Set Write Enable

Latch

■ Deselected (after Power up, a falling edge is required on Chip

Select (CS) before any instructions are started).

WRDI

0000 0100

0000 0101

0000 0001

Reset Write

Enable Latch

Status Register

Control Instruc-

tions

RDSR

WRSR

READ

WRITE

Read Status

Register

■ Standby Power mode

■ Not in the Hold Condition

Write Status

Register

■ Status register state:

❐ Write Enable (WEN) bit is reset to 0.

❐ WPEN, BP1, BP0 unchanged from previous power down

0000 0011 Read Data From

Memory Array

SRAM

Read/Write

Instructions

The WPEN, BP1, and BP0 bits of the Status Register are nonvol-

atile bits and remain unchanged from the previous power down.

0000 0010

Write Data To

Memory Array

Before selecting and issuing instructions to the memory, a valid

and stable V_CCvoltage must be applied. This voltage must

remain valid until the end of the transmission of the instruction.

STORE

0011 1100 Software STORE

RECALL

0110 0000

Software

RECALL

Special NV

Instructions

Power Down

ASENB

ASDISB

0101 1001 AutoStore Enable

0001 1001 AutoStore Disable

At power down (continuous decay of V_CC), when V_CCdrops from

the normal operating voltage and below the V_SWITCHthreshold

voltage, the device stops responding to any instruction sent to it.

If a write cycle is in progress during power down, it is allowed

Reserved

- Reserved - 0001 1110

Reserved for

Internal use

t_DELAYtime to complete after Vcc transitions below V_SWITCH

,

after which all memory accesses are inhibited and a conditional

AutoStore operation is performed (AutoStore is not performed if

no writes have happened since last RECALL cycle). This feature

prevents inadvertent writes to nvSRAM from happening during

power down.

The SPI instructions are divided based on their functionality in

the following types:

❐ Status Register Access: WRSR and RDSR instructions

❐ Write Protection Functions: WREN and WRDI instructions

along with WP pin and WEN, BP0, and BP1 bits

❐ SRAM memory Access: READ and WRITE instructions

❐ nvSRAM special instructions: STORE, RECALL, ASENB,

and ASDISB

However, to completely avoid the possibility of inadvertent writes

during power down, ensure that the device is deselected and is

in Standby Power Mode, and the Chip Select (CS) follows the

voltage applied on V_CC

.

Document #: 001-50091 Rev. *B

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Status Register

The status register bits are listed in Table 3. The status register consists of Ready bit (RDY) and data protection bits BP1, BP0, WEN,

and WPEN. The RDY bit can be polled to check the Ready or Busy status while a nvSRAM STORE cycle is in progress. The status

register can be modified by WRSR instruction and read by RDSR instruction. However, only WPEN, BP1, and BP0 bits of the Status

Register can be modified by using WRSR instruction. WRSR instruction has no effect on WEN and RDY bits. The default value shipped

from the factory for BP1, BP2 and WPEN bits is ‘0’.

Table 4. Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WPEN (0)

X

BP1 (0)

BP0 (0)

WEN

RDY

Table 5. Status Register Bit Definition

Bit

Definition

Description

Bit 0 (RDY)

Ready

Read Only bit indicates the ready status of device to perform a memory access. This bit is

set to “1” by the device while a STORE or Software RECALL cycle is in progress.

Bit 1 (WEN)

Write Enable

WEN indicates if the device is write-enabled. Setting WEN = '1' enables writes and setting

WEN = '0' disables all write operations

Bit 2 (BP0)

Bit 3 (BP1)

Block Protect bit ‘0’

Block Protect bit ‘1’

Used for block protection. For details see Table 6 on page 9.

Bit 7 (WPEN) Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 7 on page 10.

WRSR instruction is a write instruction and needs writes to be

enabled (WEN bit set to ‘1’) using the WREN instruction before

it is issued. The instruction is issued after the falling edge of CS

using the opcode for WRSR followed by 8 bits of data to be

stored in the Status Register. Since, only bits 2, 3, and 7 can be

modified by WRSR instruction, it is recommended to leave the

other bits as ‘0’ while writing to the Status Register

Read Status Register (RDSR) Instruction

The Read Status Register instruction provides access to the

status register. This instruction is used to probe the Write Enable

Status of the device or the Ready status of the device. RDY bit

is set by the device to 1 whenever a STORE cycle is in progress.

The Block Protection and WPEN bits indicate the extent of

protection employed.

Note In CY14B101Q1/CY14B101Q2/CY14B101Q3, the values

written to Status Register are saved to nonvolatile memory only

after a STORE operation. If AutoStore is disabled (or while using

CY14B101Q1), any modifications to the Status Register must be

secured by using a Software STORE operation

This instruction is issued after the falling edge of CS using the

opcode for RDSR.

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to the Status

register. However, this instruction cannot be used to modify bit 0

and bit 1 (WEN and RDY). The BP0 and BP1 bits can be used

to select one of four levels of block protection. Further, WPEN bit

can be set to ‘1’ to enable the use of Write Protect (WP) pin.

Note CY14B101Q2 does not have WP pin. Any modification to

bit 7 of the Status register has no effect on the functionality of

CY14B101Q2.

Figure 7. Read Status Register (RDSR) Instruction Timing

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

0

1

0

1

0

MSB

LSB

HI-Z

SO

D4

D2

D7 D6 D5

MSB

D3

D1 D0

LSB

Data

Document #: 001-50091 Rev. *B

Page 8 of 22

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CY14B101Q2

CY14B101Q3

PRELIMINARY

Figure 8. Write Status Register (WRSR) Instruction Timing

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

Data in

Opcode

D2

SI

1

D7

MSB

0

D3

0

LSB

HI-Z

SO

Write Disable (WRDI) Instruction

Write Protection and Block Protection

Write Disable instruction disables the write by clearing the WEN

bit to ‘0’ in order to protect the device against inadvertent writes.

This instruction is issued following falling edge of CS followed by

opcode for WRDI instruction. The WEN bit is cleared on the

rising edge of CS following a WRDI instruction.

CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features

for both software and hardware write protection using WRDI

instruction and WP. Additionally, this device also provides block

protection mechanism through BP0 and BP1 pins of the Status

Register.

Figure 10. WRDI Instruction

The write enable and disable status of the device is indicated by

WEN bit of the status register. The write instructions (WRSR and

WRITE) and nvSRAM special instruction (STORE, RECALL,

ASENB, and ASDISB) need the write to be enabled (WEN bit =

1) before they can be issued.

CS

0

1

2

3

4

5

6

7

SCK

SI

Write Enable (WREN) Instruction

On power up, the device is always in the write disable state. The

following WRITE, WRSR, or nvSRAM special instruction must

therefore be preceded by a Write Enable instruction. If the device

is not write enabled (WEN = ‘0’), it ignores the write instructions

and returns to the standby state when CS is brought HIGH. A

new CS falling edge is required to re-initiate serial communi-

cation. The instruction is issued following the falling edge of CS.

When this instruction is used, the WEN bit of status register is

set to ‘1’. WEN bit defaults to ‘0’ on power up.

0

1

0

Hi-Z

SO

Block Protection

Block protection is provided using the BP0 and BP1 pins of the

Status register. These bits can be set using WRSR instruction

and probed using the RDSR instruction. The nvSRAM is divided

into four array segments. One-quarter, one-half, or all of the

memory segments can be protected. Any data within the

protected segment is read only. Table 6 shows the function of

Block Protect bits.

Note After completion of a write instruction (WRSR or WRITE)

or nvSRAM special instruction (STORE, RECALL, ASENB, and

ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to

provide protection from any inadvertent writes. Therefore,

WREN instruction needs to be used before a new write

instruction is issued.

Table 6. Block Write Protect Bits

Figure 9. WREN Instruction

StatusRegister

Bits

CS

Level

Array Addresses Protected

0

1

2

3

4

5

6

7

BP1

BP0

SCK

SI

0

1

0

1

0

1

None

1 (1/4)

2 (1/2)

3 (All)

0x18000-0x1FFFF

0x10000-0x1FFFF

0x00000-0x1FFFF

0

1

0

Hi-Z

SO

Document #: 001-50091 Rev. *B

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CY14B101Q2

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PRELIMINARY

followed for a read operation: After the CS line is pulled LOW to

select a device, the read opcode is transmitted through the SI

line followed by three bytes of address. The Most Significant

address byte contains A16 in bit 0 and other bits as ‘don’t cares’.

Address bits A15 to A0 are sent in the following two address

bytes. After the last address bit is transmitted on the SI pin, the

data (D7-D0) at the specific address is shifted out on the SO line

on the falling edge of SCK. Any other data on SI line after the last

address bit is ignored.

Write Protect (WP) Pin

The write protect pin (WP) is used to provide hardware write

protection. WP pin enables all normal read and write operations

when held HIGH. When the WP pin is brought LOW and WPEN

bit is “1”, all write operations to the status register are inhibited.

The hardware write protection function is blocked when the

WPEN bit is “0”. This enables the user to install the device in a

system with the WP pin tied to ground, and still write to the status

register.

CY14B101Q1/CY14B101Q2/CY14B101Q3 allows reads to be

performed in bursts through SPI which can be used to read

consecutive addresses without issuing a new READ instruction.

If only one byte is to be read, the CS line must be driven HIGH

after one byte of data comes out. However, the read sequence

may be continued by holding the CS line LOW and the address

is automatically incremented and data continues to shift out on

SO pin. When the last data memory address (0x1FFFF) is

reached, the address rolls over to 0x0000 and the device

continues to read.

WP pin can be used along with WPEN and Block Protect bits

(BP1 and BP0) of the status register to inhibit writes to memory.

When WP pin is LOW and WPEN is set to “1”, any modifications

to status register are disabled. Therefore, the memory is

protected by setting the BP0 and BP1 bits and the WP pin inhibits

any modification of the status register bits, providing hardware

write protection.

Note WP going LOW when CS is still LOW has no effect on any

of the ongoing write operations to the status register.

Note CY14B101Q2 does not have WP pin and therefore does

not provide hardware write protection.

Write Sequence (WRITE)

The write operations on this device are performed through the

Serial Input (SI) pin. To perform a write operation, if the device is

write disabled, then the device must first be write enabled

through the WREN instruction. When the writes are enabled

(WEN = ‘1’), WRITE instruction is issued after the falling edge of

CS. A WRITE instruction constitutes transmitting the WRITE

opcode on SI line followed by 3 bytes address sequence and the

data (D7-D0) which is to be written. The Most Significant address

byte contains A16 in bit 0 with other bits being ‘don’t cares’.

Address bits A15 to A0 are sent in the following two address

bytes.

Table 7 summarizes all the protection features of this device

Table 7. Write Protection Operation

Protected Unprotected

Status

WPEN WP WEN

Blocks

Protected

Writable

Register

X

0

1

X

0

1

Protected

Writable

Protected

Writable

X

LOW

HIGH

CY14B101Q1/CY14B101Q2/CY14B101Q3 enables writes to be

performed in bursts through SPI which can be used to write

consecutive addresses without issuing a new WRITE instruction.

If only one byte is to be written, the CS line must be driven HIGH

after the D0 (LSB of data) is transmitted. However, if more bytes

are to be written, CS line must be held LOW and address is

incremented automatically. The following bytes on the SI line are

treated as data bytes and written in the successive addresses.

When the last data memory address (0x1FFFF) is reached, the

address rolls over to 0x0000 and the device continues to write.

The WEN bit is reset to “0” on completion of a WRITE sequence.

Memory Access

All memory accesses are done using the READ and WRITE

instructions. These instructions cannot be used while a STORE

or RECALL cycle is in progress. A STORE cycle in progress is

indicated by the RDY bit of the status register and the HSB pin.

Read Sequence (READ)

The read operations on this device are performed by giving the

instruction on Serial Input pin (SI) and reading the output on

Serial Output (SO) pin. The following sequence needs to be

Figure 11. Read Instruction Timing

CS

0

1

0

1

2

3

4

5

6

7

2

3

4

5

6

7

20 21 22 23

0

1

2

3

4

5

6

7

SCK

Op-Code

17-bit Address

0 A16

SI

0

1

A3

A2 A1 A0

0

MSB

LSB

SO

D7 D6 D5 D4 D3

D2

D1

D0

MSB

LSB

Data

Document #: 001-50091 Rev. *B

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CY14B101Q2

CY14B101Q3

PRELIMINARY

Figure 12. Burst Mode Read Instruction Timing

CS

20 21 22 23

0

1

0

1

2

3

4

5

6

7

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

Op-Code

17-bit Address

A16

1

0

A3 A2 A1 A0

SI

0

MSB

LSB

Data Byte N

Data Byte 1

SO

D7 D6 D5 D4

D0

D3 D2

D7 D0 D7 D6 D5 D4

D1

D3 D2 D1 D0

MSB

LSB

Figure 13. Write Instruction Timing

CS

0

1

0

1

2

3

4

5

7

2

3

4

5

6

7

20 21 22 23

0

1

2

3

4

5

6

7

6

SCK

Op-Code

17-bit Address

D4

D2

D1 D0

SI

0

D7 D6 D5

LSB

MSB

D3

0

1

0

A16

A3

A2 A1 A0

0

MSB

LSB

Data

HI-Z

SO

Figure 14. Burst Mode Write Instruction Timing

CS

22 23

20 21

0

1

0

1

2

3

4

5

6

7

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

Data Byte N

Data Byte 1

Op-Code

17-bit Address

A16

D7 D6 D5 D4

MSB

D7 D0 D7 D6 D5 D4

D3 D2

1

0

A3 A2 A1 A0

LSB

D1 D0

0

SI

MSB

LSB

HI-Z

SO

Table 8. nvSRAM Special Instructions

nvSRAM Special Instructions

Function Name

STORE

Opcode

0011 1100

0110 0000

Operation

Software STORE

Software RECALL

CY14B101Q1/CY14B101Q2/CY14B101Q3

provides

four

special instructions which enables access to four nvSRAM

specific functions: STORE, RECALL, ASDISB, and ASENB.

Table 8 lists these instructions.

RECALL

ASENB

0101 1001 AutoStore Enable

0001 1001 AutoStore Disable

Software STORE

ASDISB

When a STORE instruction is executed, nvSRAM performs a

Software STORE operation. The STORE operation is issued

irrespective of whether a write has taken place since last STORE

or RECALL operation.

To issue this instruction, the device must be write enabled (WEN

bit = ‘1’). The instruction is performed by transmitting the STORE

opcode on the SI pin following the falling edge of CS. The WEN

bit is cleared on the positive edge of CS following the STORE

instruction.

Document #: 001-50091 Rev. *B

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CY14B101Q2

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PRELIMINARY

AutoStore Enable (ASENB)

Figure 15. Software STORE Operation

The AutoStore Enable instruction enables the AutoStore on

CY14B101Q1. This setting is not nonvolatile and needs to be

followed by a STORE sequence to survive the power cycle.

CS

0

1

2

3

4

5

6

7

To issue this instruction, the device must be write enabled (WEN

= ‘1’). The instruction is performed by transmitting the ASENB

opcode on the SI pin following the falling edge of CS. The WEN

bit is cleared on the positive edge of CS following the ASENB

instruction.

SCK

SI

0

1

0

Hi-Z

Note If ASDISB and ASENB instructions are executed in

CY14B101Q1, the device is busy for the duration of software

sequence processing time (t_SS). However, ASDISB and ASENB

instructions have no effect on CY14B101Q1 as AutoStore is

internally disabled.

SO

Software RECALL

When a RECALL instruction is executed, nvSRAM performs a

Software RECALL operation. To issue this instruction, the device

must be write enabled (WEN = ‘1’).

Figure 18. AutoStore Enable Operation

CS

The instruction is performed by transmitting the RECALL opcode

on the SI pin following the falling edge of CS. The WEN bit is

cleared on the positive edge of CS following the RECALL

instruction.

0

1

2

3

4

5

6

7

SCK

SI

Figure 16. Software RECALL Operation

0

1

0

1

0

1

CS

Hi-Z

SO

0

1

2

3

4

5

6

7

SCK

SI

HOLD Pin Operation

0

1

0

The HOLD pin is used to pause the serial communication. When

the device is selected and a serial sequence is underway, HOLD

is used to pause the serial communication with the master device

without resetting the ongoing serial sequence. To pause, the

HOLD pin must be brought LOW when the SCK pin is LOW. To

resume serial communication, the HOLD pin must be brought

HIGH when the SCK pin is LOW (SCK may toggle during HOLD).

While the device serial communication is paused, inputs to the

SI pin are ignored and the SO pin is in the high impedance state.

Hi-Z

SO

AutoStore Disable (ASDISB)

AutoStore is enabled by default in CY14B101Q2/CY14B101Q3.

The ASDISB instruction disables the AutoStore. This setting is

not nonvolatile and needs to be followed by a STORE sequence

to survive the power cycle.

This pin can be used by the master with the CS pin to pause the

serial communication by bringing the pin HOLD LOW and

deselecting an SPI slave to establish communication with

another slave device, without the serial communication being

reset. The communication may be resumed at a later point by

selecting the device and setting the HOLD pin HIGH.

To issue this instruction, the device must be write enabled (WEN

= ‘1’). The instruction is performed by transmitting the ASDISB

opcode on the SI pin following the falling edge of CS. The WEN

bit is cleared on the positive edge of CS following the ASDISB

instruction.

Figure 19. HOLD Operation

Figure 17. AutoStore Disable Operation

CS

0

1

2

3

4

5

6

7

SCK

SI

HOLD

SO

0

1

0

1

Hi-Z

SO

Document #: 001-50091 Rev. *B

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CY14B101Q2

CY14B101Q3

PRELIMINARY

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Package Power Dissipation

Capability (T_A= 25°C) ................................................... 1.0W

Storage Temperature ................................. –65°C to +150°C

Maximum Accumulated Storage Time

Surface Mount Lead Soldering

Temperature (3 Seconds).......................................... +260°C

DC Output Current (1 output at a time, 1s duration).....15 mA

At 150°C Ambient Temperature........................ 1000h

At 85°C Ambient Temperature..................... 20 Years

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Ambient Temperature with

Power Applied ............................................ –55°C to +150°C

Latch up Current.................................................... > 200 mA

Table 9. Operating Range

Supply Voltage on V_CCRelative to GND ........–0.5V to +4.1V

DC Voltage Applied to Outputs

in High-Z State.......................................–0.5V to V_CC+ 0.5V

Range

Commercial

Industrial

Ambient Temperature

0°C to +70°C

V_CC

2.7V to 3.6V

Input Voltage..........................................–0.5V to V_CC+ 0.5V

–40°C to +85°C

Transient Voltage (<20 ns) on

Any Pin to Ground Potential ..................–2.0V to V_CC+ 2.0V

DC Electrical Characteristics

Over the Operating Range (V_CC= 2.7V to 3.6V)

Parameter

V_CC

Description

Test Conditions

Min

Typ^[4]

3.0

Max

3.6

10

Unit

V

Power Supply Voltage

2.7

I_CC1

Average V_ccCurrent At f_SCK= 40 MHz.

mA

Values obtained without output loads (I_OUT= 0 mA)

Average V_CCCurrent All Inputs Don’t Care, V_CC= Max.

during STORE Average current for duration t_STORE

AverageV_CAPCurrent All Inputs Don’t Care, V_CC= Max.

I_CC2

I_CC4

10

5

mA

during AutoStore

Cycle

Average current for duration t_STORE

I_SB

V_CCStandby Current CS > (V_CC– 0.2V). V_IN< 0.2V or > (V_CC– 0.2V).

Standby current level after nonvolatile cycle is complete.

Inputs are static. f = 0 MHz.

5

mA

[5]

InputLeakageCurrent V_CC= Max, V_SS< V_IN< V_CC

(except HSB)

–1

–100

–1

+1

µA

I_IX

InputLeakageCurrent V_CC= Max, V_SS< V_IN< V_CC

(for HSB)

I_OZ

Off State Output

Leakage Current

V_CC= Max, V_SS< V_OUT< V_CC

V_IH

V_IL

Input HIGH Voltage

Input LOW Voltage

2.0

V_SS– 0.5

2.4

V_CC+ 0.5

0.8

V

V_OH

V_OL

Output HIGH Voltage I_OUT= –2 mA

Output LOW Voltage I_OUT= 4 mA

V

0.4

V

Storage Capacitor

Between V_CAPpin and V_SS, 5V Rated

61

68

180

µF

V_CAP

Notes

4. Typical values are at 25°C, V = V (Typ) . Not 100% tested.

CC

5. The HSB pin has I

= -2 uA for V of 2.4V when both active high and LOW drivers are disabled. When they are enabled standard V and V are valid. This

OUT

O

H

O

H

O

L

parameter is characterized but not tested.

Document #: 001-50091 Rev. *B

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CY14B101Q2

CY14B101Q3

PRELIMINARY

Data Retention and Endurance

Parameter

Description

Min

Unit

Years

K

DATA_R

NV_C

Data Retention

20

Nonvolatile STORE Operations

200

Capacitance

Parameter^[6]

Description

Test Conditions

T_A= 25°C, f = 1MHz,

_CC= V_CC(Typ)

Max

6

Unit

pF

C_IN

Input Capacitance

V

C_OUT

Output Pin Capacitance

8

pF

Thermal Resistance

Parameter ^[6]

Description

Test Conditions

16-SOIC

8-DFN

Unit

Θ_JA

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA / JESD51.

TBD

°C/W

Θ_JC

Thermal Resistance

(Junction to Case)

TBD

°C/W

Figure 20. AC Test Loads and Waveforms

577Ω

R1

577Ω

R1

3.0V

OUTPUT

3.0V

OUTPUT

R2

789Ω

R2

789Ω

5 pF

30 pF

AC Test Conditions

Input Pulse Levels.................................................... 0V to 3V

Input Rise and Fall Times (10% - 90%) ....................... <3 ns

Input and Output Timing Reference Levels.....................1.5V

Note

6. These parameters are guaranteed by design and are not tested.

Document #: 001-50091 Rev. *B

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CY14B101Q2

CY14B101Q3

PRELIMINARY

AC Switching Characteristics

40MHz

Cypress

Parameter

Alt.

Parameter

Description

Unit

Min

Max

f_SCK

t_WL

t_WH

t_CE

t_CES

t_CEH

t_SU

t_H

Clock Frequency, SCK

40

MHz

ns

t_CL

Clock Pulse Width Low

Clock Pulse Width High

CS High Time

11

20

10

5

t_CH

t_CS

t_CSS

t_CSH

t_SD

CS Setup Time

CS Hold Time

Data In Setup Time

Data In Hold Time

HOLD Hold Time

HOLD Setup Time

Output Valid

t_HD

5

t_HH

t_HD

t_CD

t_V

5

t_SH

5

t_CO

9

t_HHZ

t_HLZ

t_OH

t_HZ

t_LZ

t_HO

t_DIS

HOLD to Output High Z

HOLD to Output Low Z

Output Hold Time

Output Disable Time

15

0

t_HZCS

25

Figure 21. Synchronous Data Timing (Mode 0)

t

CS

t

CSS

t

CH

CL

CSH

SCK

SI

t

HD

SD

VALID IN

t

CO

HZCS

OH

HI-Z

SO

Figure 22. HOLD Timing

CS

SCK

t

HH

t

SH

HOLD

SO

t

HLZ

HHZ

Document #: 001-50091 Rev. *B

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CY14B101Q2

CY14B101Q3

PRELIMINARY

AutoStore or Power Up RECALL

CY14B101Q1/CY14B101Q2/

CY14B101Q3

Parameters

Description

Unit

Min

Max

[7]

Power Up RECALL Duration

STORE Cycle Duration

20

8

ms

ns

t_FA

[8]

[9]

t_STORE

t_DELAY

Time Allowed to Complete SRAM Cycle

25

V_SWITCH

Low Voltage Trigger Level

VCC Rise Time

2.65

V

[6]

150

μs

t_VCCRISE

[6]

HSB Output Disable Voltage

HSB To Output Active Time

HSB High Active Time

1.9

5

V

V_HDIS

[6]

μs

ns

t_LZHSB

[6]

500

t_HHHD

Switching Waveforms

Figure 23. AutoStore or Power Up RECALL^[10]

V_CC

V_SWITCH

V_HDIS

8

V_VCCRISE

t_STORE

11

Note

t_HHHD

HSB OUT

AutoStore

t_DELAY

t_LZHSB

t_DELAY

POWER-

UP

RECALL

t_FA

Read & Write

Inhibited

(RWI)

Read & Write

POWER-UP

RECALL

BROWN

OUT

AutoStore

POWER

DOWN

AutoStore

POWER-UP

RECALL

Notes

7.

8. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware Store is not initiated

9. On a Hardware STORE, Software Store / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t

t

starts from the time V rises above V

CC SWITCH.

FA

.

DELAY

10. Read and Write cycles are ignored during STORE, RECALL, and while V is below V

CC

SWITCH.

11. HSB pin is driven high to V only by internal 100kOhm resistor, HSB driver is disabled.

CC

Document #: 001-50091 Rev. *B

Page 16 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Software Controlled STORE and RECALL Cycles

CY14B101Q1/CY14B101Q2/

CY14B101Q3

Parameter

Description

Unit

Min Max

t_RECALL

RECALL Duration

Soft Sequence Processing Time

200

100

μs

[12, 13]

t_SS

Switching Waveforms

Figure 24. Software STORE Cycle^[12]

CS

0

1

2

3

4

5

6

7

SCK

SI

0

1

0

t

STORE

Hi-Z

RWI

RDY

Figure 25. Software RECALL Cycle^[12]

CS

0

1

2

1

3

4

5

6

7

SCK

SI

0

t

RECALL

Hi-Z

RWI

RDY

Notes

12. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

13. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-50091 Rev. *B

Page 17 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Hardware STORE Cycle

CY14B101Q3

Parameter

Description

Unit

Min

Max

t_DHSB

t_PHSB

HSB To Output Active Time when write latch not set

Hardware STORE Pulse Width

25

ns

15

Switching Waveforms

Figure 26. Hardware STORE Cycle^[8]

Write Latch set

t

PHSB

HSB (IN)

t

STORE

t

HHHD

DELAY

HSB (OUT)

SO

t

LZHSB

RWI

Write Latch not set

t

PHSB

HSB (IN)

HSB pin is driven high to V

only by Internal

CC

100K: resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

HSB (OUT)

RWI

t

DELAY

DHSB

Document #: 001-50091 Rev. *B

Page 18 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Part Numbering Nomenclature

CY 14 B 101 Q 1-SF X C T

Option:

T - Tape & Reel

Blank - Std.

Temperature:

C - Commercial (0 to 70

°

C)

I - Industrial (-40 to 85

°C)

Pb-Free

Package:

SF - 16 SOIC

LH - 8 DFN

1 - 8 DFN (with WP)

2 - 8 DFN (With V_CAP

3 - 16 SOIC

)

Q - Serial SPI nvSRAM

Density:

101 - 1 Mb

Voltage:

B - 3.0V

nvSRAM

14 - Auto Store + Software STORE + Hardware STORE

Cypress

Ordering Information

Package

Diagram

Operating

Range

Ordering Code

Package Type

CY14B101Q1-LHXIT

CY14B101Q1-LHXI

CY14B101Q1-LHXCT

CY14B101Q1-LHXC

CY14B101Q2-LHXIT

CY14B101Q2-LHXI

CY14B101Q2-LHXCT

CY14B101Q2-LHXC

CY14B101Q3-SFXIT

CY14B101Q3-SFXI

CY14B101Q3-SFXCT

CY14B101Q3-SFXC

001-50671

51-85022

8 DFN (with WP)

Industrial

Commercial

Industrial

8 DFN (with WP)

8 DFN (with V_CAP

16 SOIC

)

Commercial

Industrial

16 SOIC

Commercial

16 SOIC

All the above parts are Pb - free. The above table contains advance information. Contact your local Cypress sales representative for availability of these parts.

Document #: 001-50091 Rev. *B

Page 19 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Package Diagrams

Figure 27. 8-Pin (196 mil) DFN Package (001-50671)

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS

2. PACKAGE WEIGHT: TBD

3. BASED ON REF JEDEC # MO-240 EXCEPT DIMENSIONS (L) and (b)

001-50671 *A

Document #: 001-50091 Rev. *B

Page 20 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Package Diagrams (continued)

Figure 28. 16-Pin (300 mil) SOIC (51-85022)

51-85022 *B

Document #: 001-50091 Rev. *B

Page 21 of 22

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CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

Document History Page

Document Title: CY14B101Q1/CY14B101Q2/CY14B101Q3 1 MBit (128K x 8) Serial SPI nvSRAM

Document Number: 001-50091

Orig. of

Change

Submission

Date

REV.

ECN NO.

Description of Change

**

2607408

GSIN/

GVCH/AESA

12/19/08

New Datasheet

*A

2654487 GVCH/PYRS 02/04/2009 Moved from Advance information to Preliminary

Changed part number from CY14B101QxA to CY14B101Qx

Updated pin description of V_CAPpin

Updated Device operation and SPI peripheral interface description

Added Factory setting values for BP1, BP2 and WPEN bits

Updated Real Time Clock operation description

Changed I_CC2from 5mA to 10mA

*B

2733293 GVCH/AESA 07/08/2009 Corrected typo error in the Document History Page (Description of change)

Corrected Typo error of footnote 2 and 3

Updated AtoStore operation description

Updated test condition of I_CC1and I_SBparameter

Updated V_HDISparameter description

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at cypress.com/sales.

Products

PSoC

PSoC Solutions

General

psoc.cypress.com

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wireless.cypress.com

memory.cypress.com

image.cypress.com

psoc.cypress.com/solutions

psoc.cypress.com/low-power

psoc.cypress.com/precision-analog

psoc.cypress.com/lcd-drive

psoc.cypress.com/can

Clocks & Buffers

Wireless

Low Power/Low Voltage

Precision Analog

LCD Drive

Memories

Image Sensors

CAN 2.0b

USB

psoc.cypress.com/usb

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 001-50091 Rev. *B

Revised July 02, 2009

Page 22 of 22

All products and company names mentioned in this document are the trademarks of their respective holders.

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是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	DFN	包装说明：	HVSON, SOLCC8,.25
针数：	8	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.41
风险等级：	5.66	JESD-30 代码：	R-XDSO-N8
长度：	6 mm	内存密度：	1048576 bit
内存集成电路类型：	NON-VOLATILE SRAM	内存宽度：	8
功能数量：	1	端子数量：	8
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX8
封装主体材料：	UNSPECIFIED	封装代码：	HVSON
封装等效代码：	SOLCC8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	电源：	3/3.3 V
认证状态：	Not Qualified	座面最大高度：	0.8 mm
最大待机电流：	0.005 A	子类别：	SRAMs
最大压摆率：	0.01 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5 mm
Base Number Matches：	1

型号	制造商	描述	价格	文档
CY14B101Q1-LHXI	CYPRESS	1 Mbit (128K x 8) Serial SPI nvSRAM	获取价格
CY14B101Q1-LHXIT	CYPRESS	1 Mbit (128K x 8) Serial SPI nvSRAM	获取价格
CY14B101Q1A-S104XI	CYPRESS	Non-Volatile SRAM, 128KX8, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8	获取价格
CY14B101Q1A-SXI	CYPRESS	1-Mbit (128 K x 8) Serial (SPI) nvSRAM Data retention: 20 years at 85 Â°C	获取价格
CY14B101Q1A-SXIT	CYPRESS	1-Mbit (128 K x 8) Serial (SPI) nvSRAM Data retention: 20 years at 85 Â°C	获取价格
CY14B101Q1_10	CYPRESS	1 Mbit (128K x 8) Serial SPI nvSRAM	获取价格
CY14B101Q1_11	CYPRESS	1 Mbit (128 K x 8) Serial SPI nvSRAM Infinite read, write, and RECALL cycles	获取价格
CY14B101Q1_13	CYPRESS	1-Mbit (128 K x 8) Serial SPI nvSRAM	获取价格
CY14B101Q2	CYPRESS	1 Mbit (128K x 8) Serial SPI nvSRAM	获取价格
CY14B101Q2-LHXC	CYPRESS	1 Mbit (128K x 8) Serial SPI nvSRAM	获取价格

CY14B101Q1-LHXCT

CY14B101Q1-LHXCT 概述

CY14B101Q1-LHXCT 规格参数

CY14B101Q1-LHXCT 数据手册

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