CY14B256K-SP45CT [CYPRESS]
Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDSO48, ROHS COMPLIANT, SSOP-48;
| 型号： | CY14B256K-SP45CT |
| 厂家： | 
CYPRESS |
| 描述： | Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDSO48, ROHS COMPLIANT, SSOP-48 静态存储器 光电二极管 |
| 文件： | 总21页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE
INFORMATION
CY14B256K
256-Kbit (32K x 8) nvSRAM with Real-Time
Clock
• 10 mA Typical ICC at 200-ns Cycle Time
Features
• Single 3V Operation 20%, -10%
• Data Integrity of Cypress nvSRAM Combined with
Full-Featured Real-Time Clock
• SSOP Package (ROHS compliant)
— Low Power, 300 nA Max, RTC current
— Capacitor or battery backup for RTC
• Watchdog Timer
Functional Description
The Cypress CY14B256K combines a 256-Kbit nonvolatile
static RAM with a full-featured real-time clock in a monolithic
integrated circuit. The embedded nonvolatile elements incor-
porate QuantumTrap technology producing the world’s most
reliable nonvolatile memory. The SRAM can be read and
written an unlimited number of times, while independent,
nonvolatile data resides in the nonvolatile elements.
• Clock Alarm with programmable Interrupts
• 25 ns, 35 ns, and 45 ns Access Times
• “Hands-off” Automatic STORE on Power-down with
only a small capacitor
• STORE to QuantumTrap™Initiated by Software, device
pin, or on Power-down
The Real-Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscil-
lator. The Alarm function is programmable for one-time alarms
or periodic seconds, minutes, hours, or days. There is also a
programmable Watchdog Timer for process control.
• RECALL to SRAM Initiated by Software or on Power-up
• Unlimited READ, WRITE and RECALL Cycles
• High-reliability
— Endurance to 500K Cycles
— Data Retention: 100 years
Logic Block Diagram
OE
CE
WE
Cypress Semiconductor Corporation
Document #: 001-06431 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 22, 2006
ADVANCE
INFORMATION
CY14B256K
Pin Configurations
V
1
2
V
CAP
48
47
46
45
CC
NC
NC
3
4
5
6
7
8
A
14
HSB
WE
A
A
12
A
7
44
43
13
A
6
A
8
A
5
42
41
40
39
38
A
9
INT
A
NC
NC
NC
NC
A
NC
9
10
4
11
48-SSOP
Top View
11
12
13
14
NC
NC
V
37
36
35
V
SS
(not to scale)
SS
NC
VRTCbat
NC
15
16
17
18
VRTCcap
DQ6
34
33
32
31
30
29
28
27
26
25
DQ0
A
3
OE
A
A
2
10
19
20
21
22
23
24
A
CE
1
A
0
DQ7
DQ5
DQ4
DQ3
DQ1
DQ2
X1
X2
V
CC
Pin Definitions
Pin Name
I/O Type
Input
Description
Address Inputs used to select one of the 131,072 bytes of the nvSRAM.
A0–A14
DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
NC
No Connect No Connects. This pin is not connected to the die.
WE
Input
Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to
the address location latched by the falling edge of CE.
CE
OE
Input
Input
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE high causes the I/O pins to tri-state.
X1
X2
Output
Input
Crystal Connection, drives crystal on start-up.
Crystal Connection for 32.768-kHz crystal.
VRTCcap Power Supply Capacitor-supplied backup RTC supply voltage. (Left unconnected if VRTCbat is used)
VRTCbat Power Supply Battery-supplied backup RTC supply voltage. (Left unconnected if VRTCcap is used)
INT
Output
Interrupt Output. Can be programmed to respond to the clock alarm, the watchdog timer, and the
power monitor. Programmable to either active HIGH (push/pull) or LOW (open-drain).
VSS
VCC
HSB
Ground
Ground for the device. Should be connected to ground of the system.
Power Supply Power Supply inputs to the device.
Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled
low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor
keeps this pin high if not connected. (Connection Optional)
VCAP
Power Supply AutostoreTM Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Document #: 001-06431 Rev. *A
Page 2 of 21
ADVANCE
INFORMATION
CY14B256K
Device Operation
The CY14B256K nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY14B256K supports unlimited reads and
writes just like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and up to 1
million STORE operations.
WE
SRAM Read
The CY14B256K performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A0-14 determines which of the 32,752 data bytes will
be accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of tAA (READ
cycle #1). If the READ is initiated by CE or OE, the outputs will
be valid at tACE or at tDOE, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address changes
within the tAA access time without the need for transitions on
any control input pins, and will remain valid until another
address change or until CE or OE is brought high, or WE or
HSB is brought low.
Figure 1. AutoStoreTM Mode
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. The HSB signal can be monitored by the system
to detect an AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
SRAM Write
The CY14B256K provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When the HSB pin
is driven low, the CY14B256K will conditionally initiate a
STORE operation after tDELAY. An actual STORE cycle will
only begin if a WRITE to the SRAM took place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a busy
condition while the STORE (initiated by any means) is in
progress.
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
common I/O pins DQ0–7 will be written into the memory if it is
valid tSD before the end of a WE controlled WRITE or before
the end of an CE controlled WRITE. It is recommended that
OE be kept high during the entire WRITE cycle to avoid data
bus contention on common I/O lines. If OE is left low, internal
circuitry will turn off the output buffers tHZWE after WE goes
low.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14B256K will continue SRAM operations for
AutoStore Operation
tDELAY. During tDELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
The CY14B256K stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store, activated by HSB, Software Store, activated by an
address sequence, and AutoStore, on device power-down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256K.
During any STORE operation, regardless of how it was
initiated, the CY14B256K will continue to drive the HSB pin
low, releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY14B256K will
remain disabled until the HSB pin returns high.
During normal operation, the device will draw current from VCC
to charge a capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the VCC pin drops below VSWITCH
the part will automatically disconnect the VCAP pin from VCC
,
.
If HSB is not used, it should be left unconnected.
A STORE operation will be initiated with power provided by the
VCAP capacitor.
Hardware RECALL (Power-up)
During power-up, or after any low-power condition (VCC
<
Figure 1 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the DC Charac-
teristics table for the size of VCAP. The voltage on the VCAP pin
is driven to 5V by a charge pump internal to the chip. A pull-up
should be placed on WE to hold it inactive during power-up.
V
SWITCH), an internal RECALL request will be latched. When
VCC once again exceeds the sense voltage of VSWITCH, a
RECALL cycle will automatically be initiated and will take
tHRECALL to complete.
Document #: 001-06431 Rev. *A
Page 3 of 21
ADVANCE
INFORMATION
CY14B256K
Software STORE
Software RECALL
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The CY14B256K
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE-controlled
READ operations must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence, or the
sequence will be aborted and no STORE or RECALL will take
place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is
transferred into the SRAM cells. After the tRECALL cycle time
the SRAM will once again be ready for READ and WRITE
operations.The RECALL operation in no way alters the data in
the nonvolatile elements.
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
Data Protection
The CY14B256K protects data from corruption during
low-voltage conditions by inhibiting all externally initiated
STORE and WRITE operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14B256K is in a
WRITE mode (both CE and WE low) at power-up, after a
RECALL, or after a STORE, the WRITE will be inhibited until
a negative transition on CE or WE is detected. This protects
against inadvertent writes during power-up or brown-out
conditions.
The software sequence may be clocked with CE-controlled
READs or OE-controlled READs. Once the sixth address in
the sequence has been entered, the STORE cycle will
commence and the chip will be disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence,
although it is not necessary that OE be low for the sequence
to be valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE operation.
Table 1. Mode Selection
A15–A0
Mode
I/O
Power
Standby
Active
CE
H
WE
X
OE
X
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
L
L
H
L
L
X
L
Active
H
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
ICC2
[1,2,3]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
[1,2,3]
Notes:
1. The six consecutive address locations must be in the order listed.WE must be HIGH during all six cycles to enable a non-volatile cycle.
2. While there are 17 address lines on the CY14B101K,only the lower 16 lines are used to control software modes.
3. I/O state depends on the state of OE. The I/O table shown assumes OE Low.
Document #: 001-06431 Rev. *A
Page 4 of 21
ADVANCE
INFORMATION
CY14B256K
during a read or write operation. Double buffering also circum-
vents disrupting normal timing counts or clock accuracy of the
internal clock while accessing clock data. Clock and Alarm
Registers store data in BCD format.
Noise Considerations
The CY14B256K is a high-speed memory and so must have
a high-frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high-speed CMOS ICs,
careful routing of power, ground and signals will reduce circuit
noise.
Clock Operations
The clock registers maintain time up to 9,999 years in
one-second increments. The user can set the time to any
calendar time and the clock automatically keeps track of days
of the week and month, leap years, and century transitions.
There are eight registers dedicated to the clock functions
which are used to set time with a write cycle and to read time
during a read cycle. These registers contain the Time of Day
in BCD format. Bits defined as “0” are currently not used and
are reserved for future use by Cypress.
Low Average Active Power
CMOS technology provides CY14B256K the benefit of
drawing significantly less current when it is cycled at times
longer than 50 ns. Figure 2 shows the relationship between
ICC and READ/WRITE cycle time. Worst-case current
consumption is shown for commercial temperature range, VCC
= 3.6V, and chip enable at maximum frequency. Only standby
current is drawn when the chip is disabled. The overall
average current drawn by the CY14B256K depends on the
following items:
Reading the Clock
While the double-buffered RTC register structure reduces the
chance of reading incorrect data from the clock, the user
should halt internal updates to the CY14B256K clock registers
before reading clock data to prevent the reading of data in
transition. Stopping the internal register updates does not
affect clock accuracy. The updating process is stopped by
writing a “1” to the read bit “R” (in the flags register at 0x7FF0),
and will not restart until a “0” is written to the read bit. The RTC
registers can then be read while the internal clock continues
to run. Within 20 ms after a “0” is written to the read bit, all
CY14B256K registers are simultaneously updated.
1. 1The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
6. I/O loading.
Setting the Clock
Setting the write bit “W” (in the flags register at 0x7FF0) to a
“1” halts updates to the CY14B256K registers. The correct
day, date, and time can then be written into the registers in
24-hour BCD format. The time written is referred to as the
“Base Time.” This value is stored in nonvolatile registers and
used in calculation of the current time. Resetting the write bit
to “0” transfers those values to the actual clock counters, after
which the clock resumes normal operation.
Backup Power
The RTC in the CY14B256K is intended for permanently
powered operation. Either the VRTCcap or VRTCbat pin is
connected depending on whether a capacitor or battery is
chosen for the application. When primary power, VCC, fails and
drops below VSWITCH the device will switch to the backup
power supply.
The clock oscillator uses very little current, which maximizes
the backup time available from the backup source. Regardless
of clock operation with the primary source removed, the data
stored in nvSRAM is secure, having been stored in the nonvol-
atile elements as power was lost.
During backup operation the CY14B256K consumes a
maximum of 300 nanoamps at 2 volts. Capacitor or battery
values should be chosen according to the application. Backup
time values based on maximum current specs are shown
below. Nominal times are approximately 3 times longer.
Figure 2. Current vs. Cycle Time
Real-Time Clock Operation
nvTIME Operation
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a
battery is used, a 3V lithium is recommended and the
CY14B256K will only source current from the battery when the
primary power is removed. The battery will not, however, be
recharged at any time by the CY14B256K. The battery
The CY14B256K offers internal registers that contain Clock,
Alarm, Watchdog, Interrupt, and Control functions. Internal
double buffering of the clock and the clock/timer information
registers prevents accessing transitional internal clock data
Document #: 001-06431 Rev. *A
Page 5 of 21
ADVANCE
INFORMATION
CY14B256K
Table 2. RTC Backup Time
If a binary “1” is loaded into the register, only the first 2 minutes
of the 64-minute cycle will be modified; if a binary 6 is loaded,
the first 12 will be affected, and so on. Therefore each
calibration step has the effect of adding 512 or subtracting 256
oscillator cycles for every 125,829,120 actual oscillator cycles.
That is 4.068 or –2.034 ppm of adjustment per calibration step
in the calibration register.
Capacitor Value
Backup Time
72 hours
14 days
0.1F
0.47F
1.0F
30 days
In order to determine how to set the calibration one may set
the CAL bit in the flags register at 0x1FFF0 to 1, which causes
the INT pin to toggle at a nominal 512 Hz. Any deviation
measured from the 512 Hz will indicate the degree and
direction of the required correction. For example, a reading of
512.010124 Hz would indicate a +20 ppm error, requiring a
–10 (001010) to be loaded into the Calibration register. Note
that setting or changing the calibration register does not affect
the frequency test output frequency.
capacity should be chosen for total anticipated cumulative
down-time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in calibration register at 0x1FFF8 controls the
starting and stopping of the oscillator. This bit is nonvolatile
and shipped to customers in the “enabled” (set to 0) state. To
preserve battery life while system is in storage OSCEN should
be set to a 1. This will turn off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to
enabled, it will take approximately 5 seconds (10 seconds
max) for the oscillator to start.
Alarm
The alarm function compares user-programmed values to the
corresponding time-of-day values. When a match occurs, the
alarm event occurs. The alarm drives an internal flag, AF, and
may drive the INT pin if desired.
The CY14B256K has the ability to detect oscillator failure. This
is recorded in the OSCF (Oscillator Failed bit) of the flags
register at address 0x1FFF0. When the device is powered on
(VCC goes above VSWITCH) the OSCEN bit is checked for
“enabled” status. If the OSCEN bit is enabled and the oscillator
is not active, the OSCF bit is set. The user should check for
this condition and then write a 0 to clear the flag. It should be
noted that in addition to setting the OSCF flag bit, the time
registers are reset to the “Base Time” (see the section “Setting
the Clock”), which is the value last written to the timekeeping
registers. The Control/Calibration register and the OSCEN bit
are not affected by the oscillator failed condition.
There are four alarm match fields. They are date, hours,
minutes, and seconds. Each of these fields also has a Match
bit that is used to determine if the field is used in the alarm
match logic. Setting the Match bit to “0” indicates that the
corresponding field will be used in the match process.
Depending on the Match bits, the alarm can occur as specific-
ally as one particular second on one day of the month, or as
frequently as once per second continuously. The MSB of each
alarm register is a Match bit. Selecting none of the Match bits
(all 1s) indicates that no match is required. The alarm occurs
every second. Setting the match select bit for seconds to “0”
causes the logic to match the seconds alarm value to the
current time of day. Since a match will occur for only one value
per minute, the alarm occurs once per minute. Likewise,
setting the seconds and minutes Match bits causes an exact
match of these values. Thus, an alarm will occur once per
hour. Setting seconds, minutes and hours causes a match
once per day. Lastly, selecting all match values causes an
exact time and date match. Selecting other bit combinations
will not produce meaningful results; however the alarm circuit
should follow the functions described.
If the voltage on the backup supply (either VRTCcap or VRTCbat
)
falls below its respective minimum level the oscillator may fail,
leading to the oscillator failed condition, which can be detected
when system power is restored.
The value of OSCF should be reset to 0 when the time
registers are written for the first time. This will initialize the
state of this bit, which may have been set when the system
was first powered on.
Calibrating the Clock
The RTC is driven by a quartz-controlled oscillator with a
nominal frequency of 32.768 kHz. Clock accuracy will depend
on the quality of the crystal, usually specified to 35-ppm limits
at 25°C. This error could equate to +1.53 minutes per month.
The CY14B256K employs a calibration circuit that can
improve the accuracy to +1/–2 ppm at 25°C. The calibration
circuit adds or subtracts counts from the oscillator divider
circuit.
There are two ways a user can detect an alarm event, by
reading the AF flag or monitoring the INT pin. The AF flag in
the flags register at 0x7FF0 will indicate that a date/time match
has occurred. The AF bit will be set to 1 when a match occurs.
Reading the Flags/Control register clears the alarm flag bit
(and all others). A hardware interrupt pin may also be used to
detect an alarm event.
The number of times pulses are suppressed (subtracted,
negative calibration) or split (added, positive calibration)
depends upon the value loaded into the five calibration bits
found in calibration register at 0x7FF8. Adding counts speeds
the clock up; subtracting counts slows the clock down. The
Calibration bits occupy the five lower-order bits in the control
register 8. These bits can be set to represent any value
between 0 and 31 in binary form. Bit D5 is a Sign bit, where a
“1” indicates positive calibration and a “0” indicates negative
calibration. Calibration occurs within a 64-minute cycle. The
first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscil-
lator cycles.
Watchdog Timer
The watchdog timer is a free running down counter that uses
the 32-Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator must be running for the watchdog to function. It
begins counting down from the value loaded in the Watchdog
Timer register.
The counter consists of a loadable register and a free running
counter. On power up, the watchdog time-out value in register
0x7FF7 is loaded into the counter load register. Counting
begins on power-up and restarts from the loadable value any
time the Watchdog Strobe (WDS) bit is set to 1. The counter is
Document #: 001-06431 Rev. *A
Page 6 of 21
ADVANCE
INFORMATION
CY14B256K
compared to the terminal value of 0. If the counter reaches this
value, it causes an internal flag and an optional interrupt
output. The user can prevent the time-out interrupt by setting
WDS bit to 1 prior to the counter reaching 0. This causes the
counter to be reloaded with the watchdog time-out value and
to be restarted. As long as the user sets the WDS bit prior to
the counter reaching the terminal value, the interrupt and flag
never occurs.
The clock continues to operate in the background. Updated
clock data is available to the user after tHRECALL delay (see
AutoStore/Power-up Recall) after VCC has been restored to
the device.
Interrupts
The CY14B256K provides three potential interrupt sources.
They include the watchdog timer, the power monitor, and the
clock/calendar alarm. Each can be individually enabled and
assigned to drive the INT pin. In addition, each has an
associated flag bit that the host processor can use to
determine the cause of the interrupt. Some of the sources
have additional control bits that determine functional behavior.
In addition, the pin driver has three bits that specify its behavior
when an interrupt occurs.
New time-out values can be written by setting the watchdog
write bit to 0. When the WDW is 0 (from the previous
operation), new writes to the watchdog time-out value bits
D5-D0 allow the time-out value to be modified. When WDW is
a 1, then writes to bits D5-D0 will be ignored. The WDW
function allows a user to set the WDS bit without concern that
the watchdog timer value will be modified. A logical diagram of
the watchdog timer is shown in Figure 3. Note that setting the
watchdog time-out value to 0 would be otherwise meaningless
and therefore disables the watchdog function.
The three interrupts each have a source and an enable. Both
the source and the enable must be active (true high) in order
to generate an interrupt output. Only one source is necessary
to drive the pin. The user can identify the source by reading
the Flags/Control register, which contains the flags associated
with each source. All flags are cleared to 0 when the register
is read. The cycle must be a complete read cycle (WE high);
otherwise the flags will not be cleared. The power monitor has
two programmable settings that are explained in the power
monitor section.
The output of the watchdog timer is a flag bit WDF that is set
if the watchdog is allowed to time-out. The flag is set upon a
watchdog time-out and cleared when the Flags/Control
register is read by the user. The user can also enable an
optional interrupt source to drive the INT pin if the watchdog
time-out occurs.
Once an interrupt source is active, the pin driver determines
the behavior of the output. It has two programmable settings
as shown below. Pin driver control bits are located in the Inter-
rupts register.
According to the programming selections, the pin can be
driven in the backup mode for an alarm interrupt. In addition,
the pin can be an active LOW (open-drain) or an active HIGH
(push-pull) driver. If programmed for operation during backup
mode, it can only be active LOW. Lastly, the pin can provide a
one-shot function so that the active condition is a pulse or a
level condition. In one-shot mode, the pulse width is internally
fixed at approximately 200 ms. This mode is intended to reset
a host microcontroller. In level mode, the pin goes to its active
polarity until the Flags/Control register is read by the user. This
mode is intended to be used as an interrupt to a host micro-
controller. The control bits are summarized as follows:
Watchdog Interrupt Enable - WIE. When set to 1, the
watchdog timer drives the INT pin as well as an internal flag
when a watchdog time-out occurs. When WIE is set to 0, the
watchdog timer affects only the internal flag.
Figure 3. Watchdog Timer Block Diagram
Power Monitor
Alarm Interrupt Enable - AIE. When set to 1, the alarm match
drives the INT pin as well as an internal flag. When set to 0,
the alarm match only affects to internal flag.
The CY14B256K provides a power management scheme with
power-fail interrupt capability. It also controls the internal
switch to backup power for the clock and protects the memory
from low-VCC access. The power monitor is based on an
internal band-gap reference circuit that compares the VCC
voltage to various thresholds.
Power Fail Interrupt Enable - PFE. When set to 1, the power
fail monitor drives the pin as well as an internal flag. When set
to 0, the power fail monitor affects only the internal flag.
High/Low - H/L. When set to a 1, the INT pin is active HIGH
and the driver mode is push-pull. The INT pin can drive high
only when VCC > VSWITCH. When set to a 0, the INT pin is
active LOW and the drive mode is opendrain. Active LOW
(open drain) is operational even in battery backup mode.
As described previously in the AutoStore section, when
VSWITCH is reached as VCC decays from power loss, a data
store operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor)
to operate the RTC oscillator.
Pulse/Level - P/L. When set to a 1 and an interrupt occurs,
the INT pin is driven for approximately 200 ms. When P/L is
set to a 0, the INT pin is driven high or low (determined by H/L)
until the Flags/Control register is read.
When operating from the backup source no data may be read
or written and the clock functions are not available to the user.
Document #: 001-06431 Rev. *A
Page 7 of 21
ADVANCE
INFORMATION
CY14B256K
When an enabled interrupt source activates the INT pin, an
external host can read the Flags/Control register to determine
the cause. Remember that all flags will be cleared when the
register is read. If the INT pin is programmed for Level mode,
then the condition will clear and the INT pin will return to its
inactive state. If the pin is programmed for Pulse mode, then
reading the flag also will clear the flag and the pin. The pulse
will not complete its specified duration if the Flags/Control
register is read. If the INT pin is used as a host reset, then the
Flags/Control register should not be read during a reset.
During a power-on reset with no battery, the interrupt register
is automatically loaded with the value 24h. This causes
power-fail interrupt to be enabled with an active-low pulse.
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
Enable
PF - Power fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
Figure 4. Interrupt Block Diagram
Table 3. RTC Register Map
BCD Format Data
Register
0x7FFF
0x7FFE
D7
D6
D5
D4
D3
D2
D1
Years
Months
D0
Function/Range
Years: 00–99
10s Years
0
0
0
10s
Months
Months: 01–12
0x7FFD
0x7FFC
0x7FFB
0x7FFA
0x7FF9
0
0
0
0
0
0
0
10s Day of Month
Day Of Month
Day of week
Day of Month: 01–31
Day of week: 01–07
Hours: 00–23
0
0
0
10s Hours
10s Minutes
Hours
Minutes
Seconds
Minutes: 00–59
10s Seconds
Cal Sign
Seconds: 00–59
0x7FF8 OSCEN
0
WDW
AIE
0
Calibration
WDT
P/L
Calibration Values[4]
Watchdog[4]
0x7FF7
0x7FF6
0x7FF5
0x7FF4
0x7FF3
0x7FF2
0x7FF1
WDS
WIE
M
PFE
ABE
H/L
0
0
Interrupts[4]
10s Alarm Date
10s Alarm Hours
Alarm Day
Alarm, Day of Month: 01–31
Alarm, Hours: 00–23
Alarm, Minutes: 00–59
Alarm, Seconds: 00–59
Centuries: 00–99
Flags[4]
M
0
Alarm Hours
M
10 Alarm Minutes
10 Alarm Minutes
10s Centuries
Alarm Minutes
Alarm, Seconds
Centuries
M
0x7FF0
WDF
AF
PF
OSCF
0
CAL
W
R
Note:
4. Is a binary value, not a BCD value.
Document #: 001-06431 Rev. *A
Page 8 of 21
ADVANCE
INFORMATION
CY14B256K
Table 4. Register Map Detail
D7
Time Keeping - Years
D4 D3
D6
D5
10s Years
D2
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the
0x7FFF value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
Time Keeping - Months
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
10s Month
Months
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
0x7FFE (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.
Time Keeping - Date
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Day of Month
Day of Month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1–31. Leap years are
0x7FFD automatically adjusted for.
Time Keeping - Day
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
Day of Week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from
0x7FFC 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date.
Time Keeping - Hours
D7
D6
D5
D4
D3
D2
D1
D0
12/24
0
10s Hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9;
0x7FFB upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23.
Time Keeping - Minutes
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Minutes
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
0x7FFA contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59.
Time Keeping - Seconds
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Seconds
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
0x7FF9 contains the upper digit and operates from 0 to 5. The range for the register is 0–59.
Calibration/Control
D7
D6
D5
D4
D3
D2
D1
D0
OSCEN
0
Calibration
Sign
Calibration
0X7FF8
OSCEN Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator
saves battery/capacitor power during storage. On a no-battery power-up, this bit is set to 0.
Calibration Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base.
Sign
Calibration These five bits control the calibration of the clock.
Document #: 001-06431 Rev. *A
Page 9 of 21
ADVANCE
INFORMATION
CY14B256K
Table 4. Register Map Detail (continued)
WatchDog Timer
D7
D6
D5
D4
D3
D2
D1
D0
0x7FF7
WDS
WDW
WDT
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no affect.
The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only. Reading it always will
return a 0.
WDW
WDT
Watchdog Write Enable. Setting this bit to 1 masks the watchdog time-out value (WDT5–WDT0) so it cannot be
written. This allows the user to strobe the watchdog without disturbing the time-out value. Setting this bit to 0 allows
bits 5–0 to be written on the next write to the Watchdog register. The new value will be loaded on the next internal
watchdog clock after the write cycle is complete. This function is explained in more detail in the watchdog timer
section.
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents
a multiplier of the 32-Hz count (31.25 ms). The minimum range or time-out value is 31.25 ms (a setting of 1) and
the maximum time-out is 2 seconds (setting of 3Fh). Setting the watchdog timer register to 0 disables the timer.
These bits can be written only if the WDW bit was cleared to 0 on a previous cycle.
Interrupt Status/Control
D7
D6
D5
D4
D3
D2
D1
D0
0x7FF6
WIE
AIE
PFIE
ABE
H/L
P/L
0
0
WIE
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the INT pin
as well as the WDF flag. When set to 0, the watchdog time-out affects only the WDF flag.
AIE
PFIE
ABE
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When set to 0,
the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When set to 0, the
power-fail monitor affects only the PF flag.
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function even in battery
backup mode. When set to 0, the alarm will occur only when VCC > VSWITCH
.
H/L
P/L
High/Low. When set to a 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approxi-
mately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags/Control register
is read.
Alarm - Day
D7
D6
D5
D4
D3
D2
D1
Alarm Date
D0
M
0
10s Alarm Date
0x7FF5 Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
M
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the date value.
Alarm - Hours
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Hours
Alarm Hours
0x7FF4 Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the hours value.
Alarm - Minutes
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Minutes
Alarm Minutes
0x7FF3 Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
M
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the minutes value.
Document #: 001-06431 Rev. *A
Page 10 of 21
ADVANCE
INFORMATION
CY14B256K
Table 4. Register Map Detail (continued)
Alarm - Seconds
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Seconds
Alarm Seconds
0x7FF2 Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this bit to 1 causes
the match circuit to ignore the seconds value.
Time Keeping - Centuries
D7
D6
D5
D4
D3
D2
D1
Centuries
D0
0x7FF1
0
0
10s Centuries
Flags
D7
D6
D5
D4
D3
D2
D1
D0
0x7FF0
WDF
AF
PF
OSCF
0
CAL
W
R
WDF
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being
reset by the user. It is cleared to 0 when the Flags/Control register is read.
AF
PF
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers with
the match bits = 0. It is cleared when the Flags/Control register is read.
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold VSWITCH. It is cleared
to 0 when the Flags/Control register is read.
OSCF
Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is not running in the first 5 ms of power-on operation.
This indicates that time counts are no longer valid. The user must reset this bit to 0 to clear this condition. The chip
will not clear this flag. This bit survives power cycles.
CAL
W
Calibration Mode. When set to 1, a 512-Hz square wave is output on the INT pin. When set to 0, the INT pin resumes
normal operation. This bit defaults to 0 (disabled) on power-up.
Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then write them with
updated values. Setting the W bit to 0 causes the contents of the time registers to be transferred to the timekeeping
counters.
R
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a holding
register. The user can then read them without concerns over changing values causing system errors. The R bit
going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior to reading again.
Document #: 001-06431 Rev. *A
Page 11 of 21
ADVANCE
INFORMATION
CY14B256K
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Surface Mount Lead Soldering
Temperature (3 Seconds).......................................... +240°C
Output Short Circuit Current[5]..................................... 15 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Supply Voltage on VCC Relative to GND.......... –0.5V to 4.1V
Latch-up Current.................................................... > 200 mA
Voltage Applied to Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Table 5. Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Input Voltage............................................ –0.5V to Vcc+0.5V
2.7V to 3.6V
2.7V to 3.6V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential...................–2.0V to VCC + 2.0V
–40°C to +85°C
Shaded area contains Advance Information
DC Electrical Characteristics Over the Operating Range (VCC = 2.7V to 3.6V)[6]
Parameter
Description
Test Conditions
Min.
Max.
Unit
ICC1
Average VCC Current tRC = 25 ns
Commercial
Industrial
65
55
50
mA
mA
mA
t
t
RC = 35 ns
RC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads. IOUT = 0mA.
70
60
55
mA
mA
mA
ICC2
ICC3
Average VCC Current All Inputs Don’t Care, VCC = Max.
during STORE Average current for duration tSTORE
3
mA
mA
AverageVCCCurrentat WE > (VCC – 0.2). All other inputs cycling.
10
t
AVAV = 200 ns, 3V,
Dependent on output loading and cycle rate. Values obtained
without output loads.
25°C typical
ICC4
ISB
Average VCAP Current All Inputs Don’t Care, VCC = Max.
during AutoStore Cycle Average current for duration tSTORE
3
3
mA
mA
VCC Standby Current WE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0MHz.
IIX
Input Leakage Current VCC = Max., VSS < VIN < VCC
-1
-1
+1
+1
µA
µA
IOZ
Off-State Output
Leakage Current
VCC = Max., VSS < VIN < VCC
CE or OE > VIH
,
VIH
Input HIGH Voltage
Input LOW Voltage
2.2
VSS – 0.5
2.4
VCC + 0.3
0.8
V
V
VIL
VOH
VOL
VCAP
Output HIGH Voltage IOUT = –2 mA
V
Output LOW Voltage
Storage Capacitor
IOUT = 4 mA
Between VCAP pin and VSS, 5V Rated
0.4
57
V
17
µF
Table 6. Capacitance[7]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 0 to 3.0V
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
7
7
V
COUT
pF
Notes:
5. Outputs shorted for no more than one second. No more than one output shorted at a time.
6. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and V = 3V. Not 100% tested.
CC
7. These parameters are guaranteed but not tested.
Document #: 001-06431 Rev. *A
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ADVANCE
INFORMATION
CY14B256K
Table 7. Thermal Resistance[7]
Parameter
Description
Test Conditions
Test conditions follow standard test methods and procedures for
48-SSOP Unit
ΘJA
Thermal Resistance
(Junction to Ambient) measuring thermal impedance, per EIA / JESD51.
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
°C/W
AC Test Loads
R1 577Ω
R1 577Ω
for tri-state specs
3.0V
OUTPUT
3.0V
OUTPUT
R2
789Ω
R2
789Ω
5 pF
30 pF
AC Test Conditions
Input Pulse Levels ..........................................0V to 3V
Input Rise and Fall Times (10% - 90%) ............... <5ns
Input and Output Timing Reference Levels .......... 1.5V
Document #: 001-06431 Rev. *A
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ADVANCE
INFORMATION
CY14B256K
Table 8. AC Switching Characteristics
Parameters
CY14B256K-25 CY14B256K-35 CY14B256K-45
Cypress
Alt.
Parameter Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
SRAM Read Cycle
tACE
tACS
tRC
tAA
Chip Enable Access Time
Read Cycle Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[8]
tRC
25
35
45
[9]
tAA
Address Access Time
25
12
35
15
45
20
tDOE
tOE
tOH
tLZ
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
[9]
tOHA
3
3
3
3
3
3
[10]
[10]
tLZCE
tHZCE
tHZ
10
10
25
13
13
35
15
15
45
[10]
tLZOE
tOLZ
tOHZ
tPA
0
0
0
0
0
0
[10]
tHZOE
[7]
tPU
[7]
tPD
tPS
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tWC
tWP
tCW
tDW
tDH
tAW
tAS
Write Cycle Time
25
20
20
10
0
35
25
25
12
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable To End of Write
Data Set-Up to End of Write
Data Hold After End of Write
Address Set-Up to End of Write
Address Set-Up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
tHD
tAW
20
0
25
0
30
0
tSA
tHA
tWR
tWZ
tOW
0
0
0
[10,11]
tHZWE
10
13
15
[10]
tLZWE
3
3
3
Notes:
8. WE must be HIGH during SRAM Read Cycles.
9. Device is continuously selected with CE and OE both Low.
10. Measured ±200mV from steady state output voltage.
11. If WE is Low when CE goes Low,the outputs remain in the High Impedance State
Document #: 001-06431 Rev. *A
Page 14 of 21
ADVANCE
INFORMATION
CY14B256K
Table 9. AutoStore/Power-Up RECALL
CY14B256K
20
Parameters
Description
Power-Up RECALL Duration
STORE Cycle Duration
Units
ms
ms
V
[12]
tHRECALL
[13]
tSTORE
12.5
2.65
VSWITCH
tVCCRISE
Low Voltage Trigger Level
VCC Rise Time
2.55
150
µs
Table 10.Software Controlled STORE/RECALL Cycle[14,15]
CY14B256K-25
CY14B256K-35
CY14B256K-45
Parameters
tRC
Description
STORE/RECALL Initiation Cycle Time
Address Set-Up Time
Min.
25
0
Max.
Min.
35
0
Max.
Min.
45
0
Max.
Units
ns
tAS
ns
tCW
Clock Pulse Width
20
20
25
20
30
20
ns
tGLAX
tRECALL
Address Hold Time
ns
RECALL Duration
60
60
60
µs
Table 11.Hardware STORE Cycle
CY14B256K
Parameters
Description
Min
Max
Units
[16]
tDELAY
tHLHX
tHLBL
Time allowed to complete SRAM Cycle
Hardware STORE Pulse Width
1
µs
ns
ns
15
Hardware STORE Low to STORE Busy
300
Switching Waveforms
tRC
tAA
tOH
Figure 5. SRAM Read Cycle #1: Address Controlled[8, 9, 17]
Notes:
12. t
starts from the time V rises above V
.
HRECALL
CC
SWITCH
13. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE will take place.
14. The software sequence is clocked with CE-controlled or OE-controlled READs.
15. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
16. Read and Write cycles in progress before HSB are given this amount of time to complete.
17. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-06431 Rev. *A
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INFORMATION
CY14B256K
Switching Waveforms (continued)
t
t
ACE
PU
CE
OE
t
LZCE
t
HZCE
t
t
HZOE
DOE
t
LZOE
t
PU
Figure 6. SRAM Read Cycle #2: CE and OE Controlled[8,17]
tHA
tSCE
CE
tSA
tPWE
WE
tSD
tHD
tHZWE
tLZWE
Figure 7. SRAM Write Cycle #1: WE Controlled[17,18]
Note:
18. CE or WE must be > V during address transitions.
IH
Document #: 001-06431 Rev. *A
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ADVANCE
INFORMATION
CY14B256K
Switching Waveforms (continued)
tSA
tHA
tSCE
CE
tPWE
WE
tSD
tHD
Figure 8. SRAM Write Cycle #2: CE Controlled
Figure 9. AutoStore/Power-Up RECALL
Document #: 001-06431 Rev. *A
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ADVANCE
INFORMATION
CY14B256K
Switching Waveforms (continued)
tSCE
tSA
CE
OE
tGLAX
Figure 10. CE-controlled Software STORE/RECALL Cycle[15]
CE
tSCE
tSA
OE
Figure 11. OE-controlled Software STORE/RECALL Cycle[15]
Document #: 001-06431 Rev. *A
Page 18 of 21
ADVANCE
INFORMATION
CY14B256K
Switching Waveforms (continued)
Figure 12. Hardware STORE Cycle
PART NUMBERING NOMENCLATURE
CY 14 B 256 K - SP 25 C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
A - Automotive (–40 to 125°C)
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
55 - 55 ns
Package:
SP - 48 SSOP
Data Bus:
K - x8 + RTC
L - x8
Density:
016 - 16 Kb
064 - 64 Kb
256 - 256 Kb
101 - 1 Mb
102 - 2 Mb
104 - 4 Mb
Voltage:
A - 1.8V
B - 3.0V
C - 3.3V
D - 3.0/3.3V
E - 5.0V
NVSRAM
14 - AutoStore + software store + hardware store
11 - Software store
15 - AutoStore + software store
16 - AutoStorePlus + hardware store
10 - Hardware store
22 - AutoStore + Hardware Store
25 - AutoStore
Cypress
Document #: 001-06431 Rev. *A
Page 19 of 21
ADVANCE
INFORMATION
CY14B256K
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
25
CY14B256K-SP25CT
CY14B256K-SP25IT
CY14B256K-SP25I
CY14B256K-SP45CT
CY14B256K-SP45IT
CY14B256K-SP45I
51-85061 48-pin SSOP Pb-Free
51-85061 48-pin SSOP Pb-Free
51-85061 48-pin SSOP Pb-Free
51-85061 48-pin SSOP Pb-Free
51-85061 48-pin SSOP Pb-Free
51-85061 48-pin SSOP Pb-Free
Commercial
Industrial
45
Commercial
Industrial
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Package Diagrams
48-Lead Shrunk Small Outline Package (51-85061)
51-85061-*C
Document #: 001-06431 Rev. *A
Page 20 of 21
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
ADVANCE
INFORMATION
CY14B256K
Document Title: CY14B256K 256-Kbit (32K x 8) nvSRAM with Real-Time Clock
Document Number: 001-06431
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
425138
437321
Description of Change
See ECN
See ECN
TUP
TUP
New Data Sheet
Show Data Sheet on external Web
*A
Document #: 001-06431 Rev. *A
Page 21 of 21
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