CY14V101QS-BK108XITR

PRELIMINARY

CY14V101QS

1-Mbit (128K × 8) Quad SPI nvSRAM

■ Recall from nonvolatile SONOS FLASH Quantum Trap to

SRAM

Features

■ Density

❐ 1 Mbit (128K × 8)

❐ Auto RECALL: Initiated automatically at power-up

❐ Software: Using SPI instruction (RECALL)

■ Bandwidth

■ Low-power modes

❐ 108-MHz high-speed interface

❐ Read and write at 54 Mbps

❐ Sleep: Average current = 280 µA at 85 °C, 500 µA at 105 °C

❐ Hibernate: Average current = 8 µA at 85 °C, 10 µA at 105 °C

■ Serial Peripheral Interface

❐ Clock polarity and phase modes 0 and 3

■ Operating supply voltages

❐ Core V_CC: 2.7 V to 3.6 V

❐ Multi I/O option – Single SPI (SPI), Dual SPI (DPI), and Quad

❐ I/O V_CCQ: 1.71 V to 2.0 V

SPI (QPI)

■ Temperature range

❐ Extended Industrial: –40 °C to 105 °C

❐ Industrial: –40 °C to 85 °C

■ High reliability

❐ Infinite read, write, and RECALL cycles

❐ One million STORE cycles to nonvolatile elements (SONOS

FLASH Quantum trap)

■ Packages

❐ 16-pin SOIC

❐ 24-ball FBGA

❐ Data retention: 20 years at 85 °C

■ Read

❐ Commands: Normal, Fast, Dual I/O, and Quad I/O

❐ Modes: Burst Wrap, Continuous (XIP)

Functional Overview

■ Write

The Cypress CY14V101QS combines a 1-Mbit nvSRAM in a

monolithic integrated circuit with a QPI interface. The QPI allows

writing and reading the memory in either a single (one I/O

channel for one bit per clock cycle), dual (two I/O channels for

two bits per clock cycle), or quad (four I/O channels for four bits

per clock cycle) through the use of selected opcodes.

❐ Commands: Normal, Fast, Dual I/O, and Quad I/O

❐ Modes: Burst Wrap, Continuous (XIP)

■ Data protection

❐ Hardware: Through Write Protect Pin (WP)

❐ Software: Through Write Disable instruction

❐ Block Protection: Status Register bits to control protection

The memory is organized as 128K words of eight bits each

consisting of SRAM and nonvolatile SONOS FLASH Quantum

Trap cells. The SRAM provides infinite read and write cycles,

while the nonvolatile cells provide highly reliable nonvolatile

storage of data. Data transfers from SRAM to the nonvolatile

cells (STORE operation) take place automatically at

power-down. On power-up, data is restored to the SRAM from

the nonvolatile cells (RECALL operation). You can also initiate

the STORE and RECALL operations through SPI instruction.

■ Special instructions

❐ STORE/RECALL: Access data between SRAM and

Quantum Trap

❐ Serial Number: 8-byte customer selectable (OTP)

❐ Identification Number: 4-byte Manufacturer ID and Product

ID

■ Store from SRAM to nonvolatile SONOS FLASHQuantum Trap

❐ AutoStore: Initiated automatically at power-down with a small

capacitor (V_CAP

)

❐ Software: Using SPI instruction (STORE)

❐ Hardware: HSB pin

Cypress Semiconductor Corporation

Document Number: 001-85257 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 9, 2015

PRELIMINARY

CY14V101QS

Logic Block Diagram

Serial Number

Status

Configuration

Registers

Manufacturer ID

Product ID

Nonvolatile Array

(128K x 8)

HOLD (I/O3)

HSB

STORE

SPI/DPI/QPI

Control Logic

SI (I/O0)

CS

RECALL

Memory Control

Address & Data

SRAM

Array

Write Protection

(128K x 8)

SCK

Instruction Decoder

WP (I/O2)

SO (I/O1)

SLEEP/HIBERNATE

V_CC

V_CCQ

V_SS

Power Control

Block

V_CAP

Document Number: 001-85257 Rev. *G

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CY14V101QS

Contents

Pinout ................................................................................4

Pin Definitions .............................................................5

Device Operation ..............................................................7

SRAM Write .................................................................7

SRAM Read ................................................................7

STORE Operation .......................................................7

AutoStore Operation ....................................................7

Software STORE Operation ........................................8

Hardware STORE and HSB Pin Operation .................8

RECALL Operation ......................................................8

Hardware RECALL (Power-Up) ..................................8

Software RECALL .......................................................8

Disabling and Enabling AutoStore ...............................8

Quad Serial Peripheral Interface .....................................9

SPI Overview ...............................................................9

Dual and Quad I/O Modes .........................................11

SPI Modes .................................................................11

SPI Operating Features ..................................................12

Power-Up ..................................................................12

Power-Down ..............................................................12

Active Power Mode and Standby State .....................12

SPI Functional Description ............................................13

Status Register ...............................................................15

Write Disable (WRDI) Instruction ..............................18

Write Enable (WREN) Instruction ..............................18

Enable DPI (DPIEN) Instruction ................................19

Enable QPI (QPIEN) Instruction ................................19

Enable SPI (SPIEN) Instruction .................................19

SPI Memory Read Instructions ......................................20

Read Instructions ......................................................20

Fast Read Instructions ..............................................21

Write Instructions .......................................................25

System Resources Instructions ....................................30

Software Reset (RESET) Instruction .........................30

Default Recovery Instruction .....................................31

Hibernate (HIBEN) Instruction ...................................31

Sleep (SLEEP) Instruction .........................................32

Register Instructions ......................................................34

Read Status Register (RDSR) Instruction .................34

Write Status Register (WRSR) Instruction ................34

Read Configuration Register (RDCR) Instruction ......35

Write Configuration Register (WRCR) Instruction .....36

Identification Register (RDID) Instruction ..................37

Identification Register (FAST_RDID) Instruction .......38

Serial Number Register Write (WRSN) Instruction ....39

Serial Number Register Read (RDSN) Instruction ....40

Fast Read Serial Number Register (FAST_RDSN)

Instruction ..................................................................42

NV Specific Instructions ................................................43

Software Store (STORE) Instruction .........................43

Software Recall (RECALL) Instruction ......................43

Autostore Enable (ASEN) Instruction ........................44

Autostore Disable (ASDI) Instruction .........................44

HOLD Pin Operation .................................................45

Maximum Ratings ...........................................................46

Operating Range .............................................................46

DC Specifications ...........................................................46

Data Retention and Endurance .....................................48

Capacitance ....................................................................48

Thermal Resistance ........................................................48

AC Test Loads and Waveforms .....................................48

AC Test Conditions ........................................................48

AC Switching Characteristics .......................................49

Switching Waveforms ....................................................50

AutoStore or Power-Up RECALL ..................................50

Switching Waveforms ....................................................51

Software Controlled STORE and RECALL Cycles ......52

Switching Waveforms ....................................................52

Hardware STORE Cycle .................................................53

Switching Waveforms ....................................................53

Ordering Information ......................................................54

Ordering Code Definitions .........................................55

Package Diagrams ..........................................................56

Acronyms ........................................................................57

Document Conventions .................................................57

Units of Measure .......................................................57

Document History Page ................................................58

Sales, Solutions, and Legal Information ......................61

Worldwide Sales and Design Support .......................61

Products ....................................................................61

PSoC^®Solutions .......................................................61

Cypress Developer Community .................................61

Technical Support .....................................................61

Document Number: 001-85257 Rev. *G

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CY14V101QS

Pinout

Figure 1. 16-Pin SOIC Standard Pinout

HOLD (I/O3)

16

15

SCK

1

2

3

4

5

VCC

RFU

NC

SI (I/O0)

VCCQ

VCAP

HSB

14

13

12

11

10

16-pin

SOIC

NC

Top View

RFU

CS

6

7

8

NC

VSS

SO (I/O1)

9

WP (I/O2)

Figure 2. 16-Pin SOIC Custom Pinout

HOLD (I/O3)

VCCQ

VCC

16

15

SCK

1

2

3

4

5

SI (I/O0)

NC

14

13

12

11

10

16-pin

SOIC

NC

VCAP

HSB

NC

Top View

NC

CS

6

7

8

NC

VSS

SO(I/O1)

(I/O2)

WP

9

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CY14V101QS

Figure 3. 24-Ball FPGA Standard Pinout-Top View (Ball Side Down)

1

2

3

4

5

A

B

C

D

E

HSB

NC

SCK

CS

VSS

NC

VCC

NC

WP

(I/O2)

SO

(I/O1)

SI

(I/O0)

HOLD

(I/O3)

VCAP

NC

VCCQ

Pin Definitions

Pin Description

I/O Type

Description

HOLD pin. Suspends serial operation.

Input

HOLD (I/O3)

I/O3: When the part is in quad mode, the HOLD pin becomes I/O3 pin and acts as

input/output.

Input/Output

V_CCQ

V_CC

Power Supply

Power supply inputs for the I/Os of the device.

Power supply inputs to the core of the device.

Chip Select. Activates the device when pulled LOW. Driving this pin HIGH puts the

device in standby state.

CS

Input

Output

Serial Output. Pin for output of data through SPI.

SO (I/O1)

I/O1: When the part is in dual or quad mode, the SO pin becomes I/O1 pin and acts

as input/output.

Input/Output

Input

Write Protect. Implements hardware write-protection in SPI.

WP (I/O2)

V_SS

I/O2: When the part is in quad mode, the WP pin becomes an I/O2 pin and acts as

input/output.

Input/Output

Ground

Ground power supply inputs to the core and I/Os of the device.

Hardware STORE Busy:

Output: Indicates the busy status of nvSRAM when LOW. After each Hardware and

Software STORE operation, HSB is driven HIGH for a short time (t_HHHD) with standard

output HIGH current and then a weak internal pull-up resistor keeps this pin HIGH

(external pull-up resistor connection is optional).

HSB

Input/Output

Input: Hardware STORE implemented by pulling this pin LOW externally.

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CY14V101QS

Pin Definitions (continued)

Pin Description

I/O Type

Description

AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE

data from the SRAM to nonvolatile elements. If AutoStore is not needed, this pin must

be left as No Connect. It must never be connected to ground.

V_CAP

Power Supply

Input

Serial Input. Pin for input of all SPI instructions and data.

SI (I/O0)

SCK

I/O0: When the part is in dual or quad mode, the SI pin becomes I/O0 pin and acts as

input/output.

Input/Output

Serial Clock. Runs at speeds up to a maximum of f_SCK. Serial input is latched at the

rising edge of this clock. Serial output is driven at the falling edge of the clock.

Input

NC

–

Not connected.

RFU

Reserved for future use.

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CY14V101QS

SRAM Read

Device Operation

All reads to nvSRAM are carried out on the SRAM cells at SPI

bus speeds. Read instruction (READ) executes at 40-MHz with

zero cycle latency. It consists of a Read opcode byte followed by

three bytes of address. The data is read out on the data output

pin/pins.

CY14V101QS is a 1-Mbit quad serial nvSRAM memory with a

SONOS FLASH nonvolatile element interleaved with an SRAM

element in each memory cell. All the reads and writes to

nvSRAM happen to the SRAM, which gives nvSRAM the unique

capability to handle infinite writes to the memory. The data in

SRAM is secured by a STORE sequence, which transfers the

Speeds higher than 40 MHz (up to 108 MHz) require Fast Read

instructions: FAST_READ, DOR, QOR, DIOR, and QIOR. The

Fast Read instructions consist of a Fast Read opcode byte, three

bytes of address, and a dummy/mode byte. The data is read out

on the data output pin/pins.

data in parallel to the nonvolatile cells. A small capacitor (V_CAP

)

is used to AutoStore the SRAM data in nonvolatile cells when

power goes down providing power-down data security. The

nonvolatile elements built in the reliable SONOS technology

make nvSRAM the ideal choice for secure data storage.

The device allows burst mode reads. This enables read opera-

tions on consecutive addresses without issuing a new Read

instruction. When the last address in memory is reached in burst

mode, the address rolls over to 0x00000 and the device

continues to read.

The 1-Mbit memory array is organized as 128K words × 8 bits.

The memory can be accessed through a standard SPI interface

(Single mode, Dual mode, and Quad mode) up to clock speeds

of 40-MHz with zero-cycle latency for read and write operations.

This SPI interface also supports 108-MHz operations (Single

mode, Dual mode, and Quad mode) with cycle latency for read

operations only. The device operates as a SPI slave and

supports SPI modes 0 and 3 (CPOL, CPHA = [0, 0] and [1, 1]).

All instructions are executed using Chip Select (CS), Serial Input

(SI), Serial Output (SO), and Serial Clock (SCK) pins in single

and dual modes. Quad mode uses WP and HOLD pins as well

for command, address, and data entry.

The SPI read cycle sequence is defined explicitly in the nvSRAM

Read Write Instructions in “SPI Functional Description” on

page 13.

STORE Operation

STORE operation transfers the data from the SRAM to the

SONOS FLASH nonvolatile cells. The device stores data to the

nonvolatile cells using one of the three STORE operations:

AutoStore, activated on device power-down (requires V_CAP);

Software STORE, activated by a STORE instruction; and

Hardware STORE, activated by the HSB pin. During the STORE

cycle, the SONOS FLASH is first erased followed by

programming of the nonvolatile elements. After a STORE cycle

is initiated, read/write to the device is inhibited until the cycle is

completed.

The device uses SPI opcodes for memory access. The opcodes

support SPI, Dual Data, Dual Addr/Data, Dual I/O, Quad Data,

Quad Addr/Data, and Quad I/O modes for read and write opera-

tions. In addition, four special instructions are included that allow

access to nvSRAM specific functions: STORE, RECALL,

AutoStore Disable (ASDI), and AutoStore Enable (ASEN).

The device has built-in data security features. It provides

hardware and software write-protection through the WP pin and

WRDI instruction respectively. Furthermore, the memory array

block is write-protected through Status register block protect bits.

The HSB signal or the WIP bit in Status Register can be

monitored by the system to detect if a STORE cycle is in

progress. The busy status of nvSRAM is indicated by HSB being

pulled LOW or the WIP bit being set to ‘1’. To avoid unnecessary

nonvolatile STOREs, AutoStore and Hardware STORE opera-

tions are ignored unless at least one write operation has taken

place since the most recent STORE cycle. However, software

initiated STORE cycles are performed regardless of whether a

write operation has taken place.

SRAM Write

All writes to nvSRAM are carried out on the SRAM cells and do

not use any endurance cycles of the SONOS FLASH nonvolatile

memory. This allows you to perform infinite write operations. A

write cycle is initiated through one of the Write instructions:

WRITE, DIW, QIW, DIOW, and QIOW. The Write instructions

consist of a write opcode, three bytes of address, and one byte

of data. Write to nvSRAM is done at SPI bus speed with

zero-cycle latency.

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM, which

automatically stores the SRAM data to the SONOS FLASH

nonvolatile cells during power-down. This STORE makes use of

an external capacitor (V_CAP) and enables the device to safely

STORE the data in the nonvolatile memory when power goes

down.

The device allows burst mode writes. This enables write opera-

tions on consecutive addresses without issuing a new Write

instruction. When the last address in memory is reached in burst

mode, the address rolls over to 0x00000 and the device

continues to write.

During normal operation, the device draws current from V_CCto

charge the capacitor connected to the V_CAPpin. When the

voltage on the V_CCpin drops below V_SWITCHduring power-down,

the device inhibits all memory accesses to nvSRAM and

automatically performs a STORE operation using the charge

from the V_CAPcapacitor. The AutoStore operation is not initiated

if a write cycle has not been performed since last RECALL.

The SPI write cycle sequence is defined explicitly in the nvSRAM

Read Write Instructions in “SPI Functional Description” on

page 13.

Note If a capacitor is not connected to the V_CAPpin, AutoStore

must be disabled by issuing the AutoStore Disable instruction

(Autostore Disable (ASDI) Instruction on page 44). If AutoStore

is enabled without a capacitor on the V_CAPpin, the device

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

attempts AutoStore without sufficient charge to complete the

operation. This will corrupt the data stored in the memory array

along with the serial number and Status Register. Updating them

will be required to resume normal functionality.

Note For successful last data byte STORE, a hardware STORE

should be initiated at least one clock cycle after the last data bit

D0 is received.

Note It is recommended to perform a Hardware STORE only

when the device is in Standby state. Execute-in-place (XIP)

should be exited as well.

Figure 4 shows the connection of the storage capacitor (V_CAP

for AutoStore operation. Refer to DC Specifications on page 46

for the size of the V_CAP

)

.

Upon completion of the STORE operation, the nvSRAM memory

access is inhibited for t_LZHSBtime after HSB pin returns HIGH.

The HSB pin must be left unconnected if not used.

Figure 4. AutoStore Mode

V_CCQ

V_CC

RECALL Operation

A RECALL operation transfers the data stored in the SONOS

FLASH nonvolatile cells to the SRAM cells. A RECALL may be

initiated in two ways: Hardware RECALL, initiated on power-up

and Software RECALL, initiated by a SPI RECALL instruction.

0.1uF

V_CCQ

V_CC

Internally, RECALL is a two-step procedure. First, the SRAM

data is cleared (set to ‘0’). Next, the nonvolatile information is

transferred into the SRAM cells. All memory accesses are

inhibited while a RECALL cycle is in progress. The RECALL

operation does not alter the data in the nonvolatile elements.

CS

V_CAP

Hardware RECALL (Power-Up)

V_SS

During power-up, when V_CCcrosses V_SWITCH, an automatic

RECALL sequence is initiated, which transfers the content of

nonvolatile cells to the SRAM cells. The data would previously

have been stored in nonvolatile cells through a STORE

sequence.

Software STORE Operation

A Power-Up RECALL cycle takes t_FAtime to complete and the

memory access is disabled during this time. The HSB pin is used

to detect the ready status of the device.

Software STORE allows an instruction-based STORE operation.

It is initiated by executing a STORE instruction, irrespective of

whether a write has been previously performed.

A STORE cycle takes t_STOREtime to complete, during which all

the memory accesses to nvSRAM are inhibited. The WIP bit of

the Status Register or the HSB pin may be polled to find the

Ready or Busy status. After the t_STOREcycle time is completed,

the nvSRAM is ready for normal operations.

Software RECALL

Software RECALL allows you to initiate a RECALL operation to

restore the content of the nonvolatile memory to the SRAM. A

Software RECALL is issued by using the RECALL instruction.

A Software RECALL takes t_RECALLtime to complete during

which all memory accesses to nvSRAM are inhibited.

Hardware STORE and HSB Pin Operation

The HSB pin in the device is a dual-purpose pin used to either

initiate a STORE operation or to poll STORE/RECALL

completion status. If a STORE or RECALL is not in progress, the

HSB pin can be driven low to initiate a Hardware STORE cycle.

Disabling and Enabling AutoStore

If the application does not require the AutoStore feature, it can

be disabled by using the ASDI instruction. If this is done, the

nvSRAM does not perform a STORE operation at power-down.

Detecting a low on HSB, nvSRAM will start a STORE operation

after t_DELAYduration. A hardware STORE cycle is only possible

if a write operation has been performed since the last

STORE/RECALL cycle. This allows for optimizing the SONOS

FLASH endurance cycles. All reads and writes to the memory

are inhibited for t_STOREduration. The HSB pin also acts as an

open drain driver (internal 100-kΩ weak pull-up resistor) that is

internally driven LOW to indicate a busy condition when the

STORE/RECALL is in progress.

AutoStore can be re-enabled by using the ASEN instruction.

However, ASEN and ASDI operations require a STORE

operation to make them nonvolatile.

Note The device has AutoStore enabled and 0x00 written in all

cells from the factory.

Note If AutoStore is disabled and V_CAPis not required, then the

V_CAPpin must be left open. The V_CAPpin must never be

connected to ground. The Power-Up RECALL operation cannot

be disabled.

Note After each Hardware and Software STORE operation, HSB

is driven HIGH for a short time (t_HHHD) with standard output

HIGH current and then remains HIGH by an internal 100-k

pull-up resistor.

Document Number: 001-85257 Rev. *G

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CY14V101QS

Serial Clock (SCK)

Quad Serial Peripheral Interface

The serial clock is generated by the SPI master and the commu-

nication is synchronized with this clock after CS goes LOW.

SPI Overview

The SPI is a four-pin interface with Chip Select (CS), Serial Input

(SI), Serial Output (SO), and Serial Clock (SCK) pins. The device

provides serial access to nvSRAM through the SPI interface. The

SPI bus on the device can run at speed up to 108 MHz.

The device enables SPI modes 0 and 3 for data communication.

In both these modes, the inputs are latched by the slave device

on the rising edge of SCK and outputs are issued on the falling

edge. Therefore, the first rising edge of SCK signifies the arrival

of the first bit (MSB) of SPI instruction on the SI pin. Further, all

data inputs and outputs are synchronized with SCK.

The SPI is a synchronous serial interface, which uses clock and

data pins for memory access and supports multiple devices on

the data bus. A device on the SPI bus is activated using the CS

pin.

Data Transmission - SI/SO

The SPI data bus consists of two lines, SI and SO, for serial data

communication. The SI is also referred to as Master Out Slave

In (MOSI) and SO is referred to as Master In Slave Out (MISO).

The master issues instructions to the slave through the SI pin,

while the slave responds through the SO pin. Multiple slave

devices may share the SI and SO lines as described earlier.

The relationship between chip select, clock, and data is dictated

by the SPI mode. This device supports SPI modes 0 and 3. In

both these modes, data is clocked into the nvSRAM on the rising

edge of SCK starting from the first rising edge after CS goes

active.

The SPI protocol is controlled by opcodes. These opcodes

specify the commands from the bus master to the slave device.

After CS is activated, the first byte transferred from the bus

master is the opcode. Following the opcode, any addresses and

data are then transferred. The CS must go inactive after an

operation is complete and before a new opcode can be issued.

The commonly used terms in the SPI protocol are described in

the following sections.

The device has two separate pins for SI and SO, which can be

connected with the master as shown in Figure 5 on page 10.

This SI input signal is used to transfer data serially into the

device. It receives opcode, addresses, and data to be

programmed. Values are latched on the rising edge of serial SCK

clock signal. SI becomes I/O0 - an input and output during

Extended-SPI and DPI/QPI commands for receiving opcodes,

addresses, and data to be written (values latched on rising edge

of serial SCK clock signal) as well as shifting out data (on the

falling edge of SCK).

SPI Master

The SPI master device controls the operations on an SPI bus.

An SPI bus may have only one master with one or more slave

devices. All the slaves share the same SPI bus lines and the

master may select any of the slave devices using the CS pin. All

the operations must be initiated by the master activating a slave

device by pulling the CS pin of the slave LOW. The master also

generates the SCK and all the data transmission on SI and SO

lines are synchronized with this clock.

The SO output signal is used to transfer data serially out of the

device. Data is shifted out on the falling edge of the serial SCK

clock signal. SO becomes I/O1 - an input and output during

Extended-SPI and DPI/QPI commands for receiving opcodes,

addresses, and data to be programmed (values latched on rising

edge of serial SCK clock signal) as well as shifting out data (on

the falling edge of SCK). SO has a Repeater/Bus-Hold circuit

implemented.

SPI Slave

Write-Protect (WP)

The SPI slave device is activated by the master through the Chip

Select line. A slave device gets the SCK as an input from the SPI

master and all the communication is synchronized with this

clock. The SPI slave never initiates a communication on the SPI

bus and acts on the instruction from the master.

In SPI mode, the WP pin when driven low protects against writes

to the Status registers and all data bytes in the memory area that

are protected by the Block Protect bits in the Status registers.

When WP is driven Low, during a WRSR command and while

the Status Register Write Disable (SRWD) bit of the Status

Register is set to a 1, it is not possible to write to the Status and

Configuration Registers. This prevents any alteration of the

Block Protect (BP2, BP1, BP0) and TBPROT bits. As a conse-

quence, all the data bytes in the memory area that are protected

by the Block Protect and TBPROT bits, are protected against

data modification if WP is Low during a WRSR command.

The device operates as an SPI slave and may share the SPI bus

with other SPI slave devices.

Chip Select (CS)

For selecting any slave device, the master needs to pull down

the corresponding CS pin. Any instruction can be issued to a

slave device only while the CS pin is LOW. When the device is

not selected, data through the SI pin is ignored and the serial

output pin (SO) remains in a high-impedance state.

The WP function is not available while in the Quad transfer

mode. The WP function is replaced by I/O2 for input and output

during these modes for receiving opcode, addresses, and data

to be written/programmed as well as shifting out data. WP has

an internal pull-up resistor; and may be left unconnected in the

host system if not used for Quad transfer mode. WP has an

internal 100-kΩ weak pull-up resistor in SPI mode.

Note A new instruction must begin with the falling edge of CS.

Therefore, only one opcode can be issued for each active Chip

Select cycle.

Note It is recommended to attach an external 10-kΩ pull-up

resistor to V_CCQon CS pin.

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CY14V101QS

Hold (HOLD)

Serial Opcode

The Hold (HOLD) signal is used to pause any serial communica-

tions with the device without deselecting the device or stopping

the serial clock.

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

The device uses the standard opcodes for memory accesses. In

addition to the memory accesses, it provides additional opcodes

for the nvSRAM specific functions: STORE, RECALL, AutoStore

Enable, and AutoStore Disable. Refer to Table 2 on page 13 for

details.

The Hold condition starts on the falling edge of the Hold (HOLD)

signal, provided that this coincides with SCK being at the logic

low state. Taking the HOLD signal to the logic low state does not

terminate any background operation in progress (as reflected by

WIP bit set in SR).

Invalid Opcode

During the Hold condition, SO is in high impedance and both the

SI and SCK input are Don't Care. The Hold condition ends on the

rising edge of the Hold (HOLD) signal, provided that this

coincides with the SCK signal being at the logic low state.

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin until the

next falling edge of CS and the SO pin remains tristated.

Instruction

The HOLD function is not available in the Quad transfer mode.

The Hold function is replaced by I/O3 for input and output during

these modes for receiving opcodes, addresses, and data to be

written/programmed as well as shifting out data. The HOLD

signal as an internal pull-up resistor and may be left unconnected

in the host system if not used for Quad transfer mode. HOLD has

an internal 100-kΩ weak pull-up resistor in SPI mode.

The combination of the opcode, address, and mode/dummy

cycles used to issue a command.

Mode Bits

Control bits that follow the address bits. The device uses control

bits to enable execute-in-place (XIP). These bits are driven by

the system controller when they are specified.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

MSB. This is valid for both address and data transmission.

Wait States

Required dummy clock cycles after the address bits or optional

mode bits.

The 1-Mbit serial nvSRAM requires a 3-byte address for any read

or write operation. However, because the address is only 17 bits,

it implies that the first seven bits that are fed in are ignored by

the device. Although these seven bits are ‘don’t care’, Cypress

recommends that these bits are treated as 0s to enable

seamless transition to higher memory densities.

Status Register

The device has one 8-bit Status Register. The bits in the Status

Registers are used to configure the SPI bus. These bits are

described in Table 3 on page 15 and Table 4 on page 15.

Figure 5. System Configuration Using SPI nvSRAM

SPI nvSRAM

Document Number: 001-85257 Rev. *G

Page 10 of 61

PRELIMINARY

CY14V101QS

Dual and Quad I/O Modes

SPI Modes

The device also has the capability to reconfigure the standard

SPI pins to work in dual or quad I/O modes.

The device also has the capability to reconfigure. The device

may be driven by a microcontroller with its SPI peripheral running

in either of the following two modes:

When the part is in the dual I/O mode, the SI pin and SO pin

become the I/O0 pin and I/O1 pin for either opcode, address, and

data (Dual I/O mode) or both the address and data (Dual

Addr/Data Mode) or just the data (Dual Data Mode).

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

For both these modes, the input data is latched in on the rising

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles, is considered. The output data

is available on the falling edge of SCK.

When the part is in the quad I/O mode, the SI pin, SO pin, WP

pin, and HOLD pin become I/O0 pin, I/O1 pin, I/O2 pin, and I/O3

pin for either opcode, address and data (Quad I/O Mode), or both

the address and data (Quad Addr/Data Mode), or just the data

(Quad Data Mode).

The two SPI modes are shown in Figure 6 and Figure 7. The

status of clock when the bus master is in standby state and not

transferring data is:

Table 1. I/O Modes

Command

Input

Address

Input

Data

Input/Output

Protocol

■ SCK remains at ‘0’ for Mode 0

■ SCK remains at ‘1’ for Mode 3

SPI

DPI

SI

SI/SO

The device detects the SPI mode from the status of SCK pin

when the device is selected by bringing the CS pin LOW. If the

SCK pin is LOW when the device is selected, SPI Mode 0 is

assumed and if the SCK pin is HIGH, it works in SPI Mode 3.

I/O[1:0]

SO, SI

I/O[1:0]

SO, SI

I/O[1:0]

SO, SI

I/O[3:0]

QPI

HOLD, WP,

SO, SI

HOLD, WP,

SO, SI

HOLD, WP,

SO, SI

Figure 6. SPI Mode 0

t_CSH

Dual Data Mode

(Dual Out)

I/O[0]

SI

I/O[0]

SI

I/O[1:0] SO, SI

Drive output

Capture input

CS

Dual Address/

Data Mode

(Dual I/O)

I/O[0]

SI

I/O[1:0]

SO, SI

I/O[1:0]

SO, SI

SCK

I/O[3:0]

HOLD, WP,

SO, SI

Quad Data Mode

(Quad Out)

I/O[0]

SI

I/O[0]

SI

X

BI7 BI6 BI5

BI4 BI3 BI2 BI1 BI0

X

SI

Quad Address/

Data Mode

(Quad I/O)

I/O[0]

SI

I/O[3:0]

HOLD, WP,

SO, SI

I/O[3:0]

HOLD, WP,

SO, SI

HI-Z

BO7 BO6 BO5 BO4 BO3 BO2 BO1 BO0

SO

t_CSS

For more details, refer to read and write timing diagrams later in

the datasheet.

Figure 7. SPI Mode 3

t_CSH

Drive output

Capture input

CS

SCK

SI

X

BI7 BI6 BI5

BI4 BI3 BI2

BI1 BI0

X

HI-Z

BO7 BO6 BO5 BO4 BO3 BO2 BO1

SO

t_CSS

Document Number: 001-85257 Rev. *G

Page 11 of 61

PRELIMINARY

CY14V101QS

■ WP and HOLD functionality as defined by Quad Data Width

(QUAD) CR[1]. Pull-ups activated on WP and HOLD if Quad

Data width CR[1] is logic ‘0’.

SPI Operating Features

Power-Up

Power-up is defined as the condition when the power supply is

turned on and V_CCcrosses V_SWITCHvoltage.

Power-Down

At power-down (continuous decay of V_CC), when V_CCdrops from

the normal operating voltage and below the V_SWITCHthreshold

voltage, the device stops responding to any instruction sent to it.

As described earlier, at power-up nvSRAM performs a Power-Up

RECALL operation for t_FAduration during which all memory

accesses are disabled. The HSB pin can be probed to check the

Ready/Busy status of nvSRAM after power-up.

If a write cycle is in progress and the last data bit D0 has been

received when the power goes down, it is allowed t_DELAYtime to

complete the write. After this, all memory accesses are inhibited

and a AutoStore operation is performed (AutoStore is not

performed, if no writes have happened since the last RECALL

cycle). This feature prevents inadvertent writes to nvSRAM from

happening during power-down.

The following are the device status after power-up.

■ SPI I/O Mode

■ Pull-ups activated for HSB

■ SO is tristated

However, to completely avoid the possibility of inadvertent writes

during power-down, ensure that the device is deselected and is

■ Standby power mode if CS pin is high. Active power mode if

CS pin is LOW.

in standby state, and the CS follows the voltage applied on V_CC

.

■ Not in the Hold condition

Active Power Mode and Standby State

■ Status Register state:

When CS is LOW, the device is selected and is in the active

power mode. The device consumes I_CC(I_CC1+ I_CCQ1) current,

as specified in DC Specifications on page 46. When CS is HIGH,

the device is deselected and the device goes into the standby

state time, if a STORE or RECALL cycle is not in progress. If a

STORE/RECALL cycle is in progress, the device goes into the

standby state after the STORE or RECALL cycle is completed.

❐ Write Enable bit is reset to ‘0’

❐ SRWD not changed from previous STORE operation

❐ SNL not changed from previous STORE operation

❐ Block Protection bits are not changed from previous STORE

operation

Document Number: 001-85257 Rev. *G

Page 12 of 61

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CY14V101QS

SPI Functional Description

The device has an 8-bit instruction register. Instructions and their opcodes are listed in Table 2. All instructions, addresses, and data

are transferred with a HIGH to LOW CS transition. The SPI instructions along with WP, HOLD, and HSB pins provide access to all

the functions in nvSRAM.

Table 2. Instruction Set

Instruction

Category

Instruction

Name

Max Frequency

Opcode SPI Dual Out Quad Out Dual I/O Quad I/O DPI

QPI

(MHz)

Write Status

Register

WRSR

RDCR

01h

35h

Yes

–

Yes

108

Read Configu-

ration Register

108

Write Configu-

ration Register

WRCR

RDID

87h

9Fh

9Eh

Yes

–

Yes

–

108

40

Read ID Register

Yes

Fast Read ID

Register

FAST_RDID

108

Write Serial

Number Register

WRSN

RDSN

C2h

C3h

C9h

Yes

–

Yes

108

40

Read Serial

Number Register

Fast Read Serial

Number Register

FAST_RDSN

108

NV Specific Commands

STORE

RECALL

ASEN

8Ch

8Dh

8Eh

Yes

–

Yes

108

RECALL

Autostore Enable

Autostore

Disable

ASDI

8Fh

Yes

–

Mode Bits

–

Yes

108

Mode Bit (Set,

Reset)

Axh,

!Axh

–

Yes

–

Yes

–

Based on their functionality, the SPI instructions are divided into

the following types:

❐ Status Register: RDSR, WRSR

❐ Identification: RDID, FAST_RDID

❐ Serial Number: RDSN, WRSN, FAST_RDSN

■ Control instructions:

■ nvSRAM Special instructions:

❐ STORE: STORE

❐ Write-protection: WREN, WRDI instructions

❐ I/O modes: DPIEN, QPIEN, DQPIDI

❐ RECALL: RECALL

❐ Enable/Disable: ASEN, ASDI

■ Memory Read instructions:

❐ Memory access: READ, FAST_READ, DOR, QOR, DIOR,

QIOR

Note The instruction waveforms shown in the following sections

do not incorporate the effects of pull-ups on WP (I/O2), HOLD

(I/O3) and Repeater/Bus-Hold circuitry on SO.

■ Memory Write instructions:

❐ Memory access: WRITE, DIW, QIW, DIOW, QIOW

Note Instruction Opcode C5h, 1Eh, C8h, CEh, CBh, CCh, CDh

are Cypress reserved opcodes and change the configuration of

the device. If any one of these opcodes are erroneously entered,

a software reset (66h, 99h) is required to return the device back

to correct configuration. Otherwise, the device will not behave

correctly.

■ System Resources instructions:

❐ Software Reset: RSTEN, RESET

❐ Power modes: HIBEN, SLEEP, EXSLP

■ Register instructions:

❐ Configuration Register: RDCR, WRCR

Document Number: 001-85257 Rev. *G

Page 14 of 61

PRELIMINARY

CY14V101QS

Status Register

The device has one Status Register, which is listed in Table 3

along with its bit descriptions. The bit format in the Status

Register shows whether the bit is read only (R) or can be written

to as well (W/R). The only exception to this is the serial number

lock bit (SNL). The serial number can be written using the WRSN

instruction multiple times while SNL is still '0'. When set to '1', this

bit prevents any modification to the serial number. This bit is

factory-programmed to '0' and can only be written to once. After

this bit is set to '1', it can never be cleared to '0'.

Table 3. Status Register Format and Bit Definitions

Default

State

Bit Field Name

Function

Type

R/W

Description

1 = Locks state of SR when WP is low by ignoring WRSR

command

0 = No protection, even when WP is low

Status Register

Write Disable

7

SRWD

NV

R/W

0

Serial Number

Lock

6

5

SNL

OTP

NV

R/W

0

Locks the Serial Number

Configures Start

of Block

1 = BP starts at bottom (Low address)

0 = BP starts at top (High address)

TBPROT

4

3

2

BP2

BP1

BP0

NV

R/W

0

Protects selected range of Block from Write, Program or

Erase

Block Protection

1 = Device accepts Write Registers(WRSR), Write, program

or erase commands

0 = Device ignores Write Registers (WRSR), write, program

or erase commands

This bit is not affected by WRSR, only WREN and WRDI

commands affect this bit

Write Enable

Latch

1

0

WEL

WIP

V

R

0

1 = Device Busy, a Write Registers (WRSR), program, erase

or other operation is in progress

0 = Ready Device is in standby state and can accept

commands

Work in Progress

Status Register Write Disable (SRWD) SR[7]

command. If SRWD is ‘0’, WP has no effect and the SRWD bits

may be changed by the WRSR command.

Places the device in the Hardware Protected mode when this bit

is set to '1' and the WP input is driven LOW. In this mode, all the

SRWD bits except WEL, become read-only bits and the Write

Registers(WRSR)commandisnolongeracceptedforexecution.

If WP is HIGH, the SRWD bits may be changed by the WRSR

Note: WP internally defaults to logic ‘0’, if Quad bit CR[1] in

Configuration register is set. If SRWD is set to logic ‘1’, protection

cannot be changed till Quad bit CR[1] is reset to logic ‘0’.

Table 4. SRWD, WP, WEL and Protection

Unprotected

Blocks

Status Register

(except WEL)

SRWD

WP

WEL

Protected Blocks

X

0

Protected

0

1

X

1

Protected

Writable

Protected

Writable

Low

High

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

Serial Number Lock (SNL) SR[6]

Block Protection (BP2, BP1, BP0) SR[4:2]

When set to '1', this bit prevents any modification to the serial

number. This bit is factory programmed to '0' and can only be

written to once. After this bit is set to '1', it can never be cleared

to '0'.

These bits define the memory array area to be

software-protected against write commands. The BP bits are

nonvolatile. When one or more of the BP bits is set to '1', the

relevant memory area is protected against write, program, and

erase.

Top or Bottom Protection (TBPROT) CR[5]

The Block Protect bits (Status Register bits BP2, BP1, BP0) in

combination with the TBPROT bit can be used to protect an

address range of the memory array. The size of the range is

determined by the value of the BP bits and the upper or lower

starting point of the range is selected by the TBPROT bit of the

status register.

This bit defines the operation of the Block Protection bits BP2,

BP1, and BP0.The desired state of TBPROT must be selected

during the initial configuration of the device during system

manufacture.

Table 5. Upper Array Start of Protection (TBPROT = 0)

Status Register Content

Protection Fraction of Memory

Address Range

Array

BP2

0

BP1

0

BP0

0

None

0

1

0

1

0

1

0

1

0

1

0

1

Upper 64th

Upper 32nd

Upper 16th

Upper 8th

Upper 4th

Upper Half

All Sectors

0x1F800 - 0x1FFFF

0x1F000 - 0x1FFFF

0x1E000 - 0x1FFFF

0x1C000 - 0x1FFFF

0x18000 - 0x1FFFF

0x10000 - 0x1FFFF

0x00000 - 0x1FFFF

Table 6. Lower Array Start of Protection (TBPROT = 1)

Status Register Content

Protection Fraction of Memory

Array

Address Range

BP2

0

BP1

0

BP0

0

None

0

1

0

1

0

1

0

1

0

1

0

1

Lower 64th

Lower 32nd

Lower 16th

Lower 8th

Lower 4th

Lower Half

All Sectors

0x00000 - 0x007FF

0x00000 - 0x00FFF

0x00000 - 0x01FFF

0x00000 - 0x03FFF

0x00000 - 0x07FFF

0x00000 - 0x0FFFF

0x00000 - 0x1FFFF

cleared to 0 at the end of any successful write to registers,

STORE, RECALL, program or erase operation – note it is not

cleared after write operations to memory macro. After a

power-down/power-up sequence, hardware reset, or software

reset, the Write Enable Latch is set to ‘0’. The WRSR command

does not affect this bit.

Write Enable (WEL) SR[1]

The WEL bit must be set to '1' to enable program, write, or erase

operations as a means to provide protection against inadvertent

changes to memory or register values. The Write Enable

(WREN) command execution sets the Write Enable Latch to a ‘1’

to allow any write commands to execute afterwards. The Write

Disable (WRDI) command sets the Write Enable Latch to 0 to

prevent all write commands from execution. The WEL bit is

Note: AutoStore, power up RECALL and Hardware STORE

(HSB based) are not affected by WEL bit.

Document Number: 001-85257 Rev. *G

Page 16 of 61

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CY14V101QS

Table 7. Instructions Requiring WEL Bit Set

Instruction Description

Instruction Name Opcode

Memory Write

Write

WRITE

DIW

02h

A2h

32h

A1h

D2h

Dual Input Write

Quad Input Write

Dual I/O Write

QIW

DIOW

QIOW

Quad I/O Write

Register Commands

Write Status Register

WRSR

WRCR

WRSN

01h

87h

C2h

Write Configuration Register

Write Serial Number Register

NV specific Commands

STORE

RECALL

ASEN

8Ch

8Dh

8Eh

8Fh

RECALL

AutoStore Enable

AutoStore Disable

ASDI

Work In Progress (WIP) SR[0]

tions to the Status Register must be secured by performing a

Software STORE operation.

Indicates whether the device is performing a program, write,

erase operation, or any other operation, during which a new

operation command will be ignored. When the bit is set to '1', the

device is busy performing a background operation. While WIP is

‘1’, only Read Status (RDSR) command may be accepted. When

the WIP bit is cleared to '0', no operation is in progress. This is a

read-only bit.

Configuration Register

QPI nvSRAM has one Configuration register which is listed in

Table 8 along with its bit descriptions. The bit format in the

Configuration register shows whether the bit is read only (R) or

can be written to as well (W/R). The Configuration register

controls interface functions.

All values written to SR are saved to nonvolatile memory only

after a STORE operation. If AutoStore is disabled, any modifica-

Table 8. Configuration Register

Bit

7

Field Name

RFU

Function

Reserved

Type R/W Default State

Description

Reserved for future use

1: Quad; 0: Dual or Serial

Reserved for future use

–

0

1

0

6

RFU

Reserved

–

V

–

5

RFU

Reserved

4

RFU

Reserved

–

3

RFU

Reserved

–

2

RFU

Reserved

–

1

QUAD

RFU

Puts device in Quad Mode

Reserved

R/W

–

0

Quad Data Width (QUAD) CR[1]

QUAD I/O Read, QUAD Input Write, QUAD I/O Write, and all

QUAD SPI commands. The QUAD bit is non-volatile.

When set to ‘1’, this bit switches the data width of the device to

four bits i.e. WP becomes I/O2 and HOLD becomes I/O3. The

WP and HOLD inputs are not monitored for their normal

functions and HOLD is internally taken to be inactive while WP

is internally taken to be active. The commands for Serial, Dual

Output, and Dual I/O Read still function normally but, there is no

need to drive WP and HOLD inputs for those commands when

switching between commands using different data path widths.

The QUAD bit must be set to ‘1’ when using QUAD Out Read,

Note To set the Quad bit, 0x42 must be written to the Configu-

ration register. Similarly, to reset the Quad bit, 0×40 must be

written to the Configuration register. Any other data combination

will change the configuration of the device and make it unusable.

Note: When Quad bit CR[1] in Configuration register is set, WP

internally defaults to logic ‘0’ and HOLD internally defaults to

logic ‘1’.

Document Number: 001-85257 Rev. *G

Page 17 of 61

PRELIMINARY

CY14V101QS

Write Enable (WREN) Instruction

SPI Control Instructions

On power-up, the device is always in the Write Disable state. The

write instructions and nvSRAM special instruction must therefore

be preceded by a Write Enable instruction. If the device is not

write enabled (WEL = ‘0’), it ignores the write instructions and

returns to the standby state when CS is brought HIGH. This

instruction is issued following the falling edge of CS and sets the

WEL bit of the Status Register to ‘1’. The WEL bit defaults to ‘0’

on power-up.

Write Disable (WRDI) Instruction

The Write Disable instruction disables all writes by clearing the

WEL bit to ‘0’ to protect the device against inadvertent writes.

This instruction is issued after the falling edge of CS followed by

opcode for WRDI instruction. The WEL bit is cleared on the rising

edge of CS.

Figure 8. WRDI Instruction in SPI Mode

Note The WEL bit is cleared to 0 at the end of any successful

write to registers, STORE, RECALL, ASEN, and ASDI operation.

It is not cleared after write operations to memory macro.

CS

Figure 11. WREN Instruction in SPI Mode

SCK

CS

0

1

0

X

SI (I/O0)

SCK

HI-Z

SO (I/O1)

Opcode (04h)

SI (I/O0)

0

1

0

X

HI-Z

SO (I/O1)

Figure 9. WRDI Instruction in DPI Mode

Opcode (06h)

CS

Figure 12. WREN Instruction in DPI Mode

SCK

HI-Z

CS

HI-Z

0

1

0

SI (I/O0)

SCK

HI-Z

SO (I/O1)

HI-Z

SI (I/O0)

0

1

0

1

Opcode (04h)

HI-Z

SO (I/O1)

Figure 10. WRDI Instruction in QPI Mode

Opcode (06h)

CS

Figure 13. WREN Instruction in QPI Mode

SCK

HI-Z

CS

HI-Z

0

1

0

SI (I/O0)

SCK

HI-Z

SO (I/O1)

HI-Z

SI (I/O0)

SO (I/O1)

0

1

0

WP (I/O2)

HI-Z

HOLD (I/O3)

WP (I/O2)

Opc.

(04h)

HOLD (I/O3)

Opc.

(06h)

Document Number: 001-85257 Rev. *G

Page 18 of 61

PRELIMINARY

CY14V101QS

Figure 17. Enable Quad I/O in DPI Mode

Enable DPI (DPIEN) Instruction

DPIEN enables the Dual I/O mode wherein opcode, address,

mode bits, and data is sent over I/O0 and I/O1.

CS

SCK

Figure 14. Enable Dual I/O Instruction in SPI Mode

CS

HI-Z

0

1

0

1

0

SI (I/O0)

SO (I/O1)

SCK

SI (I/O0)

0

1

0

1

X

Opcode (38h)

HI-Z

SO (I/O1)

Opcode (37h)

Enable SPI (SPIEN) Instruction

SPIEN disables Dual I/O or Quad I/O modes and returns the

device in SPI mode. SPIEN instruction does not reset the Quad

bit CR[1] in Configuration register.

Figure 15. Enable Dual I/O Instruction in QPI Mode

Figure 18. Enable SPI Instruction in DPI Mode

CS

SCK

HI-Z

SI (I/O0)

SO (I/O1)

1

0

1

0

HI-Z

1

SI (I/O0)

SO (I/O1)

WP (I/O2)

Opcode (FFh)

HOLD (I/O3)

Figure 19. Enable SPI Instruction in QPI Mode

Opc.

(37h)

CS

Enable QPI (QPIEN) Instruction

SCK

QPIEN enables QPI mode wherein opcode, address,

dummy/mode bits and data is sent over I/O0, I/O1, I/O2, and

I/O3. QPIEN instruction does not set the Quad bit CR[1] in

Configuration register. WRCR instruction to set Quad bit CR[1]

must therefore proceed QPIEN instruction.

HI-Z

1

SI (I/O0)

SO (I/O1)

Note Disabling QPI mode does not reset Quad bit CR[1].

Figure 16. Enable Quad I/O instruction in SPI Mode

WP (I/O2)

CS

HOLD (I/O3)

Opc.

(FFh)

SCK

0

1

0

X

SI (I/O0)

HI-Z

SO (I/O1)

Opcode (38h)

Document Number: 001-85257 Rev. *G

Page 19 of 61

PRELIMINARY

CY14V101QS

READ Instruction

SPI Memory Read Instructions

READ instruction can be used in SPI, Dual I/O (DPI) or Qua I/O

(QPI) Modes. In SPI Mode, opcode and address bytes are trans-

mitted through SI pin, one bit per clock cycle. At the falling edge

of SCK of the last address cycle, the data (D7-D0) at the specific

address is shifted out on SO pin one bit per clock cycle starting

with D7.

Read instructions access the memory array. These instructions

cannot be used while a STORE or RECALL cycle is in progress.

A STORE cycle in progress is indicated by the WIP bit of the

Status Register and the HSB pin.

Read Instructions

In DPI Mode, opcode and address bytes are transmitted through

I/O1 and I/O0 pins, two bits per clock cycle. At the falling edge of

SCK after the last address cycle, the data (D7-D0) at the specific

address is shifted out two bits per clock cycle starting with D7 on

I/O1 and D6 on I/O0. In QPI Mode, opcode and address bytes

are transmitted through I/O3, I/O2, I/O1, and I/O0 pins, four bits

per clock cycle. At the falling edge of SCK of the last address

cycle, data (D7-D0) at the specific address is shifted out four bits

per clock cycle starting with D7 on I/O3, D6 on I/O2, D5 on I/O1,

and D4 on I/O0.

The device performs the read operations when read instruction

opcodes are given on the SI pin and provides the read output

data on the SO pin for SPI mode or the I/O1, I/O0 pins for Dual

I/O Mode or the I/O3, I/O2, I/O1, and I/O0 pins for Quad I/O

Mode. After the CS pin is pulled LOW to select a device, the read

opcode is entered followed by three bytes of address. The device

contains a 17-bit address space for 1-Mbit configuration.

The most significant address byte contains A16 in bit 0 and other

bits as 'don't care'. Address bits A15 to A0 are sent in the

following two address bytes. After the last address bit is trans-

mitted, the data (D7-D0) at the specific address is shifted out on

the falling edge of SCK starting with D7. The reads can be

performed in burst mode if CS is held LOW.

The device automatically increments to the next higher address

after each byte of data is output. When the last data memory

address (0x1FFFF) is reached, the address rolls over to 0x00000

and the device continues the read instruction. The read

operation is terminated by driving CS HIGH at any time during

data output.

Note The Read instruction operates up to maximum of 40-MHz

frequency. In Dual and Quad I/O modes, a wait state (dummy

cycles) is required after the address bytes. This allows the device

to pre-fetch the first byte and start the pipeline flowing.

Figure 20. READ Instruction in SPI Mode

CS

SCK

0

1

A23 A22 A21 Am-3 A3

A2

A1

A0

X

SI (I/O0)

SO (I/O1)

D7

D6

D5

D4

D3

D2

D1

D0

Opcode (03h)

Address

Read data

Figure 21. Burst Mode READ Instruction in SPI Mode

CS

SCK

SI (I/O0)

SO (I/O1)

0

1

A23 A22 A21 Am-3 A3

A2

A1

A0

X

HI-Z

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

Opcode (03h)

Address

Read Data

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Figure 22. READ Instruction in DPI Mode

CS

SCK

HI-Z

0

1

A22 A20

A23 A21

A2

A3

A0

A1

D6

D7

D4

D5

D2

D3

D0

D1

SI (I/O0)

SO (I/O1)

D

M

Y

Opcode (03h)

Address

Read Data

Figure 23. READ Instruction in QPI Mode

by the 3 address bytes and then a mode byte. At the next falling

edge of the SCK, data from the specific address is shifted out on

the SO pin for SPI Mode or the I/O1, I/O0 pins for Dual I/O Mode

or the I/O3, I/O2, I/O1, and I/O0 pins for Quad I/O Mode. The first

byte specified can be at any location. The device automatically

increments to the next higher address after each byte of data is

output. The entire memory array can therefore be read with a

single fast read instruction. When the highest address in the

memory array is reached, the address counter rolls over to

starting address 0x00000 and allows the read sequence to

continue indefinitely. The fast read instructions are terminated by

driving CS HIGH at any time during data output.

CS

SCK

HI-Z

0

1

0

A20

A21

A22

A23

A0

A1

A2

A3

D4

D0

D1

D2

D3

SI (I/O0)

HI-Z

SO (I/O1)

D5

D6

D7

Note These instructions operate up to maximum of 108-MHz SPI

frequency.

WP (I/O2)

FAST_READ Instruction

HOLD (I/O3)

FAST_READ instruction can be used in SPI, Dual I/O (DPI) or

Quad I/O (QPI) Modes. In SPI Mode, opcode, address and mode

byte are transmitted through SI pin, one bit per clock cycle. At

the falling edge of SCK of the last mode byte cycle, the data

(D7-D0) from the specific address is shifted out on SO pin, one

bit per clock cycle starting with D7. In DPI Mode, opcode,

address and mode byte are transmitted through I/O1 and I/O

pins, two bits per clock cycle. At the falling edge of the last mode

cycle, the data (D7-D0) from the specific address is shifted out

two bits per clock cycle starting with D7 on I/O1 and D6 on I/O0.

In QPIO Mode, opcode, and address bytes are transmitted

through I/O3, I/O2, I/O1, and I/O0 pins, four bits per clock cycle.

At the falling edge of SCK of the last mode cycle, the data

(D7-D0) from the specific address is shifted out, four bits per

clock cycle starting with D7 on I/O3, D6 on I/O2, D5 on I/O1, and

D4 on I/O0.

D

M

Y

Opc.

(03h)

Read

Data

Address

Note: Quad bit CR[1] must be logic ‘1’ before executing the

READ instruction in QPI mode.

Fast Read Instructions

The fast read instructions allow you to read memory at SPI

frequency up to 108 MHz (max). The instruction is similar to the

normal read instruction with the addition of a wait state in all I/O

configurations; a mode byte must be sent after the address and

before the first data is sent out. This allows the device to

pre-fetch the first byte and start the pipeline flowing. The host

system must first select the device by driving CS LOW, followed

Figure 24. FAST_READ Instruction in SPI Mode

CS

SCK

0

1

A23 A22

A1

A0

M7

M6

M1

M0

X

SI (I/O0)

SO (I/O1)

HI-Z

D7

D6

D5

D4

D3

D6

D5

D4

D3

D2

D1

D0

Opcode (0Bh)

Address

Mode Byte

Read data

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Figure 25. FAST_READ Instruction in DPI Mode

CS

SCK

HI-Z

0

1

A22 A20

A23 A21

A2

A3

A0

A1

M6

M7

M4

M5

M2

M3

M0

M1

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI (I/O0)

SO (I/O1)

HI-Z

Opcode (0Bh)

Address

Mode Byte

Read Data

Figure 26. FAST_READ Instruction in QPI Mode

DOR Instruction

DOR instruction is used in Dual Data Mode, which is part of

Extended SPI Read commands. In Dual Data Mode, opcode,

address and mode byte are transmitted through SI pin, one bit

per clock cycle. At the falling edge of SCK of the last mode cycle,

the pins are reconfigured as SO becoming I/O1, and SI

becoming I/O0. The data (D7-D0) from the specified address is

shifted out on I/O1, and I/O0 pins two bits per clock cycle starting

with D7 on I/O1, and D6 on I/O0.

CS

SCK

HI-Z

0

O5

0

1

0

1

A20

A21

A22

A23

A0

A1

A2

A3

M4

M5

M6

M7

M0

M1

M2

M3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (I/O0)

HI-Z

SO (I/O1)

WP (I/O2)

QOR Instruction

QOR instruction is used in Quad Data Mode, which is part of

Extended SPI Read commands. In Quad Data Mode, opcode,

address and mode byte are transmitted through SI pin, one bit

per clock cycle. At the falling edge of SCK of the last mode cycle,

the pins are reconfigured as HOLD becoming I/O3, WP

becoming I/O2, SO becoming I/O1, and SI becoming I/O0. The

data (D7-D0) from the specified address is shifted out on I/O3,

I/O2, I/O1, and I/O0 pins four bits per clock cycle starting with D7

on I/O3 and D6 on I/O2, D5 on I/O1, and D4 on I/O0.

0

HOLD (I/O3)

Opc.

(0Bh)

Mode

Byte

Address

Read data

Note Quad bit CR[1] must be logic ‘1’ before executing the QOR

instruction.

Figure 27. DOR Instruction

CS

SCK

HI-Z

0

1

A23 A22

A1

A0

M7

M6

M1

M0

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI (I/O0)

SO (I/O1)

HI-Z

Opcode (3Bh)

Address

Mode Byte

Read data

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Figure 28. QOR Instruction

CS

SCK

HI-Z

X

0

1

A23 A22

A1

A0

M7

M6

M1

M0

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (I/O0)

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

HI-Z

Opcode (6Bh)

Address

Mode Byte

Read Data

DIOR Instruction

is then transmitted into the part through I/O1 and I/O0 pins, 2 bits

per clock cycle, starting with A23 on I/O1 and A22 on I/O0, until

three bytes worth of address is input. The data (D7-D0) at the

specific address is shifted out on I/O1, and I/O0 pins two bits per

clock cycle starting with D7 on I/O1, and D6 on I/O0.

DIOR instruction is used in Dual Addr/Data Mode, which is part

of Extended SPI Read commands. In Dual Addr/Data Mode,

opcode is transmitted through SI pin, one bit per clock cycle.

After the last bit of the opcode, the pins are reconfigured as

HOLD SO becoming I/O1, and SI becoming I/O0. The address

Figure 29. DIOR Instruction

CS

SCK

HI-Z

1

0

1

A22 A20

A23 A21

A2

A3

A0

A1

M6

M7

M4

M5

M2

M3

M0

M1

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI (I/O0)

SO (I/O1)

Opcode (BBh)

Address

Mode Byte

Read Data

QIOR Instruction

starting with A23 on I/O3, A22 in I/O2, A21 on I/O1 and A20 on

I/O0, until three bytes worth of address is input. The data (D7-D0)

at the specific address is shifted out on I/O3, I/O2, I/O1, and I/O0

pins four bits per clock cycle starting with D7 on I/O3 and D6 on

I/O2, D5 on I/O1, and D4 on I/O0.

QIOR instruction is used in Quad Addr/Data Mode, which is part

of Extended SPI Read commands. In Quad Addr/Data Mode,

opcode is transmitted through SI pin, one bit per clock cycle.

After the last bit of the opcode, the pins are reconfigured as

HOLD becoming I/O3, WP becoming I/O2, SO becoming I/O1,

and SI becoming I/O0. The address is then transmitted into the

part through I/O3, I/O2, I/O1 and I/O0 pins, 4 bits per clock cycle,

Note Quad bit CR[1] must be logic ‘1’ before executing the QIOR

instruction.

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Figure 30. QIOR Instruction

CS

SCK

HI-Z

1

A20

A21

A22

A23

A0

A1

A2

A3

M4

M5

M6

M7

M0

M1

M2

M3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (I/O0)

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

Mode

Byte

Opcode (EBh)

Address

Read Data

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resumes writes. The same operation is true if a burst write is

initiated within a write-protected block.

Write Instructions

The device performs the write operations when write instruction

opcodes along with write data are given on the SI pin for SPI

Mode or the I/O1, I/O0 pins for Dual I/O Mode or the I/O3, I/O2,

I/O1, and I/O0 pins for Quad I/O Mode. To perform a write

operation, if the device is write disabled, then the device must be

first write enabled through the WREN instruction. When the

writes are enabled (WEL = '1'), WRITE instruction is issued after

the falling edge of CS. nvSRAM enables writes to be performed

in bursts which can be used to write consecutive addresses

without issuing a new Write instruction. If only one byte is to be

written, the CS pin must be driven HIGH after the D0 (LSB of

data) is transmitted. However, if more bytes are to be written, CS

pin must be held LOW and the address is incremented automat-

ically. The data bytes on the input pin(s) are written in successive

addresses. When the last data memory address (0x1FFFF) is

reached, the address rolls over to 0x00000 and the device

continues to write.

Note These instructions operate up to a maximum of 108-MHz

frequency.

After the CS pin is pulled LOW to select a device, the write

opcode is followed by three bytes of address. The device has a

17-bit address space for 1-Mbit configuration. The most signif-

icant address byte contains A16 in bit 0 and the remaining bits

as 'don't care'. Address bits A15 to A0 are sent in the following

two address bytes. Immediately after the last address bit is trans-

mitted, the data (D7-D0) is transmitted through the input line(s).

This command can be used in SPI, DPI or QPI Modes.

WRITE Instruction

WRITE instruction can be used in SPI, DPI, or QPI Modes. In SPI

Mode, opcode, address bytes and data bytes are transmitted

through SI pin, one bit per clock cycle starting with D7. In DPI

Mode, opcode, address bytes and data bytes are transmitted

through I/O1 and I/O pins, two bits per clock cycle starting with

D7 on I/O1 and D6 on I/O0. In QPI Mode, opcode, address bytes,

and data bytes are transmitted through I/O3, I/O2, I/O1, and I/O0

pins, four bits per clock cycle starting with D7 on I/O3, D6 on I/O2,

D5 on I/O1, and D4 on I/O0.

Note The WEL bit in the Status Register does not reset to '0' on

completion of a Write sequence to the memory array.

Note When a burst write reaches a protected block address, it

continues incrementing the address into the protected space but

does not write any data to the protected memory. If the address

rolls over and takes the burst write to unprotected space, it

Figure 31. WRITE Instruction in SPI Mode

CS

SCK

0

1

0

A23 A22 A21 Am-3 A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

X

SI (I/O0)

SO (I/O1)

Opcode (02h)

Address

Write Data

Figure 32. Burst WRITE Instruction in SPI Mode

CS

SCK

0

1

0

A23 A22 A21 Am-3 A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

X

SI (I/O0)

SO (I/O1)

HI-Z

Opcode (02h)

Address

Write data

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Figure 33. WRITE Instruction in DPI Mode

CS

SCK

HI-Z

0

1

A22 A20

A23 A21

A2

A3

A0

A1

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

SI (I/O0)

SO (I/O1)

HI-Z

D1

Opcode (02h)

Address

Write Data

Figure 34. WRITE Instruction in QPI Mode

Note: Quad bit CR[1] must be logic ‘1’ before executing the

WRITE instruction in QPI mode.

CS

DIW Instruction

DIW Instruction can be used in Dual Data Mode, which is part of

Extended SPI Write commands. In Dual Data Mode, opcode,

and address bytes are transmitted through SI pin, one bit per

clock cycle. Immediately after the last address bit is transmitted,

the pins are reconfigured as SO becoming I/O1, and SI

becoming I/O0, and the data (D7-D0) is transmitted into the I/O1,

and I/O0 pins, 2 bits per clock cycle, starting with D7 on I/O1 and

D6 on I/O0.

SCK

HI-Z

0

1

0

A20

A21

A22

A23

A0

A1

A2

A3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (I/O0)

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

Opc.

(02h)

Address

Write Data

Figure 35. DIW Instruction

CS

SCK

SI (I/O0)

SO (I/O1)

HI-Z

1

0

1

A23 A22

A1

A0

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

X

0

HI-Z

Opcode (A2h)

Address

Write Data

QIW Instructions

becoming I/O2, SO becoming I/O1, and SI becoming I/O0, and

the data (D7-D0) is transmitted into the I/O3 I/O2, I/O1, and I/O0

pins, 4 bits per clock cycle, starting with D7 on I/O3 and D6 on

I/O2, D5 on I/O1, and D4 on I/O0.

QIW Instruction can be used in Quad Data Mode, which is part

of Extended SPI Write commands. In Quad Data Mode, opcode,

and address bytes are transmitted through SI pin, one bit per

clock cycle. Immediately after the last address bit is transmitted,

the pins are reconfigured as HOLD becoming I/O3, WP

Note Quad bit CR[1] must be logic ‘1’ before executing the QIW

instruction.

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Figure 36. QIW Instruction

CS

SCK

HI-Z

0

1

0

A23 A22

A1

A0

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (I/O0)

X

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

HI-Z

Opcode (32h)

Address

Write Data

DIOW Instruction

the address is transmitted into the part through I/O1 and I/O0

pins, 2 bits per clock cycle, starting with A23 on I/O1, A22 on

I/O0, until three bytes worth of address is input. After the last

address bits are transmitted, the data (D7-D0) is transmitted into

the part through I/O1 and I/O0 two bits per clock cycle starting

with D7 on I/O1 and D6 on I/O0.

DIOW Instruction can be used in Dual Addr/Data Mode, which is

part of Extended SPI Write commands. In Dual Addr/Data Mode,

opcode is transmitted through SI pin, one bit per clock cycle.

Immediately after the last opcode bit is transmitted, the pins are

reconfigured as SO becoming I/O1, and SI becoming I/O0, and

Figure 37. DIOW Instruction

CS

SCK

HI-Z

1

0

1

A22 A20

A23 A21

A2

A3

A0

A1

D6

D7

D4

D5

D2

D3

D0

D1

D6

D7

D4

D5

D2

D3

D0

D1

SI (I/O0)

SO (I/O1)

X

HI-Z

Opcode (A1h)

Address

Write Data

QIOW Instruction

is transmitted into the part through I/O3, I/O2, I/O1 and I/O0 pins,

4 bits per clock cycle, starting with A23 on I/O3, A22 in I/O2, A21

on I/O1, and A20 on I/O0, until three bytes worth of address is

input. After the last address bits are transmitted, the data

(D7-D0) is transmitted into the part through I/O3, I/O2, I/O1 and

I/O0 four bits per clock cycle starting with D7 on I/O3, D6 on I/O2,

D5 on I/O1, and D4 on I/O0.

QIOW instruction can be used in Quad Addr/Data Mode, which

is part of Extended SPI Write commands. In Quad Addr/Data

Mode, opcode is transmitted through SI pin, one bit per clock

cycle. Immediately after the last opcode bit is transmitted, the

pins are reconfigured as HOLD becoming I/O3, WP becoming

I/O2, SO becoming I/O1, and SI becoming I/O0, and the address

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Note Quad bit CR[1] must be logic ‘1’ before executing the QIOW

instruction.

Figure 38. QIOW Instruction

CS

SCK

HI-Z

1

0

A20

A21

A22

A23

A0

A1

A2

A3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

SI (I/O0)

X

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

HI-Z

Opcode (D2h)

Address

Write Data

Execute-In-Place (XIP)

may be high impedance – it is often used by the microcontrollers

to turn the bus around for read data. If the Mode bits equal Exh,

then the device is set to be/remain in read Mode and the next

address can be entered without the opcode, as shown in figure

below; thus, eliminating some cycles for the opcode sequence.

If the Mode bits equal Fxh, then the XIP mode is reset and the

device expects an opcode after the end of the current trans-

action.

Execute-in-place (XIP) mode allows the memory to perform a

series of reads beginning at different addresses without having

to load the command code for every read. This improves random

access time and eliminates the need to shadow code onto RAM

for fast execution. The read commands supported in XIP mode

are FAST_READ (in SPI, DPI, and QPI mode), DOR, DIOR,

QOR and QIOR.

XIP can be entered or exited during these commands at any time

and in any sequence. If it is necessary to perform another

operation, not supported by XIP, such as a write, then XIP must

be exited before the new command code is entered for the

desired operation.

XIP mode for these commands is Set or Reset by entering the

Mode bits. The upper nibble (bits 7-4) of the Mode bits control

the length of the next afore mentioned read command through

the inclusion or exclusion of the first byte instruction code. The

lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”) and

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Figure 39. XIP for SPI Mode and FAST_READ Instruction (0Bh)

CS

SCK

0

1

A23 A22

A1

A0

1

0

x

A23 A22

HI-Z

A0

1

SI (I/O0)

SO (I/O1)

X

HI-Z

D7

D6

D5

D0

D7

D0

D7

D6

D0

D7

D0

Read Data

(n Bytes)

Opcode (0Bh)

Address

XIP Mode (Axh)

(Begin)

Address

XIP Mode (FFh)

(End)

Read Data

Figure 40. XIP for QPI Mode and FAST_READ Instruction (0Bh)

CS

SCK

HI-Z

0

1

0

1

A20

A21

A22

A23

A0

A1

A2

A3

0

1

0

1

x

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

A20

A21

A22

A23

A0

A1

A2

A3

1

D4

D5

D6

D7

D0

D4

D5

D6

D7

D0

SI (I/O0)

SO (I/O1)

HI-Z

0

D1

D2

D3

D1

D2

D3

HI-Z

0

WP (I/O2)

HI-Z

0

HOLD (I/O3)

Mode

Byte

(Axh)

Mode

Byte

(FFh)

(End)

Opc.

(0Bh)

Read Data

(n Bytes)

Address

Read Data

(Begin)

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Note: Any command other than RESET following the RSTEN

command, will clear the reset enable condition and prevent a

later RESET command from being recognized.

System Resources Instructions

Software Reset (RESET) Instruction

Note: If WIP (SR[0]) bit is high and the RSTEN/RESET

instruction is entered, the device ignores the RSTEN/RESET

instruction.

RESET instruction resets the whole device and makes it ready

to receive commands. The I/O mode is configured to SPI. All

nonvolatile registers or nonvolatile register bits maintain their

values. All volatile registers or volatile register bits default to logic

‘0’. It takes t_RESETtime to complete. No STORE/RECALL opera-

tions are performed. To initiate the software reset process, the

reset enable (RSTEN) instruction is required. This ensures

protection against any inadvertent resets. Thus software reset is

a sequence of two commands.

Note The functionalities of WP and HOLD are controlled by the

Quad bit CR[1] in Configuration register. If Quad bit is set to logic

‘1’, WP and HOLD are configured as I/O2 and I/O3 respectively.

Otherwise, WP and HOLD functionality is configured.

Table 9 summarizes the device’s state after software reset.

Table 9. Software Reset State

State 3

State 1

State 2

I/O Mode & Register Bits

I/O Mode: SPI

SRWD SR[7]: Same as State 1

SNL SR[6]: Same as State 1

TBPROT SR[5]: Same as State 1

BP2 SR[4]: Same as State 1

BP1 SR[3]: Same as State 1

BP0 SR[2]: Same as State 1

WEL SR[1]: 0

STANDBY

Software RESET

STANDBY

WIP SR[0]: 0

QUAD CR[1]: Same as State 1

Figure 41. RESET Instruction in SPI Mode

Figure 42. RESET Instruction in DPI Mode

CS

SCK

HI-Z

SCK

HI-Z

1

0

1

0

1

SI (I/O0)

0

1

0

1

0

SI (I/O0)

X

HI-Z

SO(I/O1)

HI-Z

SO (I/O1)

Opcode (66h)

CS

SCK

SI (I/O0)

SO(I/O1)

HI-Z

0

1

0

1

0

Opcode (99h)

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Page 30 of 61

PRELIMINARY

CY14V101QS

Figure 43. RESET Instruction in QPI Mode

Note The functionalities of WP and HOLD are controlled by the

Quad bit CR[1] in configuration register. If Quad bit is set to logic

‘1’, WP and HOLD are configured as I/O2 and I/O3 respectively.

Otherwise, WP and HOLD functionality is configured.

CS

SCK

Figure 44. Default Recovery Instruction

CS

HI-Z

0

1

0

1

0

SI (I/O0)

SO(I/O1)

SCK

HI-Z

1

SI (I/O0)

SO (I/O1)

WP(I/O2)

HOLD (I/O3)

WP (I/O2)

Opc.

(66h)

HOLD (I/O3)

CS

SCK

(FFFFh)

Hibernate (HIBEN) Instruction

HI-Z

HIBEN instruction puts the nvSRAM in hibernate mode. When

the HIBEN instruction is issued, the nvSRAM takes tSS time to

process the HIBEN request. After the HIBEN command is

successfully registered and processed, the nvSRAM toggles

HSB LOW, performs a STORE operation to secure the data to

nonvolatile cells and then enters hibernate mode. The device

starts consuming I_ZZcurrent after t_HIBENtime when the HIBEN

instruction is registered. The device is not accessible for normal

operations after the HIBEN instruction is issued. In hibernate

mode, the SCK and SI pins are ignored and SO will be HI-Z but

the device continues to monitor the CS pin.

1

0

1

SI (I/O0)

0

1

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

Opc.

(99h)

To wake the nvSRAM from the hibernate mode, the device must

be selected by toggling the CS pin from HIGH to LOW. The

device wakes up and is accessible for normal operations after

tWAKE duration after a falling edge of CS pin is detected. The

part will wake up in the same mode as before the HIBEN

instruction.

Note Quad bit CR[1] must be logic ‘1’ before executing

RSTEN/RESET instructions in QPI mode.

Default Recovery Instruction

The device provides a default recovery mode where the device

is brought back to SPI mode. A logic high on all I/Os (I/O3, I/O2,

I/O1, I/O0) with eight SCLKs brings the device into a known

mode (SPI) so that the host can communicate to the device if the

starting mode is unknown.

Note Whenever nvSRAM enters hibernate mode, it initiates a

nonvolatile STORE cycle, which results in an endurance cycle

per hibernate command execution. A STORE cycle starts only if

a write to the SRAM has been performed since the last STORE

or RECALL cycle.

Table 10 summarizes the wake from Hibernate device states.

Table 10. Wake (Exit Hibernate) States

State 3

State 1

State 2

I/O Mode and Register Bits

I/O Mode: Same mode as State 1 (SPI/DPI/QPI)

SRWD SR[7]: Same as State 1

SNL SR[6]: Same as State 1

TBPROT SR[5]: Same as State 1

BP2 SR[4]: Same as State 1

BP1 SR[3]: Same as State 1

BP0 SR[2]: Same as State 1

WEL SR[1]: 0

STANDY

Hibernate

STANDBY

WIP SR[0]: 0

QUAD CR[1]: Same as State 1

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Page 31 of 61

PRELIMINARY

CY14V101QS

Figure 45. HIBEN Instruction in SPI Mode

Figure 46. HIBEN Instruction in DPI Mode

CS

SCK

HI-Z

SI (I/O0)

1

0

1

0

1

0

SI (I/O0)

SO (I/O1)

0

1

0

1

0

1

X

HI-Z

SO (I/O1)

Opcode (BAh)

Sleep (SLEEP) Instruction

SLEEP instruction puts the nvSRAM in sleep mode. When the SLEEP instruction is issued, the nvSRAM takes t_SLEEPtime to process

the SLEEP request and starts consuming I_SLEEPcurrent. The device is not accessible for normal operations after the SLEEP

instruction is issued. In sleep mode, all pins are active.

To wake the nvSRAM from sleep mode, EXSLP instruction must be entered. The nvSRAM is accessible for normal operations after

t_EXSLPduration. The part will wake in the same mode as before the SLEEP instruction. Any instructions entered other than EXSLP

and RDSR instructions while the device is in sleep mode will be ignored.

Table 11 summarizes the exit from sleep device states.

Table 11. Exit SLEEP (EXSLP) States

State 1

State 2

State 3

I/O Mode & Register Bits

I/O Mode: Same mode as State 1 (SPI/DPI/QPI)

SRWD SR[7]: Same as State 1

SNL SR[6]: Same as State 1

TBPROT SR[5]: Same as State 1

BP2 SR[4]: Same as State 1

BP1 SR[3]: Same as State 1

BP0 SR[2]: Same as State 1

WEL SR[1]: Same as State 1

WIP SR[0]: 0

STANDY

SLEEP

STANDBY

QUAD CR[1]: Same as State 1

Figure 49. SLEEP Instruction in DPI Mode

CS

Figure 48. SLEEP Instruction in SPI Mode

SCK

CS

HI-Z

0

1

0

1

0

SI (I/O0)

SCK

1

0

1

0

1

SO (I/O1)

X

SI (I/O0)

Opcode (B9h)

HI-Z

SO (I/O1)

Opcode (B9h)

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Page 32 of 61

PRELIMINARY

CY14V101QS

Figure 50. SLEEP Instruction in QPI Mode

Figure 52. EXSLP Instruction in DPI Mode

CS

SCK

HI-Z

1

0

1

0

1

0

1

0

1

0

1

SI (I/O0)

SO (I/O1)

HI-Z

SO (I/O1)

Opcode (ABh)

WP (I/O2)

Figure 53. EXSLP Instruction in QPI Mode

HOLD (I/O3)

Opc.

(B9h)

CS

SCK

HI-Z

Figure 51. EXSLP Instruction in SPI Mode

HI-Z

1

0

1

0

1

SI (I/O0)

CS

HI-Z

SO (I/O1)

SCK

WP (I/O2)

1

0

1

0

1

0

1

X

SI (I/O0)

HOLD (I/O3)

HI-Z

SO (I/O1)

Opc.

(ABh)

Opcode (ABh)

Document Number: 001-85257 Rev. *G

Page 33 of 61

PRELIMINARY

CY14V101QS

Register Instructions

Read Status Register (RDSR) Instruction

The RDSR instruction provides access to Status Register at SPI frequencies up to 108 MHz. This instruction is used to probe the

status of the device.

Note After the last bit of Status Register is read, the device loops back to the first bit of the Status Register.

Figure 54. RDSR Instruction in SPI Mode

CS

SCK

0

1

0

1

X

SI (I/O0)

HI-Z

Opcode (05h)

HI-Z

D7

D6

D5

D4

D3

D2

D1

D0

SO (I/O1)

Read data

Figure 55. RDSR Instruction in DPI Mode

CS

SCK

HI-Z

0

1

0

1

0

D6

D7

D4

D5

D2

D3

D0

D1

SI (I/O0)

HI-Z

SO (I/O1)

Opcode (05h)

Read Data

Figure 56. RDSR Instruction in QPI Mode

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to Status

Register. However, this instruction can only modify writable bits

- bit 2 (BP0), bit 3 (BP1), bit 4 (BP2) bit 5 TBPROT, bit 6 SNL,

and bit 7 (SRWD). WRSR instruction is a write instruction and

needs the WEL bit set to ‘1’ (by using WREN instruction). WRSR

instruction opcode is issued after the falling edge of CS followed

by eight bits of data to be stored in Status Register. As mentioned

before, WRSR instruction can only modify bits 2, 3, 4, 5, 6, and

7 of Status Register.

CS

SCK

HI-Z

0

1

0

1

0

D4

D5

D6

D7

D0

D1

D2

D3

SI (I/O0)

HI-Z

SO (I/O1)

Note The values written to Status Register are saved to nonvol-

atile memory only after a STORE operation. If AutoStore is

disabled, any modifications to the Status Register must be

secured by performing a Software STORE operation.

WP (I/O2)

Note The WEL bit in the Status Register resets to '0' on

completion of a Status Register Write sequence.

HOLD (I/O3)

Opc.

(05h)

Rd.

data

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PRELIMINARY

CY14V101QS

Figure 57. WRSR Instruction in SPI Mode

CS

SCK

0

1

D7

D6

D5

D4

D3

D2

D1

D0

X

SI (I/O0)

SO (I/O1)

HI-Z

Opcode (01h)

Write Data

Figure 58. WRSR Instruction in DPI Mode

Read Configuration Register (RDCR) Instruction

The RDCR instruction provides access to Configuration Register

at SPI frequencies up to 108 MHz. The following figures provide

the configuration register instruction transfer waveforms in SPI,

DPI, and QPI modes.

CS

SCK

HI-Z

Note After the last bit of Configuration Register is read, the

device loops back to the first bit of the Configuration register.

HI-Z

0

1

0

D6

D7

D4

D5

D2

D3

D0

D1

SI (I/O0)

HI-Z

SO (I/O1)

Opcode (01h)

Write Data

Figure 59. WRSR Instruction in QPI Mode

CS

SCK

HI-Z

0

1

0

D4

D5

D6

D7

D0

D1

D2

D3

SI (I/O0)

SO (I/O1)

HI-Z

WP (I/O2)

HOLD (I/O3)

Opc.

(01h)

Wr.

Data

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

Figure 60. RDCR Instruction in SPI Mode

CS

SCK

SI (I/O0)

SO (I/O1)

0

1

0

1

0

1

X

HI-Z

Opcode (35h)

HI-Z

D7

D6

D5

D4

D3

D2

D1

D0

Read Data

Figure 61. RDCR Instruction in DPI Mode

Figure 62. RDCR Instruction in QPI Mode

CS

SCK

HI-Z

SI (I/O0)

0

1

0

1

0

D6

D7

D4

D5

D2

D3

D0

D1

SI (I/O0)

SO (I/O1)

1

0

1

0

1

0

D4

D5

D6

D7

D0

D1

D2

D3

HI-Z

SO (I/O1)

Opcode (35h)

Read Data

WP (I/O2)

HOLD (I/O3)

Opc.

(35h)

Rd.

Data

Note Quad bit CR[1] must be logic ‘1’ before executing the

RDCR instruction in QPI mode.

Write Configuration Register (WRCR) Instruction

The WRCR instruction writes enables user to change the data

width of the device by setting the Quad Bit. The Quad bit must

be set to one when using Read Quad Out, Quad I/O Read, and

Quad Input Write commands. The QUAD bit is non-volatile.

Note Enabling the QPI mode (QPIEN Instruction) does not set

the Quad bit in configuration register.

Note It is recommended that RFU bits should always be written

as provided in Table 8.

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

Figure 63. WRCR Instruction in SPI Mode

CS

SCK

SI (I/O0)

SO (I/O1)

1

0

1

0

D1

0

X

HI-Z

Opcode (87h)

Write Data

Figure 64. WRCR Instruction in DPI Mode

the bus. An RDID instruction can be issued by shifting the

opcode for RDID after CS# goes LOW.

CS

Device ID is 4-byte read only code identifying 1-Mbit QPI

nvSRAM product uniquely. This includes the product family

code, configuration and density of the product.

SCK

The RDID command reads the 4 byte Device ID structure (the

structure cannot be written to). The structure is accessed one

Byte at a time. The first accessed Byte is the most significant byte

of the structure ID[31:24], the second accessed byte is ID[23:16],

…, the last accessed Byte is ID[7:0].

HI-Z

SI (I/O0)

0

1

0

1

0

1

0

SO (I/O1)

D1

Note As the structure is always accessed in the same order, no

address transfer is required. Instead an internal 2-bit address

pointer is used that is initialized to “0” when the opcode is

decoded. After each Byte access the internal address pointer is

incremented. The address pointer wraps around from ‘3’ to ‘0’;

after the 4th Byte ID[7:0] is accessed, the 1st Byte ID[31:24] is

accessed. This command can be issued in SPI, DPI or QPI

Modes.

Opcode (87h)

Write Data

Identification Register (RDID) Instruction

RDID instruction is used to read the JEDEC-assigned manufac-

turer ID and product ID of the device at an SPI frequency of up

to 40 MHz. This instruction can be used to identify a device on

Table 12. Device Identification

Manufacturer ID Product ID

Density

6-3

4 bits

0100

Die REV

2-0

3 bits

000

Device

CY14V101QS

31-21

11 bits

20-7

14 bits

00000110100

00001100010001

Figure 65. RDID Instruction in SPI Mode

CS

SCK

X

1

0

1

X

SI (I/O0)

SO (I/O1)

HI-Z

ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24

ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Opcode (9Fh)

ID Data

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PRELIMINARY

CY14V101QS

Figure 66. RDID Instruction in DPI Mode

CS

SCK

HI-Z

0

1

0

1

ID30 ID28 ID26 ID24

ID31 ID29 ID27 ID25

ID6 ID4 ID2 ID0

ID7 ID5 ID3 ID1

SI (I/O0)

SO (I/O1)

Opcode (9Fh)

ID Data

Figure 67. RDID Instruction in QPI Mode

Note: Quad bit CR[1] must be logic ‘1’ before executing the RDID

instruction in QPI mode.

CS

Identification Register (FAST_RDID) Instruction

The FAST_RDID instruction is similar to RDID except it allows

for a dummy byte after the opcode. FAST_RDID instruction is

used to read the JEDEC-assigned manufacturer ID and product

ID of the device at an SPI frequency of up to 108 MHz.

SCK

HI-Z

1

0

1

ID28 ID24

ID29 ID25

ID30 ID26

ID31 ID27

ID4 ID0

ID5 ID1

ID6 ID2

ID7 ID3

SI (I/O0)

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

Opc.

(9Fh)

ID Data

Figure 68. FAST_RDID in SPI Mode

CS

SCK

X

1

0

1

0

X

SI (I/O0)

HI-Z

ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24

ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

SO (I/O1)

Opcode (9Eh)

Dummy Byte

ID Data

Figure 69. FAST_RDID in DPI Mode

CS

SCK

HI-Z

0

1

0

1

ID30 IDID3028 ID26 ID24

ID31 IDID3129 ID27 ID25

ID6 ID4 ID2 ID0

SI (I/O0)

HI-Z

0

ID7 ID5 ID3 ID1

SO (I/O1)

Opcode (9Eh)

DMY Byte

ID Data

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

Figure 70. FAST_RDID in QPI Mode

CS

SCK

HI-Z

1

0

1

0

1

ID28 ID24

ID29 ID25

ID30 ID26

ID31 ID27

ID4 ID0

ID5 ID1

ID6 ID2

ID7 ID3

SI (I/O0)

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

Opc.

(9Eh)

DMY

Byte

ID Data

Serial Number Register Write (WRSN) Instruction

The serial number is an 8 byte programmable memory space

provided to the user to uniquely identify the device. It typically

number. This command requires the WEL bit to be set before it

can be executed. The WEL bit is reset to '0' after completion of

this command if SRWD bit in the Status register is not set to ‘1’

This command can be issued in SPI, DPI or QPI Modes.

consists of a two byte Customer ID, followed by five bytes of

unique serial number and one byte of CRC check. However,

device does not calculate the CRC and it is up to the system

designer to utilize the eight byte memory space in whatever

manner desired. The default value for eight byte locations are set

to ‘0x00’.

The serial number is written using the WRSN instruction at an

SPI frequency of up to 108 MHz.

Note A STORE operation (AutoStore or Software STORE) is

required to store the serial number in the nonvolatile memory. If

AutoStore is disabled, you must perform a Software STORE

operation to secure and lock the serial number. If the SNL bit is

set to ‘1’ and is not stored (AutoStore disabled), the SNL bit and

serial number defaults to ‘0’ at the next power cycle. If the SNL

bit is set to ‘1’ and is stored, the SNL bit can never be cleared to

‘0’. This instruction requires the WEL bit to be set before it can

be executed. This instruction can be issued in SPI, DPI, or QPI

modes.

The serial number is written using WRSN command. To write

serial number, the write must be enabled using the WREN

command. The WRSN command can be used in burst mode to

write all the 8 bytes of serial number. After the last byte of serial

number is written, the device loops back to the first (MSB) byte

of the serial number. The serial number is locked using the SNL

bit of the Status Register. Once this bit is set to '1', no modifi-

cation to the serial number is possible. After the SNL bit is set to

'1', using the WRSN command has no effect on the serial

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

Note The WEL bit is reset to ‘0’ after completion of this instruction.

Figure 71. WRSN Instruction in SPI Mode

CS

SCK

1

0

1

0

SN63 SN62 SN61 SN60 SN59 SN58 SN57 SN56

SN7 SN6 SN5 SN4 SN3 SN2 SN1 SN0

X

SI (I/O0)

SO (I/O1)

HI-Z

Opcode (C2h)

SN Write Data

Figure 72. RSN Instruction in DPI Mode

CS

SCK

HI-Z

1

0

1

SN62 SN60 SN58 SN56

SN63 SN61 SN59 SN57

SN6 SN4 SN2 SN0

SN7 SN5 SN3 SN1

SI (I/O0)

SO (I/O1)

Opcode (C2h)

SN Write Data

Figure 73. WRSN Instruction in QPI Mode

CS

SCK

HI-Z

0

1

0

SN60 SN56

SN61 SN57

SN62 SN58

SN63 SN59

SN4 SN0

SN5 SN1

SN6 SN2

SN7 SN3

SI (I/O0)

SO (I/O1)

HI-Z

0

1

WP (I/O2)

HOLD (I/O3)

Opc.

(C2h)

SN Write Data

Serial Number Register Read (RDSN) Instruction

The serial number is read using the RDSN instruction at an SPI

frequency of up to 40 MHz. A serial number read may be

performed in burst mode to read all the eight bytes at once. After

the last byte of serial number is read, the device loops back to

the first (MSB) byte of the serial number. An RDSN instruction

can be issued by shifting the opcode for RDSN after CS goes

LOW. This is followed by nvSRAM shifting out the eight bytes of

the serial number. This instruction can be issued in SPI, DPI or

QPI modes.

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

Figure 74. RDSN Instruction in SPI Mode

CS

SCK

1

0

1

X

SI (I/O0)

SO (I/O1)

HI-Z

SN63 SN62 SN61 SN60 SN59 SN58 SN57 SN56

SN7 SN6 SN5 SN4 SN3 SN2 SN1 SN0

Opcode (C3h)

SN Read Data

Figure 75. RDSN Instruction in DPI Mode

CS

SCK

HI-Z

1

0

1

SN62 SN60 SN58 SN56

SN63 SN61 SN59 SN57

SN6 SN4 SN2 SN0

SI (I/O0)

SN7 SN5 SN3 SN1

SO (I/O1)

Opcode (C3h)

SN Read Data

Figure 76. RDSN Instruction in QPI Mode

CS

SCK

HI-Z

0

1

0

SN60 SN56

SN61 SN57

SN62 SN58

SN63 SN59

SN4 SN0

SN5 SN1

SN6 SN2

SN7 SN3

SI (I/O0)

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

Opc.

(C3h)

SN Read Data

Note Quad bit CR[1] must be logic ‘1’ before executing the RDSN instruction in QPI mode.

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

Fast Read Serial Number Register (FAST_RDSN) Instruction

The FAST_RDSN instruction is similar to RDSN except it allows for a dummy byte after the opcode. FAST_RDSN instruction is used

up to 108 MHz.

Figure 77. FAST_RDSN Instruction in SPI Mode

CS

SCK

SI (I/O0)

X

1

0

1

0

1

X

HI-Z

SO (I/O1)

SN63 SN62 SN61 SN60 SN59 SN58 SN57 SN56

SN7 SN6 SN5 SN4 SN3 SN2 SN1 SN0

Opcode (C9h)

Dummy Byte

SN Data

Figure 78. FAST_RDSN Instruction in DPI Mode

CS

SCK

HI-Z

SI (I/O0)

1

0

1

0

SN62IDS3N060 SN58 SN56

SN63IDS3N161 SN59 SN57

SN6 SN4 SN2 SN0

HI-Z

SO (I/O1)

SN7 SN5 SN3 SN1

Opcode (C9h)

DMY Byte

SN Data

Figure 79. FAST_RDSN Instruction in QPI Mode

CS

SCK

HI-Z

0

1

0

1

SN60 SN56

SN61 SN57

SN62 SN58

SN63 SN59

SN4 SN0

SN5 SN1

SN6 Sn2

SN7 SN3

SI (I/O0)

SO (I/O1)

HI-Z

WP (I/O2)

HOLD (I/O3)

Opc.

(C9h)

DMY

Byte

SN Data

Document Number: 001-85257 Rev. *G

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PRELIMINARY

CY14V101QS

NV Specific Instructions

The nvSRAM device provides four special instructions, which enable access to the nvSRAM specific functions: STORE, RECALL,

ASEN, and ASDI.

Software Store (STORE) Instruction

When a STORE instruction is executed, nvSRAM performs a

Software STORE operation. The STORE operation is performed

irrespective of whether a write has taken place since the last

STORE or RECALL operation. To issue this instruction, the

device must be write enabled (WEL bit = ‘1’). The instruction can

be issued in SPI, DPI and QPI modes.

Figure 82. STORE Instruction in QPI Mode

CS

SCK

Note The WEL bit is cleared on the positive edge of CS following

the STORE instruction

HI-Z

SI (I/O0)

SO (I/O1)

0

1

0

1

Figure 80. STORE Instruction in SPI Mode

HI-Z

CS

WP (I/O2)

SCK

HOLD (I/O3)

SI (I/O0)

1

0

1

0

X

Opc.

(8Ch)

HI-Z

SO (I/O1)

Opcode (8Ch)

Figure 81. STORE Instruction in DPI Mode

CS

SCK

HI-Z

SI (I/O0)

0

1

0

1

0

HI-Z

SO (I/O1)

Opcode (8Ch)

Software Recall (RECALL) Instruction

When a RECALL instruction is executed, nvSRAM performs a

Software RECALL operation. To issue this instruction, the device

must be write enabled (WEL = ‘1’). This instruction can be issued

in SPI, DPI, or QPI modes.

Figure 83. RECALL Instruction in SPI Mode

CS

Note The WEL bit is cleared on the positive edge of CS following

the RECALL instruction.

SCK

1

0

1

0

1

SI (I/O0)

X

HI-Z

SO (I/O1)

Opcode (8Dh)

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CY14V101QS

Figure 84. RECALL Instruction in DPI Mode

Figure 87. ASEN Instruction in DPI Mode

CS

SCK

CS

SCK

HI-Z

SI (I/O0)

SO (I/O1)

0

1

0

1

0

1

0

1

0

1

SI (I/O0)

HI-Z

0

SO (I/O1)

Opcode (8Dh)

Opcode (8Eh)

Figure 85. RECALL Instruction in QPI Mode

Figure 88. ASEN Instruction in QPI Mode

CS

SCK

HI-Z

SI (I/O0)

SO (I/O1)

0

1

0

1

0

1

0

1

SI (I/O0)

SO (I/O1)

HI-Z

WP (I/O2)

HOLD (I/O3)

Opc.

(8Dh)

Opc.

(8Eh)

Note Quad bit CR[1] must be logic ‘1’ before executing the ASEN

instruction in QPI mode.

Autostore Enable (ASEN) Instruction

The AutoStore Enable instruction enables the AutoStore on the

nvSRAM device. This setting is not nonvolatile and needs to be

followed by a STORE sequence to survive the power cycle. To

issue this instruction, the device must be write enabled (WEL =

‘1’). This instruction can be issued in SPI, DPIO, or QPI modes.

Autostore Disable (ASDI) Instruction

AutoStore is enabled by default in this device. The ASDI

instruction disables the AutoStore. This setting is not nonvolatile

and needs to be followed by a STORE sequence to survive the

power cycle. To issue this instruction, the device must be write

enabled (WEL = ‘1’). This instruction can be issued in SPI, DPI,

or QPI modes.

Note If the ASDI and ASEN instructions are executed, the device

is busy for the duration of software sequence processing time

(t_SS).

Note The WEL bit is cleared on the positive edge of CS following

the ASE instruction.

Note The WEL bit is cleared on the positive edge of CS following

the ASDI instruction.

Figure 86. ASEN Instruction in SPI Mode

CS

SCK

SI (I/O0)

1

0

1

0

X

HI-Z

SO (I/O1)

Opcode (8Eh)

Document Number: 001-85257 Rev. *G

Page 44 of 61

PRELIMINARY

CY14V101QS

Figure 89. ASDI Instruction in SPI Mode

Figure 91. ASDI Instruction in QPI Mode

CS

SCK

CS

SCK

HI-Z

SI (I/O0)

1

0

1

0

1

X

SI (I/O0)

HI-Z

SO (I/O1)

WP (I/O2)

HOLD (I/O3)

SO (I/O1)

Opcode (8Fh)

Figure 90. ASDI Instruction in DPI Mode

Opc.

(8Fh)

CS

SCK

Note: Quad bit CR[1] must be logic ‘1’ before executing the ASDI

instruction in QPI mode.

HI-Z

SI (I/O0)

0

1

0

1

HI-Z

SO (I/O1)

0

1

Opcode (8Fh)

HOLD Pin Operation

The HOLD pin is used to pause the serial communication. When

the device is selected and a serial sequence is underway, HOLD

is used to pause the serial communication with the master device

without resetting the ongoing serial sequence. To pause, the

HOLD pin must be brought LOW when the SCK pin is LOW. To

resume serial communication, the HOLD pin must be brought

HIGH when the SCK pin is LOW (SCK may toggle during HOLD).

While the device serial communication is paused, inputs to the

SI pin are ignored and the SO pin is in the high-impedance state.

This pin can be used by the master with the CS pin to pause the

serial communication by bringing the HOLD pin LOW and

deselecting an SPI slave to establish communication with

another slave device, without the serial communication being

reset. The communication may be resumed at a later stage by

selecting the device and setting the HOLD pin HIGH.

Figure 92. HOLD Operation

HOLD

CS

SCK

SI (I/O0)

SO (I/O1)

X

O7

O6

X

O5

O4

O3

O2

O1

O0

X

D7

D6 D5

D4

D3

D2

D1

D0

Opcode

Write Data

Document Number: 001-85257 Rev. *G

Page 45 of 61

PRELIMINARY

CY14V101QS

24-ball FPGA ......................................................... 1.0W

Maximum Ratings

Package power dissipation

capability (T_A= 25 °C) ................................................. 1.0 W

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Surface mount lead soldering

temperature (3 seconds) ......................................... +260C

Storage temperature ................................ –65 C to +150 C

Maximum accumulated storage time

DC output current (1 output at a time, 1-s duration) ... 15 mA

At 150 C ambient temperature ...................... 1000 h

At 85 C ambient temperature .................... 20 Years

Maximum junction temperature .................................. 150 C

Supply voltage on V_CCrelative to V_SS.........–0.5 V to +4.1 V

Supply voltage on V_CCQrelative to V_SS.....–0.5 V to +2.45 V

Static discharge voltage

(per MIL-STD-883, Method 3015) ..........................> 2001 V

Latch-up current ....................................................> 140 mA

Operating Range

DC voltage applied to outputs

in HI-Z state ......................................–0.5 V to V_CCQ+ 0.5 V

Ambient

Temperature

Range

V_CC

V_CCQ

Industrial

–40 C to +85 C 2.7 V to 3.6 V 1.71 V to 2.0 V

Input voltage .....................................–0.5 V to V_CCQ+ 0.5 V

Extended

Industrial

Transient voltage (< 20 ns) on

any pin to ground potential ...............–2.0 V to V_CCQ+ 2.0 V

–40 C to +105 C 2.7 V to 3.6 V 1.71 V to 2.0 V

Package power dissipation capability (T_A= 25 °C)

16-pin SOIC....................................................... 1.0 W

DC Specifications

Parameter

V_CC

Description

Power Supply - Core voltage

Power Supply - I/O voltage

Test Conditions

Min

Typ^[1]

Max

3.60

Units

V

–

2.70

1.71

–

3.00

1.80

–

V_CCQ

2.00

V

SPI = 1 MHz

1.00

mA

µA

Average Read/Write V_CCCurrent at

85 °C (all inputs toggling, no output SPI = 40 MHz

load)

–

1.50

QPI = 108 MHz

–

33.00

1.00

I_CC1

SPI = 1 MHz

–

Average Read/Write V_CCCurrent at

105 °C (all inputs toggling, no output SPI = 40 MHz

load)

–

1.50

QPI = 108 MHz

–

33.00

150.00

2.00

SPI = 1 MHz

–

Average V_CCQCurrent at 85 °C (all

inputs toggling, no output load)

SPI= 40 MHz

–

mA

µA

QPI = 108 MHz

SPI = 1 MHz

–

5.00

I_CCQ1

–

150.00

2.00

Average V_CCQCurrent at 105 °C (all

inputs toggling, no output load)

SPI= 40 MHz

–

mA

QPI = 108 MHz

–

5.00

Standby Current at 85 °C

(V_CC+ V_CCQ

V

CS > ( _CCQ– 0.2 V). Standby current

–

1.70

2.00

mA

µA

)

level after nonvolatile cycle is

complete. (CS High, Other I/Os have

no restrictions, f_SCK≤ 108 MHz)

I_SB1

Standby Current at105 °C

(V_CC+ V_CCQ

)

Standby Current at 85 °C

(V_CC+ V_CCQ

> (V_CCQ– 0.2 V).

CS

280.00

)

Standby current level after nonvolatile

cycle is complete. All I/Os Static,

f_SCK= 0 MHz

I_SB2

Standby Current at 105 °C

(V_CC+ V_CCQ

–

500.00

6.00

µA

mA

)

I_CC2

I_CC4

Average V_CCcurrent during STORE

–

Average V_CAPcurrent during

AUTOSTORE

6.00

Notes

1. Typical values are at 25 °C, V = V

and V

= V

. Not 100% tested.

CCQ(Typ

CC

CC(Typ)

CC Q

Document Number: 001-85257 Rev. *G

Page 46 of 61

PRELIMINARY

CY14V101QS

Parameter

Description

Test Conditions

Min

Typ^[1]

Max

Units

Sleep Mode current at 85 °C

CS > (V_CCQ– 0.2 V).

–

280.00

µA

(V_CC+ V_CCQ

Sleep Mode current at 105 °C

(V_CC+ V_CCQ

Hibernate mode current at 85 °C

(V_CC+ V_CCQ

Hibernate mode current at 105 °C

(V_CC+ V_CCQ

)

Sleep current level after nonvolatile

cycle is complete. All I/Os Static,

f_SCK= 0 MHz

I_SLEEP

–

500.00

8.00

µA

)

V

CS > ( _CCQ– 0.2 V). t_HIBENtime after

)

HIBEN Instruction is registered. All

inputs are static and configured at

CMOS logic level.

I_ZZ

10.00

)

Input leakage current (except HSB)

Input leakage current (for HSB)

–1.00

–

1.00

µA

V_CCQ= Max, VSS < VIN < V_CCQ

–100.00

[1]

Input leakage current (for WP in

SPI/DPI modes)

I_IX

–

–2

1

µA

Input leakage current (for HOLD in

SPI/DPI modes)

I_OZ

Off State Output Leakage Current

Input high voltage

V_CCQ= Max, VSS < VIN < V_CCQ

–1.00

0.70 * V_CCQ

–0.30

–

1.00

V_CCQ+ 0.30

–0.30 * V_CCQ

–

µA

V

V_IH

V_IL

–

Input low voltage

–

V

V_OH

V_OL

Output high voltage at -2 mA

Output low voltage at 2 mA

Storage capacitor

I_OH= –2 mA

V_CCQ–0.45

–

V

I_OL= 2 mA

–

0.45

V

[2]

V_CAP

Between V_CAPpin and V_SS

61.00

68.00

120.00

µF

Maximum Voltage Driven on V_CAP

[4]

V_VCAP

–

V_CC

V

Notes

2. The HSB pin has I

= -4 µA for V of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This

OH OH OL

OUT

parameter is characterized but not tested.

3. Min V value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V

value guarantees that the capacitor on

CAP

V

is charged to a minimum voltage during a power-up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore, it

CAP

is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V

4. These parameters are guaranteed by design and are not tested.

options.

CAP

Document Number: 001-85257 Rev. *G

Page 47 of 61

PRELIMINARY

CY14V101QS

Data Retention and Endurance

Parameter

Description

Data retention at 85 ^oC

Min

20

Unit

Years

K

DATA_R

NV_C

Nonvolatile STORE operations

1,000

Capacitance

Parameter^[6]

Description

Input capacitance

Test Conditions

Max

Unit

C_IN

C_SCK

Clock input capacitance

Output pin capacitance

T_A= 25 C, f = 1 MHz, V_CC= V_CC(typ),V_{CC Q}= V_CCQ(typ)

6.00

pF

C_OUT

Thermal Resistance

Parameter^[6]

Description

Test Conditions

16-Pin SOIC 24-Ball FBGA

Unit

Thermal resistance

(junction to ambient)

_JA

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51.

TBD

C/W

Thermal resistance

(junction to case)

_JC

AC Test Loads and Waveforms

Figure 93. AC Test Loads and Waveforms

450 

R1

450 

1.8 V

R1

OUTPUT

30 pF

R2

450 

R2

450 

5 pF

AC Test Conditions

Description

CY14V101QS

0 V to 1.8 V

< 1.8 ns

Input pulse levels

Input rise and fall times (10%–90%)

Input and output timing reference levels

0.9 V

Notes

5. Min V

value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V

value guarantees that the capacitor on

CAP

V

is charged to a minimum voltage during a power-up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore, it

CAP

is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V

6. These parameters are guaranteed by design and are not tested.

options.

CAP

Document Number: 001-85257 Rev. *G

Page 48 of 61

PRELIMINARY

CY14V101QS

AC Switching Characteristics

Parameter^[7]

f_SCK

Description

Min

–

Max

Units

Clock frequency (QPI)

Clock Pulse Width Low

Clock Pulse Width High

CS HIGH time

108.00

MHz

ns

t_CL

t_CH

t_CS

0.45*1/f_SCK

–

ns

End of READ

10.00

5.00

2.00

3.00

2.00

–

ns

End of WRITE

–

t_CSS

t_CSH

t_SD

CS setup time

–

CS hold time

–

Data in setup time

Data in hold time

HOLD setup time

HOLD hold time

–

t_HD

t_SH

–

t_HH

–

t_SW

WP setup time

–

t_HW

t_CO

WP hold time

–

Output Valid

7.00

–

t_HHZ

t_HLZ

t_CLZ

t_HHHD

t_OH

HOLD to output High Z

HOLD to output Low Z

Clock Low to Output Low Z

HSB high Active Time

Output Hold Time

Output Disable Time

–

0.00

–

500.00

–

1.00

–

t_HZCS

7.00

Notes

7. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of V

/2, input pulse levels of 0 to V

, and output loading of the specified

CCQ

CCQ(typ)

I

/I and load capacitance shown in Figure 93 on page 48.

OL OH

8. These parameters are guaranteed by design and are not tested.

Document Number: 001-85257 Rev. *G

Page 49 of 61

PRELIMINARY

CY14V101QS

Switching Waveforms

Figure 94. Synchronous Data Timing (Mode 0)

t

CS

SCK

SI

t

CL

CSS

t

CSH

CH

t

HD

SD

VALID IN

t

HZCS

t

CO

OH

t

CLZ

HI-Z

SO

Figure 95. HOLD Timing

CS

SCK

t

HH

t

SH

HOLD

SO

t

HLZ

HHZ

AutoStore or Power-Up RECALL

Over the Operating Range

Parameter

Description

Power-Up RECALL duration

STORE cycle duration

Min

Max

Unit

ms

ns

V

[9]

–

20.00

8.00

25.00

2.60

–

t_FA

[10]

[11]

–

t_STORE

t_DELAY

Time allowed to complete SRAM write cycle

Low voltage trigger level for V_CC

V_CCrise time

–

V_SWITCH

–

[12]

150.00

s

V

t_VCCRISE

[12]

[13]

HSB output disable voltage

I/O disable voltage on V_CCQ

HSB HIGH to nvSRAM active time

–

1.90

1.50

5.00

V_HDIS

V

V_IODIS

[12]

s

t_LZHSB

[12]

HSB HIGH active time

–

500.00

20.00

8.00

ns

ms

t_HHHD

t_WAKE

Time for nvSRAM to wake up from HIBERNATE mode

Time to enter HIBERNATE mode after issuing HIBEN instruction

t_HIBEN

Notes

9.

t

starts from the time V rises above V

.

FA

CC

SWITCH

10. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.

11. On a Hardware STORE, Software STORE/RECALL, AutoStore Enable/Disable and AutoStore initiation, SRAM operation continues to be enabled for time t

12. These parameters are guaranteed by design and are not tested.

.

DELAY

13. HSB is not defined below V

voltage.

IODIS

Document Number: 001-85257 Rev. *G

Page 50 of 61

PRELIMINARY

CY14V101QS

AutoStore or Power-Up RECALL (continued)

Over the Operating Range

Parameter

Description

Time to enter into sleep mode after

Min

–

Max

0.00

Unit

µs

[14]

going HIGH

t_SLEEP

t_EXSLP

t_RESET

CS

Time to exit from sleep mode after CS going HIGH

Soft reset duration

–

0.00

µs

–

500.00

µs

Switching Waveforms

Figure 96. AutoStore or Power-Up RECALL^[15]

V_CC

V_SWITCH

V_HDIS

V_CCQ

V

IODIS

17

Note

17

t_VCCRISE

t_STORE

16

Note

t_HHHD

Note

16

Note

HSB OUT

V_CCQ

t_DELAY

t_LZHSB

AutoStore

t_DELAY

POWER-

UP

RECALL

t_FA

Read & Write

Inhibited

(

RWI )

Read & Write

Read

&

Write

POWER-UP

RECALL

POWER

DOWN

POWER-UP

RECALL

Read

&

V_CC

Write AutoStore

V_CCQ

BROWN

OUT

AutoStore

BROWN

OUT

I/O Disable

Notes

14. These parameters are guaranteed by design and are not tested.

15. Read and write cycles are ignored during STORE, RECALL, and while V is below V

CC

SWITCH.

16. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.

Document Number: 001-85257 Rev. *G

Page 51 of 61

PRELIMINARY

CY14V101QS

Software Controlled STORE and RECALL Cycles

Over the Operating Range

Parameter

t_RECALL

Description

Min

–

Max

500

Unit

s

RECALL duration

[18, 19]

t_SS

Soft sequence processing time

–

s

Switching Waveforms

Figure 97. Software STORE Cycle ^[19]

Figure 98. Software RECALL Cycle ^[19]

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

SCK

SI

0

1

0

1

0

t

RECALL

STORE

HI-Z

RWI

RDY

RWI

RDY

Figure 99. AutoStore Enable Cycle

Figure 100. AutoStore Disable Cycle

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

SCK

SI

0

1

0

1

0

1

0

1

0

1

t

SS

HI-Z

RWI

RDY

RWI

RDY

Notes

18. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

19. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

Document Number: 001-85257 Rev. *G

Page 52 of 61

PRELIMINARY

CY14V101QS

Hardware STORE Cycle

Over the Operating Range

Parameter

Description

Min

Max

Unit

t_PHSB

Hardware STORE pulse width

15

600

ns

Switching Waveforms

Figure 101. Hardware STORE Cycle ^[20]

Write Latch set

t

PHSB

HSB (IN)

t

STORE

t

HHHD

DELAY

HSB (OUT)

RWI

t

LZHSB

Write Latch not set

t

PHSB

HSB (IN)

HSB pin is driven HIGH to V

only by Internal

CC

100 K: resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

HSB (OUT)

RWI

t

DELAY

Note

20. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.

Document Number: 001-85257 Rev. *G

Page 53 of 61

PRELIMINARY

CY14V101QS

Ordering Information

Ordering Code

CY14V101QS-BK108XI

CY14V101QS-BK108XITR

CY14V101QS-BK108XQ

CY14V101QS-BK108XQTR

CY14V101QS-SE108XI

CY14V101QS-SE108XITR

CY14V101QS-SE108XQ

CY14V101QS-SE108XQTR

CY14V101QS-SF108XI

CY14V101QS-SF108XITR

CY14V101QS-SF108XQ

CY14V101QS-SF108XQTR

Package Diagram

Package Type/Pinout

Operating Range

Industrial

001-97209

24-FBGA, Standard

Extended Industrial

Industrial

16-SOIC, Custom

16-SOIC, Standard

Extended Industrial

Industrial

51-85022

Extended Industrial

All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.

Document Number: 001-85257 Rev. *G

Page 54 of 61

PRELIMINARY

CY14V101QS

Ordering Code Definitions

CY 14 V 101 QS - SF 108 X I TR

Option:

TR - Tape and Reel, Blank - Std.

Temperature:

I - Industrial, Q - Extended Industrial

Pb-free

Frequency:

108 - 108 MHz

Package:

SF - 16 SOIC Standard, SE - 16 SOIC Custom, BK - 24 FBGA

QS - Quad SPI, PS - Quad SPI with RTC

Density:

101 - 1-Mbit

Voltage:

V - 3.0 V, 1.8 V I/O

14 - nvSRAM

CY - Cypress

Document Number: 001-85257 Rev. *G

Page 55 of 61

PRELIMINARY

CY14V101QS

Package Diagrams

Figure 102. 16-Pin SOIC (0.413 × 0.299 × 0.0932 Inches) Package Outline, 51-85022

51-85022 *E

Figure 103. 24-ball FBGA Package

TOP VIEW

8.00 BSC

BOTTOM VIEW

4.00 BSC

SIDE VIEW

4.00 BSC

6.00 BSC

1.00 BSC

Ø0.40 0.0ꢀ

0.20 MIN

PIN A1

CORNER

PIN A1

CORNER

1.20 MAX

0.10

C

001-97209 **

Document Number: 001-85257 Rev. *G

Page 56 of 61

PRELIMINARY

CY14V101QS

Acronyms

Document Conventions

Units of Measure

Symbol

Acronym

Description

CPHA

CPOL

CMOS

CRC

clock phase

clock polarity

Unit of Measure

°C

degree Celsius

complementary metal oxide semiconductor

cyclic redundancy check

Hz

kHz

k

Mbit

MHz

A

F

s

hertz

kilohertz

kilohm

EEPROM electrically erasable programmable read-only

memory

megabit

megahertz

microampere

microfarad

microsecond

milliampere

millisecond

nanosecond

ohm

EIA

Electronic Industries Alliance

input/output

I/O

JEDEC

LSB

Joint Electron Devices Engineering Council

least significant bit

MSB

most significant bit

mA

ms

ns

nvSRAM

RWI

nonvolatile static random access memory

read and write inhibit

RoHS

SNL

restriction of hazardous substances

serial number lock



%

percent

SPI

serial peripheral interface

pF

V

picofarad

volt

SONOS

SOIC

SRAM

silicon-oxide-nitride-oxide semiconductor

small outline integrated circuit

static random access memory

W

watt

Document Number: 001-85257 Rev. *G

Page 57 of 61

PRELIMINARY

CY14V101QS

Document History Page

Document Title: CY14V101QS, 1-Mbit (128K × 8) Quad SPI nvSRAM

Document Number: 001-85257

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

**

3847722

4477078

GVCH

SZZX

04/22/2013 New datasheet.

*A

10/08/2014 Added 16-pin DFN pin and package details.

Updated 16-pin SOIC pinout.

Updated average standby mode current.

Updated I/O Modes

Updated SPI Functional Description, Status Register, Memory Access, Special

Instructions, Identification Instruction, and .

Updated DC Specifications and AC Switching Characteristics.

*B

*C

4567579

4620720

AVIA

11/13/2014 Removed DFN package

Updated ordering information

SZZX

01/23/2015 Updated the document title (removed the brackets around SPI since this is not

a Quad nvSRAM).

Replaced the following sections: Features, Functional Overview, Device

Operation, SPI Functional Description, DC Specifications, AC Switching

Characteristics, and Ordering Information.

Added The device provides a default recovery mode where the device is

brought back to SPI mode. A logic high on all I/Os (I/O3, I/O2, I/O1, I/O0) with

eight SCLKs brings the device into a known mode (SPI) so that the host can

communicate to the device if the starting mode is unknown.

Updated the figure title in Figure 1.

Added Figure 1.

Replaced Figure 40 and Figure 41.

Updated Pin Definitions.

Removed the Notes in Pin Definitions section.

Updated Table 1.

Updated Power-Down from “conditional AutoStore operation is performed” to

“Autostore operation is performed”.

Updated the first paragraph in SPI Overview.

Updated the first sentence to “CY14V101QS has one 8-bit Status Register, in

Status Register.

Updated the device status for Status Register state, in Power-Up.

Updated the V_CCQvalues in Operating Range.

Updated the Minimum factor V_IHand Maximum factor for V_ILin DC

Specifications.

Updated the description for DATA_Rin Data Retention and Endurance.

Updated the Maximum value of C_IN, C_CLK, and C_OUTto 7, in Capacitance.

Updated AutoStore or Power-Up RECALL.

Updated Figure 98.

Added Note 17.

Updated the Maximum value of t_RECALLto 500 s, in Software Controlled

STORE and RECALL Cycles.

Updated Ordering Information and Ordering Code Definitions.

*D

4653540

SZZX

02/19/2015 Updated Low-power modes feature in Features.

Updated section heading “Active Power and Standby Power Modes” to 6.

Updated CS Pin Description in Pin Definitions.

Updated the term “Standby power mode” to “Standby mode” in Power-Up and

Power-Down.

Updated the section title “Active Power and Standby Modes” to Active Power

Mode and Standby State.

Updated Table 2.

Updated Active Power Mode and Standby State.

Updated the Power modes in System Resource instruction, in SPI Functional

Description.

Removed “Standby (STANDBY) Instruction” section.

Updated Sleep (SLEEP) Instruction.

Document Number: 001-85257 Rev. *G

Page 58 of 61

PRELIMINARY

CY14V101QS

Document Title: CY14V101QS, 1-Mbit (128K × 8) Quad SPI nvSRAM

Document Number: 001-85257

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

*D (cont.)

4653540

SZZX

02/19/2015 Added Hibernate (HIBEN) Instruction.

Replaced the term “dummy” to “mode” in the following subsections:

SRAM Read, Fast Read Instructions, FAST_READ Instruction, DOR

Instruction, and QOR Instruction.

Replaced the term “dummy” with “mode/dummy” in Instruction.

Replaced the term “dummy cycle” with “mode byte cycle” in FAST_READ

Instruction.

Replaced the following figures: Figure 22, Figure 23, Figure 31, Figure 40, and

Figure 70 through Figure 72.

Updated DC Specifications.

Updated AutoStore or Power-Up RECALL.

*E

4779656

SZZX

05/28/2015 Updated the following in Features: Temperature range, Packages, and

Low-power modes.

Added the following figures: Figure 3, Figure 61, Figure 63 through Figure 65,

and Figure 79 through Figure 81.

Updated the following figures: Figure 6, Figure 7, Figure 14, Figure 15,

Figure 22, Figure 23, Figure 38 through Figure 45, Figure 66, Figure 70

through Figure 72, Figure 78, Figure 82 through Figure 93, and Figure 105.

Added the following sections:

Write-Protect (WP), Hold (HOLD), Configuration Register, Read Status

Register (RDSR) Instruction, Write Configuration Register (WRCR) Instruction,

and Fast Read Serial Number Register (FAST_RDSN) Instruction.

Updated the following sections:

Functional Overview, SRAM Read, Status Register Write Disable (SRWD)

SR[7], Write Enable (WEL) SR[1], Quad Data Width (QUAD) CR[1], Software

Store (STORE) Instruction, Software Recall (RECALL) Instruction, Data

Transmission - SI/SO, Write-Protect (WP), Power-Up, Configuration Register,

Enable QPI (QPIEN) Instruction, Enable SPI (SPIEN) Instruction, Software

Reset (RESET) Instruction, Serial Number Register Write (WRSN) Instruction,

Serial Number Register Read (RDSN) Instruction, Identification Register

(RDID) Instruction, Maximum Ratings, Operating Range, DC Specifications,

Thermal Resistance, AC Switching Characteristics, AutoStore or Power-Up

RECALL, Ordering Information and Ordering Code Definitions.

Updated the following in SPI Functional Description: Updated the Register

instructions and nvSRAM Special instruction, and added a Note.

Updated the following in Quad Data Width (QUAD) CR[1]: Updated the section

and added a Note.

Added Table 7 through Table 11.

Updated the following tables: Table 1, Table 2, Table 5, and Table 6.

Added a Note in Write-Protect (WP), Chip Select (CS), QOR Instruction, QIOR

Instruction, QIW Instructions, QIOW Instruction, Status Register Write Disable

(SRWD) SR[7], Write Enable (WEL) SR[1], Quad Data Width (QUAD) CR[1],

Write Disable (WRDI) Instruction, Write Enable (WREN) Instruction, Enable

DPI (DPIEN) Instruction, Enable SPI (SPIEN) Instruction, READ Instruction,

FAST_READ Instruction, WRITE Instruction, Default Recovery Instruction,

Software Reset (RESET) Instruction, Hibernate (HIBEN) Instruction, Sleep

(SLEEP) Instruction, Read Status Register (RDSR) Instruction, Write Status

Register (WRSR) Instruction, Identification Register (RDID) Instruction,

Identification Register (FAST_RDID) Instruction, Serial Number Register Write

(WRSN) Instruction, Serial Number Register Read (RDSN) Instruction, Fast

Read Serial Number Register (FAST_RDSN) Instruction, Software Store

(STORE) Instruction, Software Recall (RECALL) Instruction, Autostore Disable

(ASDI) Instruction, and Autostore Enable (ASEN) Instruction.

Document Number: 001-85257 Rev. *G

Page 59 of 61

PRELIMINARY

CY14V101QS

Document Title: CY14V101QS, 1-Mbit (128K × 8) Quad SPI nvSRAM

Document Number: 001-85257

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

*E (cont.)

4779656

SZZX

05/28/2015

Removed the section “Read Fault Register (RDGR) Instruction” and “Device

ID section”.

Removed Table 8. Fault Register Format and Bit Definitions.

Removed Figure 65. RDGR Instruction in SPI Mode, Figure 66. RDGR

Instruction in DPI Mode, and Figure 67. RDGR Instruction in QPI Mode.

*F

4797469

4827642

SZZX

07/02/2015 Removed 256-Kbit device description and associated part numbers

Changed datasheet status from SUMMARY to PRELIMINARY

07/09/2015 No technical changes

*G

Document Number: 001-85257 Rev. *G

Page 60 of 61

PRELIMINARY

CY14V101QS

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

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61

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any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-85257 Rev. *G

Revised July 9, 2015

Page 61 of 61

All products and company names mentioned in this document may be the trademarks of their respective holders.


型号：	CY14V101QS-BK108XITR
厂家：	CYPRESS
描述：	Non-Volatile SRAM, 128KX8, CMOS, PBGA24, LEAD FREE, FBGA-24 静态存储器内存集成电路
文件：	总61页 (文件大小：1301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY14V101QS-BK108XITR [CYPRESS]

相关型号：

CY14V101QS-BK108XQ

CY14V101QS-BK108XQTR

CY14V101QS-SE108XI

CY14V101QS-SE108XIT

CY14V101QS-SE108XQ

CY14V101QS-SE108XQT

CY14V101QS-SE108XQTR

CY14V101QS-SF108XI

CY14V101QS-SF108XIT

CY14V101QS-SF108XQ

CY14V101QS-SF108XQT

CY14V101QS-SF108XQTR