CY2291F [CYPRESS]
Three-PLL General Purpose EPROM Programmable Clock Generator; 三锁相环通用的EPROM可编程时钟发生器
| 型号： | CY2291F |
| 厂家： | 
CYPRESS |
| 描述： | Three-PLL General Purpose EPROM Programmable Clock Generator |
| 文件： | 总13页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2291
Three-PLL General Purpose
EPROM Programmable Clock Generator
Features
Three integrated phase-locked loops
EPROM programmability
Benefits
Generates up to 3 custom frequencies from external sources
Easy customization and fast turnaround
Factory-programmable (CY2291) or field-programmable
(CY2291F) device options
Programming support available for all opportunities
Low-skew, low-jitter, high-accuracy outputs
Power-management options (Shutdown, OE, Suspend)
Frequency select option
Meets critical industry standard timing requirements
Supports low-power applications
8 user-selectable frequencies on CPU PLL
Allows downstream PLLs to stay locked on CPUCLK output
Enables application compatibility
Smooth slewing on CPUCLK
Configurable 3.3V or 5V operation
20-pin SOIC Package
Industry-standard packaging saves on board space
Selector Guide
Part Number Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY2291
8
8
8
8
10 MHz–25 MHz (external crystal) 76.923 kHz–100 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–80 MHz (3.3V)
Factory Programmable
Commercial Temperature
CY2291I
CY2291F
CY2291FI
10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V)
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V)
Field Programmable
Industrial Temperature
10 MHz–25 MHz (external crystal) 76.923 kHz–80 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–60.0 MHz (3.3V)
Logic Block Diagram
32XIN
OSC.
32K
32XOUT
XTALIN
OSC.
XBUF
CPUCLK
CLKA
XTALOUT
CPLL
(8 BIT)
/1,2,4
S0
S1
S2/SUSPEND
UPLL
(10 BIT)
CLKB
/1,2,4,8
CLKC
CLKD
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96,104
SPLL
(8 BIT)
/2,3,4
CLKF
CONFIG
EPROM
SHUTDOWN/
OE
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 14, 2000, rev. **
CY2291
Pin Configurations
CY2291
20-pin SOIC
32XOUT
32K
1
2
3
4
5
6
32XIN
20
19
18
17
16
V
BATT
CLKC
SHUTDOWN/OE
S2/SUSPEND
V
DD
GND
V
DD
S1
15
14
XTALIN
XTALOUT
XBUF
S0
7
13
12
11
CLKF
CLKA
CLKB
8
CLKD
9
CPUCLK
10
Pin Summary
Name
32XOUT
32K
Pin Number Description
1
32.768 kHz crystal feedback.
2
32.768 kHz output (always active if V
Configurable clock output C.
Voltage supply.
is present).
BATT
CLKC
3
V
4, 16
5
DD
GND
Ground.
[1]
XTALIN
6
Reference crystal input or external reference clock input.
Reference crystal feedback.
[1, 2]
XTALOUT
XBUF
CLKD
CPUCLK
CLKB
CLKA
CLKF
S0
7
8
Buffered reference clock output.
Configurable clock output D.
9
10
11
12
13
14
15
17
CPU frequency clock output.
Configurable clock output B.
Configurable clock output A.
Configurable clock output F.
CPU clock select input, bit 0.
CPU clock select input, bit 1.
S1
[3]
S2/SUSPEND
CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
[4]
[4]
SHUTDOWN/OE 18
Places outputs in three-state condition and shuts down chip when LOW. Optionally, only
places outputs in three-state condition and does not shut down chip when LOW.
V
19
20
Battery supply for 32.768-kHz circuit.
32.768-kHz crystal input.
BATT
32XIN
Notes:
1. For best accuracy, use a parallel-resonant crystal, CLOAD ≈ 17 pF or 18 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.
4. The CY2291 has weak pull-downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
2
CY2291
shutdown is enabled, a LOW on this pin also shuts off the
PLLs, counters, the reference oscillator, and all other active
Operation
The CY2291 is a third-generation family of clock generators.
The CY2291 is upwardly compatible with the industry standard
ICD2023 and ICD2028 and continues their tradition by provid-
ing a high level of customizable features to meet the diverse
clock generation needs of modern motherboards and other
synchronous systems.
components. The resulting current on the V pins will be less
DD
than 50 µA (for Commercial Temp. or 100 µA for Industrial
Temp.) plus 15 µA max. for the 32-kHz subsystem and is typ-
ically 10 µA. After leaving shutdown mode, the PLLs will have
to re-lock. All outputs except 32K have a weak pull-down so
[4]
that the outputs do not float when three-stated.
All parts provide a highly configurable set of clocks for PC
motherboard applications. Each of the four configurable clock
outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in
any combination. Multiple outputs configured for the same or
related frequencies will have low (<500 ps) skew, in effect
providing on-chip buffering for heavily loaded signals.
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs except 32K can be shut off in nearly any
combination. The only limitation is that if a PLL is shut off, all
outputs derived from it must also be shut off. Suspending a
PLL shuts off all associated logic, while suspending an output
[3]
[3]
simply forces a three-state condition.
The CY2291 can be configured for either 5V or 3.3V operation.
The internal ROM tables use EPROM technology, allowing full
customization of output frequencies. The reference oscillator
has been designed for 10-MHz to 25-MHz crystals, providing
additional flexibility. No external components are required with
this crystal. Alternatively, an external reference clock of fre-
quency between 1 MHz and 30 MHz can be used. Customers
using the 32-kHz oscillator should connect a 10-MΩ resistor in
parallel with the 32-kHz crystal.
The CPUCLK can slew (transition) smoothly between 8 MHz
and the maximum output frequency (100 MHz at 5V/80 MHz
at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz
at 3.3V for Industrial Temp. and for field-programmed parts).
This feature is extremely useful in “Green” PC and laptop ap-
plications, where reducing the frequency of operation can re-
sult in considerable power savings. This feature meets all 486
and Pentium® processor slewing requirements.
Output Configuration
CyClocks™ Software
The CY2291 has five independent frequency sources on-chip.
These are the 32-kHz oscillator, the reference oscillator, and
three Phase-Locked Loops (PLLs). Each PLL has a specific
function. The System PLL (SPLL) drives the CLKF output and
provides fixed output frequencies on the configurable outputs.
The SPLL offers the most output frequency divider options.
The CPU PLL (CPLL) is controlled by the select inputs
(S0–S2) to provide eight user-selectable frequencies with
smooth slewing between frequencies. The Utility PLL (UPLL)
provides the most accurate clock. It is often used for miscella-
neous frequencies not provided by the other frequency sourc-
es.
CyClocks is an easy-to-use application that allows you to con-
figure any one of the EPROM programmable clocks offered by
Cypress. You may specify the input frequency, PLL and output
frequencies, and different functional options. Please note the
output frequency ranges in this data sheet when specifying
them in CyClocks to ensure that you stay within the limits.
CyClocks also has a power calculation feature that allows you
to see the power consumption of your specific configuration.
You can download a copy of CyClocks for free on Cypress’s
website at www.cypress.com.
Cypress FTG Programmer
All configurations are EPROM programmable, providing short
sample and production lead times. Please refer to the applica-
tion note “Understanding the CY2291, CY2292, and CY2295”
for information on configuring the part.
The Cypress Frequency Timing Generator (FTG) Program-
mers is a portable programmer designed to custom program
our family of EPROM Field Programmable Clock Devices. The
FTG programmers connect to a PC serial port and allow users
of CyClocks software to quickly and easily program any of the
CY2291F, CY2292F, CY2071AF, and CY2907F devices. The
ordering code for the Cypress FTG Programmer is CY3670.
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when
pulled LOW (the 32-kHz clock output is not affected). If system
3
CY2291
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Max. Soldering Temperature (10 sec) ..........................260°C
Junction Temperature...................................................150°C
Package Power Dissipation ...................................... 750 mW
Supply Voltage............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Storage Temperature .................................–65°C to +150°C
Static Discharge Voltage.............................................>2000V
(per MIL-STD-883, Method 3015)
Operating Conditions[5]
Parameter
Description
Part Numbers
Min.
4.5
3.0
2.0
0
Max.
5.5
3.6
5.5
+70
+85
25
Unit
V
V
V
V
Supply Voltage, 5.0V operation
All
All
All
DD
Supply Voltage, 3.3V operation
V
DD
Battery Backup Voltage
V
BATT
T
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
Max. Load Capacitance 5.0V Operation
Max. Load Capacitance 3.3V Operation
External Reference Crystal
CY2291/CY2291F
°C
A
CY2291I/CY2291FI
−40
°C
C
C
All
All
All
All
pF
pF
MHz
MHz
LOAD
LOAD
15
f
10.0
1
25.0
30
REF
[6, 7, 8]
External Reference Clock
Electrical Characteristics, Commercial 5.0V
Parameter
Description
Conditions
Min.
2.4
Typ.
Max.
Unit
V
V
HIGH-Level Output Voltage
LOW-Level Output Voltage
I
I
I
= 4.0 mA
= 4.0 mA
= 0.5 mA
OH
OH
OL
OH
V
0.4
V
OL
V
32.768-kHz HIGH-Level
Output Voltage
V
V
OH–32
BATT
0.5
V
32.768-kHz LOW-Level
Output Voltage
I
= 0.5 mA
0.4
V
OL–32
OL
[9]
V
HIGH-Level Input Voltage
Except crystal pins
Except crystal pins
2.0
V
V
IH
IL
[9]
V
LOW-Level Input Voltage
0.8
10
I
I
I
I
Input HIGH Current
Input LOW Current
V
V
= V –0.5V
<1
<1
µA
µA
µA
mA
IH
IN
IN
DD
= +0.5V
10
IL
Output Leakage Current
Three-state outputs
= V Max., 5V operation
250
100
OZ
DD
[10]
V
Supply Current
V
75
10
5
DD
DD
DD
Commercial
I
I
V
Power Supply Current Shutdown active,
CY2291/CY2291F
50
15
µA
µA
DDS
DD
[10]
in Shutdown Mode
excluding V
BATT
V
Power Supply
V
= 3.0V
BATT
BATT
BATT
Current
Notes:
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is
recommended that a 150Ω pull-up resistor to VDD be connected to the Xout pin.
9. Xtal inputs have CMOS thresholds.
10. Load = Max., VIN = 0V or VDD, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations will vary. Power can be approximated by the following
formula (multiply by 0.65 for 3V operation): IDD=10+0.06•(FCPLL+FUPLL+2•FSPLL)+0.27•(FCLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FCLKF+FXBUF).
4
CY2291
Electrical Characteristics, Commercial 3.3V
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
V
HIGH-Level Output Voltage
LOW-Level Output Voltage
I
I
I
= 4.0 mA
= 4.0 mA
= 0.5 mA
2.4
OH
OH
OL
OH
V
0.4
0.4
V
OL
V
32.768-kHz HIGH-Level
Output Voltage
V
V
OH–32
BATT
0.5
V
32.768-kHz LOW-Level
Output Voltage
I
= 0.5 mA
V
OL–32
OL
[9]
V
HIGH-Level Input Voltage
Except crystal pins
Except crystal pins
2.0
V
V
IH
IL
[9]
V
LOW-Level Input Voltage
0.8
10
I
I
I
I
Input HIGH Current
Input LOW Current
V
V
= V –0.5V
<1
<1
µA
µA
µA
mA
IH
IN
IN
DD
= +0.5V
10
IL
Output Leakage Current
Three-state outputs
= V Max., 3.3V operation
250
65
OZ
DD
[10]
V
Supply Current
V
50
10
5
DD
DD
DD
Commercial
I
V
Power Supply Current Shutdown active,
CY2291/CY2291F
50
15
µA
µA
DDS
DD
[10]
in Shutdown Mode
excluding V
BATT
I
V
Power Supply
V
= 3.0V
BATT
BATT
BATT
Current
Electrical Characteristics, Industrial 5.0V
Parameter
Description
Conditions
Min.
2.4
Typ.
Max.
Unit
V
V
HIGH-Level Output Voltage
LOW-Level Output Voltage
I
I
I
= 4.0 mA
= 4.0 mA
= 0.5 mA
OH
OH
OL
OH
V
0.4
V
OL
V
32.768-kHz HIGH-Level
Output Voltage
V
V
OH–32
BATT
0.5
V
32.768-kHz LOW-Level
Output Voltage
I
= 0.5 mA
0.4
V
OL–32
OL
[9]
V
V
HIGH-Level Input Voltage
Except crystal pins
Except crystal pins
2.0
V
V
IH
IL
[9]
LOW-Level Input Voltage
0.8
10
I
I
I
I
Input HIGH Current
Input LOW Current
V
V
= V –0.5V
< 1
< 1
µA
µA
µA
mA
IH
IN
IN
DD
= +0.5V
10
IL
Output Leakage Current
Three-state outputs
250
110
OZ
DD
[10]
V
Supply Current
V
= V Max., 5V operation
75
10
5
DD
DD
DD
Industrial
I
V
Power Supply Currentin Shutdown active,
CY2291I/CY2291FI
100
15
µA
µA
DDS
DD
[10]
Shutdown Mode
excluding V
BATT
I
V
Power Supply Current
V
= 3.0V
BATT
BATT
BATT
5
CY2291
Electrical Characteristics, Industrial 3.3V
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
V
HIGH-Level Output Voltage
LOW-Level Output Voltage
I
I
I
= 4.0 mA
= 4.0 mA
= 0.5 mA
2.4
OH
OH
OL
OH
V
0.4
0.4
V
OL
V
32.768-kHz HIGH-Level
Output Voltage
V
V
OH–32
BATT
0.5
V
32.768-kHz LOW-Level
Output Voltage
I
= 0.5 mA
V
OL–32
OL
[9]
V
V
HIGH-Level Input Voltage
Except crystal pins
Except crystal pins
2.0
V
V
IH
IL
[9]
LOW-Level Input Voltage
0.8
10
I
I
I
I
Input HIGH Current
Input LOW Current
V
V
= V –0.5V
< 1
< 1
µA
µA
µA
mA
IH
IN
IN
DD
= +0.5V
10
IL
Output Leakage Current
Three-state outputs
= V max., 3.3V operation
250
70
OZ
DD
[10]
V
Supply Current
V
50
10
5
DD
DD
DD
Industrial
I
V
Power Supply Current in
Shutdown active,
excluding V
CY2291I/CY2291FI
100
15
µA
µA
DDS
DD
[10]
Shutdown Mode
BATT
I
V
Power Supply Current
V
= 3.0V
BATT
BATT
BATT
6
CY2291
Switching Characteristics, Commercial 5.0V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t
Output Period
Clock output range,
5V operation
CY2291
10
13000
(76.923 kHz)
ns
1
(100 MHz)
CY2291F
11.1
13000
ns
(90 MHz)
(76.923 kHz)
[12]
[12]
Output Duty
Cycle
Duty cycle for outputs, defined as t ÷ t
40%
50%
50%
60%
2
1
[11]
f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t ÷ t
45%
55%
2
1
f
< 66 MHZ
OUT
[13]
t
t
t
Rise Time
Fall Time
Output clock rise time
3
5
4
ns
ns
ns
3
4
5
[13]
Output clock fall time
2.5
10
Output Disable
Time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
15
t
t
t
t
t
t
t
t
t
Output Enable
Time
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
10
15
0.5
20.0
1
ns
ns
6
Skew
Skew delay between any identical or related out-
< 0.25
7
[3, 12, 15]
puts
CPUCLK Slew
Frequency transition rate
1.0
MHz/
ms
8
[14]
Clock Jitter
Peak-to-peak period jitter (t Max. – t min.),
<0.5
<0.7
<400
<250
<25
%
ns
ps
ps
ms
ms
9A
9B
9C
9D
10A
10B
9A
9A
% of clock period (f
< 4 MHz)
OUT
[14]
Clock Jitter
Peak-to-peak period jitter (t Max. – t min.)
1
9B
9B
(4 MHz < f
< 16 MHz)
OUT
[14]
Clock Jitter
Peak-to-peak period jitter
(16 MHz < f < 50 MHz)
500
350
50
1
OUT
[14]
Clock Jitter
Peak-to-peak period jitter
(f > 50 MHz)
OUT
Lock Time for
CPLL
Lock Time from Power-Up
Lock Time from Power-Up
CPU PLL Slew Limits
Lock Time for
UPLL and SPLL
<0.25
Slew Limits
CY2291
8
8
100
90
MHz
MHz
CY2291F
Notes:
11. XBUF duty cycle depends on XTALIN duty cycle.
12. Measured at 1.4V.
13. Measured between 0.4V and 2.4V.
14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the
application note: “Jitter in PLL-Based Systems.”
15. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.
7
CY2291
Switching Characteristics, Commercial 3.3V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t
Output Period
Clock output range, 3.3V CY2291
operation
12.5
(80 MHz)
13000
(76.923 kHz)
ns
1
CY2291F
15
13000
ns
(66.6 MHz)
(76.923 kHz)
[12]
[12]
Output Duty
Cycle
Duty cycle for outputs, defined as t ÷ t
40%
50%
50%
60%
2
1
[11]
f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t ÷ t
45%
55%
2
1
f
< 66 MHZ
OUT
[13]
t
t
t
Rise Time
Fall Time
Output clock rise time
3
5
4
ns
ns
ns
3
4
5
[13]
Output clock fall time
2.5
10
Output Disable
Time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
15
t
t
t
t
t
t
t
t
t
Output Enable
Time
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
10
15
0.5
20.0
1
ns
ns
6
Skew
Skew delay between any identical or related
< 0.25
7
[3, 12, 15]
outputs
CPUCLK Slew
Frequency transition rate
1.0
MHz/
ms
8
[14]
Clock Jitter
Peak-to-peak period jitter (t Max. – t min.),
<0.5
<0.7
<400
<250
<25
%
ns
ps
ps
ms
ms
9A
9B
9C
9D
10A
10B
9A
9A
% of clock period (f
< 4 MHz)
OUT
[14]
Clock Jitter
Peak-to-peak period jitter (t Max. – t min.)
1
9B
9B
(4 MHz < f
< 16 MHz)
OUT
[14]
Clock Jitter
Peak-to-peak period jitter
(16 MHz < f < 50 MHz)
500
350
50
1
OUT
[14]
Clock Jitter
Peak-to-peak period jitter
(f > 50 MHz)
OUT
Lock Time for
CPLL
Lock Time from Power-Up
Lock Time from Power-Up
CPU PLL Slew Limits
Lock Time for
UPLL and SPLL
<0.25
Slew Limits
CY2291
8
8
80
MHz
MHz
CY2291F
66.6
8
CY2291
Switching Characteristics, Industrial 5.0V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t
Output Period
Clock output range,
5V operation
CY2291I
11.1
(90 MHz)
13000
(76.923 kHz)
ns
1
CY2291FI
12.5
13000
ns
(80 MHz)
(76.923 kHz)
[12]
[12]
Output Duty
Cycle
Duty cycle for outputs, defined as t ÷ t
40%
50%
50%
60%
2
1
[11]
f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t ÷ t
45%
55%
2
1
f
< 66 MHZ
OUT
[13]
t
t
t
Rise Time
Fall Time
Output clock rise time
3
5
4
ns
ns
ns
3
4
5
[13]
Output clock fall time
2.5
10
Output Disable
Time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
15
t
t
t
t
t
t
t
t
t
Output Enable
Time
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
10
15
0.5
20.0
1
ns
ns
6
Skew
Skew delay between any identical or related
< 0.25
7
[3, 12, 15]
outputs
CPUCLK Slew
Frequency transition rate
1.0
MHz/
ms
8
[14]
Clock Jitter
Peak-to-peak period jitter (t Max. – t min.),
<0.5
<0.7
<400
<250
<25
%
9A
9B
9C
9D
10A
10B
9A
9A
% of clock period (f
< 4 MHz)
OUT
[14]
Clock Jitter
Peak-to-peak period jitter (t Max. – t min.)
1
ns
9B
9B
(4 MHz < f
< 16 MHz)
OUT
[14]
Clock Jitter
Peak-to-peak period jitter
(16 MHz < f < 50 MHz)
500
350
50
ps
OUT
[14]
Clock Jitter
Peak-to-peak period jitter
(f > 50 MHz)
ps
OUT
Lock Time for
CPLL
Lock Time from Power-Up
Lock Time from Power-Up
CPU PLL Slew Limits
ms
ms
Lock Time for
UPLL and SPLL
<0.25
1
Slew Limits
CY2291I
8
8
90
80
MHz
MHz
CY2291FI
9
CY2291
Switching Characteristics, Industrial 3.3V
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t
Output Period
Clock output range, 3.3V CY2291I
operation
15
13000
(76.923 kHz)
ns
1
(66.6 MHz)
CY2291FI
16.66
13000
ns
(60 MHz)
(76.923 kHz)
[12]
[12]
Output Duty
Cycle
Duty cycle for outputs, defined as t ÷ t
40%
50%
50%
60%
2
1
1
[11]
f
> 66 MHZ
OUT
Duty cycle for outputs, defined as t ÷ t
45%
55%
2
f
< 66 MHZ
OUT
[13]
t
t
t
Rise Time
Fall Time
Output clock rise time
3
5
4
ns
ns
ns
3
4
5
[13]
Output clock fall time
2.5
10
Output Disable
Time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
15
t
t
t
t
t
t
t
t
t
Output Enable
Time
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
10
15
0.5
20.0
1
ns
ns
6
Skew
Skew delay between any identical or related out-
< 0.25
7
[3, 12, 15]
puts
CPUCLK Slew
Frequency transition rate
1.0
MHz/
ms
8
[14]
Clock Jitter
Peak-to-peak period jitter (t Max. – t min.),
<0.5
<0.7
<400
<250
<25
%
9A
9B
9C
9D
10A
10B
9A
9A
% of clock period (f
< 4 MHz)
OUT
[14]
Clock Jitter
Peak-to-peak period jitter (t Max. – t min.)
1
ns
9B
9B
(4 MHz < f
< 16 MHz)
OUT
[14]
Clock Jitter
Peak-to-peak period jitter
(16 MHz < f < 50 MHz)
500
350
50
ps
OUT
[14]
Clock Jitter
Peak-to-peak period jitter
(f > 50 MHz)
ps
OUT
Lock Time for
CPLL
Lock Time from Power-Up
Lock Time from Power-Up
CPU PLL Slew Limits
ms
ms
Lock Time for
UPLL and SPLL
<0.25
1
Slew Limits
CY2291I
8
8
66.6
60
MHz
MHz
CY2291FI
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t
1
t
2
OUTPUT
t
3
t
4
10
CY2291
Switching Waveforms (continued)
[4]
Output Three-State Timing
OE
t
5
t
6
ALL
THREE-STATE
OUTPUTS
CLK Outputs Jitter and Skew
t
9A
CLK
OUTPUT
t7
RELATED
CLK
CPU Frequency Change
OLD SELECT
NEW SELECT STABLE
t & t
SELECT
CPU
F
new
F
old
8
10
Test Circuit
V
DD
CLK out
0.1 F
µ
C
OUTPUTS
LOAD
V
DD
0.1 F
µ
GND
11
CY2291
Ordering Information
Package
Name
Operating
Range
Operating
Voltage
Ordering Code
CY2291SC–XXX
CY2291SL–XXX
CY2291F
Package Type
20-Pin SOIC
S5
S5
S5
S5
S5
Commercial
5.0V
3.3V
20-Pin SOIC
20-Pin SOIC
20-Pin SOIC
20-Pin SOIC
Commercial
Commercial
Industrial
3.3V or 5.0V
3.3V or 5.0V
3.3V or 5.0V
CY2291SI–XXX
CY2291FI
Industrial
Document #: 38-00945-**
CyClocks is a trademark of Cypress Semiconductor Corporation.
Pentium is a registered trademark of Intel Corporation.
Custom Configuration Request Procedure
The CY229x are EPROM-programmable devices that may be configured in the factory or in the field by a Cypress Field Application
Engineer (FAE). The output frequencies requested will be matched as closely as the internal PLL divider and multiplier options
allow. All custom requests must be submitted to your local Cypress FAE or sales representative. The method to use to request
custom configurations is:
Use CyClocks™ software. This software automatically calculates the output frequencies that can be generated by the CY229x
devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales
representative. The CyClocks software is available free of charge from the Cypress website (http://www.cypress.com) or from
your local sales representative.
Once the custom request has been processed you will receive a part number with a 3-digit extension (e.g., CY2292SC-128)
specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production
orders.
Package Characteristics
Package
θ
(C/W)
θ
(C/W)
JC
Transistor Count
JA
20-pin SOIC
125
25
9271
12
CY2291
Package Diagram
20-Lead (300-Mil) Molded SOIC S5
51-85024-A
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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