CY2300_08 [CYPRESS]
Phase-Aligned Clock Multiplier; 相位对齐的时钟乘法器
| 型号： | CY2300_08 |
| 厂家： | 
CYPRESS |
| 描述： | Phase-Aligned Clock Multiplier |
| 文件： | 总6页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2300
Phase-Aligned Clock Multiplier
Features
Benefits
■ 4-multiplier configuration
■ Single phase-locked loop architecture
■ Phase Alignment
■ 1/2x, 1x, 1x, 2x Ref
■ 10 MHz to 166.67 MHz operating range (reference input from
20 MHz to 83.33 MHz)
■ Alloutputshaveaconsistentphaserelationshipwitheachother
and the reference input
■ Low jitter, high accuracy outputs
■ Output enable pin
■ Meets critical timing requirements
■ 3.3V operation
■ Enables design flexibility and lower power
consumption
■ 5V Tolerant input
■ Supports industry standard design platforms
■ Allows flexibility on Reference input
■ Internal loop filter
■ 8-pin 150-mil SOIC package
■ Commercial Temperature
■ Alleviates the need for external components
■ Industry standard packaging saves on board space
■ Suitable for wide spectrum of applications
Logic Block Diagram
FBK
PLL
1/2xREF
/2
REFIN
REF
Divider
Logic
REF
2xREF
OE
Cypress Semiconductor Corporation
Document #: 38-07252 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 23, 2008
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CY2300
Pinouts
Figure 1. CY2300 - 8-pin SOIC - Top View
OE
1
2
3
4
8
7
6
5
1/2xREF
V
DD
GND
REFIN
REF
2xREF
REF
Table 1. Pin Definitions
Pin
Signal[1]
Description
1
2
3
4
5
6
7
8
1/2xREF
Clock output, 1/2x Reference
Ground
GND
REFIN
REF
Input Reference frequency, 5V tolerant input
Clock output Reference
REF
Clock output Reference
2xREF
VDD
OE
Clock output, 2x Reference
3.3V Supply
Output Enable (weak pull up)
Functional Description
Maximum Ratings
The CY2300 is a 4-output 3.3V phase-aligned system clock
designed to distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance applications.
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V
DC Input Voltage REF ........................................... –0.5 to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature................................................. 150°C
The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN
output frequencies on respective output pins.
The part has an on-chip PLL which locks to an input clock
presented on the REFIN pin. The input-to-output skew is
guaranteed to be less than ±200 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............................>2000V
Multiple CY2300 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 400 ps.
The CY2300 is available in commercial temperature range.
Operating Conditions
Parameter
VDD
Description
Min
3.0
0
Max
3.6
70
18
12
7
Unit
V
Supply Voltage
TA
CL
Operating Temperature (Ambient Temperature)
Load Capacitance, Fout < 133.33 MHz
Load Capacitance,133.33 MHz < Fout < 166.67 MHz
Input Capacitance
°C
pF
pF
pF
CIN
tPU
Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
0.05
50
ms
Note
1. Weak pull down on all outputs.
Document #: 38-07252 Rev. *C
Page 2 of 6
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CY2300
Electrical Characteristics
Parameter
Description
Min
Max
Unit
V
VIL
VIH
IIL
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage[2]
Output HIGH Voltage[2]
Supply Current
0.8
2.0
V
VIN = 0V
100
50
μA
μA
V
IIH
VIN = VDD
VOL
VOH
IDD
IOL = 8 mA
0.4
IOH = –8 mA
2.4
V
Unloaded outputs, REFIN = 66 MHz
Unloaded outputs, REFIN = 33 MHz
Unloaded outputs, REFIN = 20 MHz
45
32
18
mA
mA
mA
Switching Characteristics
Parameter
Name
Test Conditions
18-pF load
Min
Typ.
Max
Unit
MHz
MHz
%
1/t1
Output Frequency
10
133.33
166.67
60
12-pF load
Duty Cycle[3] = t2 ÷ t1
Rise Time[3]
Measured at VDD/2
40
50
t3
t4
t5
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
1.20
1.20
200
ns
Fall Time[3]
ns
Output to Output Skew on
rising edges[3]
All outputs equally loaded
Measured at VDD/2
ps
t6
t7
Delay, REFIN Rising Edge to Measured at VDD/2 from REFIN to any
±200
ps
ps
Output Rising Edge[3]
output
Device to Device Skew[3]
Measured at VDD/2 on the 1/2xREF pin
of
400
devices (pin 1)
Period Jitter[3]
tJ
Measured at Fout=133.33 MHz, loaded
outputs, 18-pF load
±175
ps
PLL Lock Time[3]
tLOCK
Stable power supply, valid clocks
presented on REFIN
1.0
ms
Switching Waveforms
Figure 2. Duty Cycle Timing
t
1
t
2
VDD/2
Notes
2. Parameter is guaranteed by design and characterization. It is not 100% tested in production.
3. All parameters are specified with equally loaded outputs.
Document #: 38-07252 Rev. *C
Page 3 of 6
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CY2300
Switching Waveforms (continued)
Figure 3. All Outputs Rise/Fall Time
3.3V
0V
2.0V
0.8V
2.0V
0.8V
OUTPUT
t
3
t
4
Figure 4. Output-Output Skew
VDD/2
OUTPUT
OUTPUT
VDD/2
t
5
Figure 5. Input-Output Propagation Delay
VDD/2
REFIN
VDD/2
OUTPUT
t6
Figure 6. Device-Device Skew
V
DD/2
1/2xREF, Device1
1/2xREF, Device2
VDD/2
t7
Test Circuits
Test Circuit # 1
VDD
CLK OUT
CLOAD
0.1 μF
OUTPUTS
GND
Document #: 38-07252 Rev. *C
Page 4 of 6
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CY2300
Ordering Information
Ordering Code
Pb-Free
Package Type
Operating Range
CY2300SXC
8-pin 150-mil SOIC
8-pin 150-mil SOIC - Tape and Reel
Commercial
Commercial
CY2300SXCT
Package Drawing and Dimensions
Figure 7. 8-Pin (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 38-07252 Rev. *C
Page 5 of 6
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CY2300
Document History Page
Document Title: CY2300 Phase-Aligned Clock Multiplier
Document Number: 38-07252
Orig. of
Change
Submission
Date
REV.
ECN
Description of Change
**
110517
121854
246829
2568533
SZV
RBI
01/07/02
12/14/02
08/02/04
09/23/08
Change from Spec number: 38-01039 to 38-07252
*A
*B
*C
Power up requirements added to Operating Conditions Information
Added Lead Free Devices
RGL
AESA
Updated template.
Removed Selector Guide.
Removed Operating Conditions for CY2300SI Industrial Temperature
Devices.
Removed Electrical Characteristics for CY2300SI Industrial Temper-
ature Devices.
Removed Switching Characteristics for CY2300SI Industrial Temper-
ature Devices.
Removed part number CY2300SC, CY2300SC, CY2300SI, CY2300SI,
CY2300SXI and CY2300SXIT.
Sales, Solutions, and Legal Information
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closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07252 Rev. *C
Revised September 23, 2008
Page 6 of 6
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