CY2308AZI-2 [CYPRESS]
PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16;
| 型号： | CY2308AZI-2 |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16 光电二极管 |
| 文件： | 总8页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2308A
Eight-Output, 200-MHz Zero Delay Buffer
Features
Functional Description
• 50-MHz to 200-MHz operating range
The CY2308A is a high-performance 200-MHz zero delay
buffer designed for high-speed clock distribution. The
• 650-ps Total Timing Budget (TTB ) window
• Multiple configurations (see Table 2)
• Eight low-skew outputs
integrated PLL is designed for low jitter and optimized for noise
rejection. These parameters are critical for reference clock
distribution in systems using high-performance ASICs and
microprocessors. The CY2308A PLL feedback is external and
is required to be driven into the FBK pin using anyone of the
outputs.
— Output-output skew < 200 ps
— Device-device skew < 500 ps
• Input-output skew < 250 ps
• Three-stateable outputs
The device features a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
• < 50-µA shutdown current
• Phase-locked loop (PLL) bypass mode (see Table 1)
• Spread Aware
The CY2308A has two banks of four outputs each that can be
controlled by the Select inputs as shown in Table 1. If all output
clocks are not required, Bank B can be three-stated. The
select inputs also allow the input clock to be directly applied to
the output for chip and system testing purposes.
• 16-pin TSSOP
• 3.3V operation
• Commercial/Industrial temperature
The CY2308A PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
50 µA of current draw. The PLL shuts down in two additional
cases, as shown in Table 1.
The CY2308A is available in five different configurations, as
shown in Table 2. The CY2308A–1 is the base part with the
output frequencies equal to the reference if there is no divider
in the feedback path. The CY2308A–1H is the high-drive
version of the –1 with faster rise and fall times.
The CY2308A–2 allows the user to obtain 1X / ½X frequencies
on each output bank. The exact configuration and output
frequencies depends on which output drives FBK.
Pin Configuration
Block Diagram
TSSOP
Top View
FBK
PLL
REF
MUX
1
2
3
4
5
6
7
8
16
REF
FBK
CLKA1
CLKA2
CLKA3
CLKA4
15
14
13
12
11
10
9
CLKB1
CLKA1
CLKA2
CLKB2
V
V
DD
DD
GND
GND
CLKA3
CLKA4
S1
CLKB3
S2
Select Input
Decoding
CLKB4
S2
S1
/2
CLKB1
CLKB2
CLKB3
CLKB4
Extra Divider (–2)
Cypress Semiconductor Corporation
Document #: 38-07377 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 5, 2003
CY2308A
Pin Description
Pin
Signal
Description
Input reference frequency, 5V-tolerant input
Clock output, Bank B
Clock output, Bank B
3.3V supply
1
2
REF
CLKB1[2]
CLKB2[2]
VDD
3
4
5
GND
Ground
6
CLKB3[2]
CLKB4[2]
S2[1]
Clock output, Bank B
Clock output, Bank B
Select input, 5V-tolerant input
Select input, 5V-tolerant input
Clock output, Bank A
Clock output, Bank A
Ground
7
8
9
S1[1]
10
11
12
13
14
15
16
CLKA4[2]
CLKA3[2]
GND
VDD
3.3V supply
CLKA2[2]
CLKA1[2]
FBK
Clock output, Bank A
Clock output, Bank A
PLL feedback input
Table 1. Select Input Decoding
S2
0
S1
0
CLOCK A1–A4
CLOCK B1–B4
Three-state
Three-state
Driven
Output Source
PLL Shutdown
Three-state
Driven
PLL
PLL
Y
N
Y
N
0
1
1
0
Driven
Reference
PLL
1
1
Driven
Driven
Table 2. Available CY2308A Configurations
Device
CY2308A–1
CY2308A–1H
CY2308A–2
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank A Frequency
Bank B Frequency
Reference
Reference
Reference
Reference
Reference/2
Reference
Reference
CY2308A–2
Bank B
Reference X2
Notes:
1. Weak pull-up.
2. Weak pull-down.
Document #: 38-07377 Rev. *C
Page 2 of 8
CY2308A
Maximum Ratings
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Junction Temperature.................................................. 125°C
Junction-to-Ambient Thermal Resistance
DC Input Voltage
(Except Ref, S1, S2) ..............................–0.5V to VDD + 0.5V
16-pin TSSOP ......................................................... 115°C/W
DC Input Voltage (REF, S1, S2).............................–0.5 to 7V
Static Discharge Voltage
Storage Temperature ..................................–65°C to +150°C
(per MIL-STD-883, Method 3015) ............................> 2000V
Table 3. Operating Conditions for CY2308AZC–XX Commercial Temperature Devices
Parameter
VDD
Description
Min.
3.135
0
Max.
3.465
70
Unit
V
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
Input Capacitance
°C
CIN
tPU
7
pF
ms
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
Table 4. Electrical Characteristics for CY2308AZC–XX Commercial Temperature Devices
Parameter
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Test Conditions
CMOS Levels, 30% of VDD
Min.
Max.
Unit
VIL
VIH
IIL
0.25
VDD
VDD
µA
CMOS Levels, 70% of VDD
VIN = 0V
0.7
50.0
10.0
IIH
VIN = VDD
µA
IOL
Output LOW Current[3] (–1, –2) VOL = 0.5V
12
18
mA
(–1H)
IOH
Output HIGH Current[3] (–1, –2) VOH = VDD – 0.5V
–12
–18
50
mA
(–1H)
IDDS
IDD
Power-down Supply Current
Supply Current
REF = 0V, S1 = VDD, S2 = VDD
µA
Unloaded outputs @ 200 MHz
115
145
mA
Loaded outputs @ 200 MHz, CL = 10 pF
Table 5. Switching Characteristics for CY2308AZC–XX Commercial Temperature Devices[4]
Parameter
Name
Test Conditions
Min.
50
Typ.
Max.
200
4
Unit
MHz
V/ns
%
Reference Frequency
Reference Edge Rate
Reference Duty Cycle
Output Frequency
30% to 70% of VDD
0.5
25
75
200
140
55.0
4
t1
CL = 10 pF
50
MHz
MHz
%
CL = 15 pF
50
Duty Cycle[3] = t2÷ t1
Measured at VDD/2
45.0
0.8
1
50.0
t3
Rising Edge Rate[3] (–1, –2) 20% to 80% of VDD, CL = 15 pF
Rising Edge Rate[3] (–1H) 20% to 80% of VDD, CL = 15 pF
Falling Edge Rate[3] (–1, –2) 80% to 20% of VDD, CL = 15 pF
Falling Edge Rate[3] (–1H) 80% to 20% of VDD, CL = 15 pF
TTB window, Bank A and B Outputs @ 200 MHz, Tracking Skew Not
V/ns
V/ns
V/ns
V/ns
ps
4
t4
0.8
1
4
4
tTB
650
Same Frequency[5]
Included
TTB window, Bank A and B
Different Frequency[5]
850
Notes:
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4. All parameters are specified with loaded outputs.
5.
tTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-
cycle jitter, and dynamic phase error. tTB will be equal to or smaller than the maximum specified value at a given output frequency.
Document #: 38-07377 Rev. *C
Page 3 of 8
CY2308A
Table 5. Switching Characteristics for CY2308AZC–XX Commercial Temperature Devices[4] (continued)
Parameter
t5
Name
Test Conditions
Min.
Typ.
Max.
200
Unit
ps
Output-to-Output Skew[3] All Outputs Equally Loaded
t6
Input-to-Output Skew
(Static Phase Error)[3]
Measured at VDD/2, REF to FBK
250
ps
t7
tJ
Device-to-Device Skew[3] Measured at VDD/2
500
200
35
ps
ps
Cycle-to-Cycle Jitter,[3]
Bank A and B Same
Frequency
Loaded Outputs
psRMS
Cycle-to-Cycle Jitter,[3]
Bank A and B Different
Frequency
Loaded Outputs
400
70
ps
psRMS
tLOCK
PLL Lock Time[3]
Stable Power Supply, Valid Clock at REF
1.0
ms
Table 6. Operating Conditions for CY2308AZI–XX Industrial Temperature Devices
Parameter Description
VDD
Min.
3.135
–40
Max.
Unit
Supply Voltage
3.465
85
V
TA
Operating Temperature (Ambient Temperature)
Input Capacitance
°C
pF
ms
CIN
tPU
7
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
Table 7. Electrical Characteristics for CY2308AZI-XX Industrial Temperature Devices
Parameter
Description
Input LOW Voltage
Test Conditions
CMOS Levels, 30% of VDD
CMOS Levels, 70% of VDD
VIN = 0V
Min.
Max.
Unit
VDD
VDD
µA
VIL
VIH
IIL
0.25
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Current[3] (–1, –2)
(–1H)
0.7
50.0
10.0
IIH
VIN = VDD
µA
IOL
VOL = 0.5V
10
15
mA
IOH
Output HIGH Current[3] (–1, –2)
VOH = VDD – 0.5V
–10
–15
mA
(–1H)
IDDS
IDD
Power-down Supply Current
Supply Current
REF = 0V, S1 = VDD, S2 = VDD
Unloaded outputs @ 133 MHz
50
µA
80.0
110.0
mA
Loaded outputs @ 133 MHz, CL = 10 pF
Table 8. Switching Characteristics for CY2308AZI–XX Industrial Temperature Devices[4]
Parameter
Name
Test Conditions
Min.
50
Typ.
Max.
Unit
MHz
V/ns
%
Reference Frequency
Reference Edge Rate
Reference Duty Cycle
Output Frequency
133
4
30% to 70% of VDD
0.5
25
75
133
60.0
3
t1
CL = 10 pF
50
MHz
%
Duty Cycle[3] = t2 ÷ t1
Measured at VDD/2
40.0
0.5
0.8
0.5
0.8
50.0
t3
t4
Rising Edge Rate[3] (–1, –2) 20% to 80% of VDD, CL = 15 pF
Rising Edge Rate[3] (–1H)
20% to 80% of VDD, CL = 15 pF
Falling Edge Rate[3] (–1, –2) 80% to 20% of VDD, CL = 15 pF
Falling Edge Rate[3] (–1H)
80% to 20% of VDD, CL = 15 pF
V/ns
V/ns
V/ns
V/ns
4
3
4
Document #: 38-07377 Rev. *C
Page 4 of 8
CY2308A
Table 8. Switching Characteristics for CY2308AZI–XX Industrial Temperature Devices[4] (continued)
Parameter Name Test Conditions Min. Typ.
tTB Total Timing Budget window, Outputs @ 133 MHz, Tracking Skew Not
Max.
Unit
650
ps
Bank A and B Same
Included
Frequency[5]
Total Timing Budget window,
Bank A and B Different
Frequency[5]
850
t5
t6
Output-to-Output Skew[3]
All Outputs Equally Loaded
200
250
ps
ps
Input-to-Output Skew (Static Measured at VDD/2, REF to FBK
Phase Error)[3]
t7
tJ
Device-to-Device Skew[3]
Cycle-to-Cycle Jitter[3], Bank Loaded Outputs
Measured at VDD/2
500
200
35
ps
ps
A and B Same Frequency
psRMS
ps
Cycle-to-Cycle Jitter[3], Bank Loaded Outputs
A and B Different Frequency
400
70
psRMS
ms
tLOCK
PLL Lock Time[3]
Stable Power Supply, Valid Clock at REF
1.0
REF. Input to CLKA/CLKB Delay vs. Difference in Loading
Between FBK Pin and CLKA/CLKB Pins
Zero Delay and Skew Control
To close the feedback loop of the CY2308A, the FBK can be
driven from any of the eight available output pins. The output
driving the FBK will be driving a total load of 7 pF plus any
additional load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the input-
output delay. See REF Input to CLK Delay vs. Loading
Difference.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally
loaded. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the
feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
For further information on using CY2308A, refer to the appli-
cation note CY2308: Zero Delay Buffer.
Document #: 38-07377 Rev. *C
Page 5 of 8
CY2308A
Test Circuits
Duty Cycle Timing
Test Circuit
VDD
t
1
t
2
CLK OUT
CLOAD
0.1 µF
V
/2
V
/2
V
/2
DD
OUTPUTS
VDD
DD
DD
0.1 µF
GND
GND
Switching Waveforms
All Outputs Rise/Fall Time
VDD
0V
80%
OUTPUT
20%
80%
20%
t
3
t
4
Output-Output Skew
V
/2
DD
OUTPUT
V
/2
DD
OUTPUT
t
5
Input-Output Propagation Delay
V
/2
DD
INPUT
V
/2
DD
OUTPUT
t
6
Device-Device Skew
V
/2
DD
FBK, Device 1
V
/2
DD
FBK, Device 2
t
7
Ordering Information
Ordering Code
CY2308AZC-1
Package Type
16-pin 4.4-mm TSSOP
Operating Range
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
CY2308AZC–1T
CY2308AZC–1H
CY2308AZC–1HT
CY2308AZC–2
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 4.4-mm TSSOP
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 4.4-mm TSSOP
CY2308AZC–2T
CY2308AZI-1
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 4.4-mm TSSOP
CY2308AZI-1T
16-pin 4.4-mm TSSOP – Tape and Reel
Document #: 38-07377 Rev. *C
Page 6 of 8
CY2308A
Ordering Information (continued)
Ordering Code
Package Type
Operating Range
CY2308AZI–1H
CY2308AZI–1HT
CY2308AZI-2
16-pin 4.4-mm TSSOP
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 4.4-mm TSSOP
CY2308AZI-2T
16-pin 4.4-mm TSSOP – Tape and Reel
Package Diagram
16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
Spread Aware, Total Timing Budget, and TTB are trademarks of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07377 Rev. *C
Page 7 of 8
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2308A
Document History Page
Document Title: CY2308A Eight-Output, 200-MHz Zero Delay Buffer
Document Number: 38-07377
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
**
112938 04/02/02
114685 07/17/02
CTK New Data Sheet
*A
HWT Change freq. of operation to 50 MHz–200 MHz
Eliminate specification related to 30-pF load
*B
*C
121892 12/14/02
124597 03/06/03
RBI
Power-up requirements added to Operating Conditions information
RGL Changed VIL max value in Commercial Temp. Device from 0.3V to 0.25V
Changed IDD max values in Commercial Temp. Device from 75 and 150 to 115 and 145
mA, respectively
Changed VIL max value in Industrial Temp Device from 0.3V to 0.25V
Changed IDD max value in Industrial Temp Device from 60 and 120 mA to 80 and 110 mA
Removed Preliminary (final data sheet)
Document #: 38-07377 Rev. *C
Page 8 of 8
相关型号：
CY2308AZI-2T
PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16
CYPRESS
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