CY2410SXC-1 [CYPRESS]
Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8;
| 型号： | CY2410SXC-1 |
| 厂家： | 
CYPRESS |
| 描述： | Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总7页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2410
MPEG Clock Generator with VCXO
• Application compatibility for a wide variety of designs
• Enables design compatibility
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• Advanced Features
• Serial programming interface (CY2410-3 only)
• Lower drive strength settings (CY2410-4, -6)
• Matches nonlinear MK3727A VCXO control curve (-5, -6)
• Matches nonlinear MK3727C VCXO control curve (-7)
• 3.3V operation
• Compatible with MK3727 (–1, –4, –5, –6, –7)
Benefits
Benefits
• Highest-performance PLL tailored for multimedia applica-
tions
• Digital VCXO control
• Electromagnetic interference (EMI) reduction for standards
compliance
• Meets critical timing requirements in complex system
designs
• Second source for existing designs
• Large ±150-ppm range, better linearity
Part
Number
Output
Frequencies
VCXO Control
Curve
Outputs
Input Frequency Range
Other Features
CY2410–1
1
13.5-MHz pullable crystal input per 1 copy of 27 MHz linear
Cypress specification
Compatible with MK3727
CY2410–3
CY2410–4
CY2410–5
CY2410–6
CY2410–7
1
1
1
1
1
13.5-MHz pullable crystal input per 1 copy of 27 MHz linear
Cypress specification
Serial programming interface
13.5-MHz pullable crystal input per 1 copy of 27 MHz linear
Cypress specification
Same as CY2410–1 except
lower drive strength settings
13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear
Cypress specification
Matches MK3727A nonlinear
VCXO Control Curve
13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear
Cypress specification
Same as CY2410–5 except
lower drive strength
13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear
Cypress specification
Matches MK3727C nonlinear
VCXO control curve
CY2410–1,–4,–5,–6,–7 Logic Block Diagram
CY2410–3 Logic Block Diagram
13.5 XIN
XOUT
OUTPUT
OSC
Q
Φ
27 MHz
DIVIDERS
VCO
13.5 XIN
OUTPUT
OSC
Q
Φ
27 MHz
P
DIVIDERS
XOUT
VCO
PLL
P
VCXO
PLL
Digital VCXO
Serial
SCLK
SDAT
VSS
VDD
VSS
VDD
Programming
Interface
Pin Configurations
CY2410–3
8-pin SOIC
CY2410–1,–4,–5,–6,–7
8-pin SOIC
1
2
3
4
XOUT
8
7
6
5
XIN
1
2
3
4
XOUT
8
7
6
5
XIN
NC or VSS
27 MHz
SCLK
VDD
SDAT
VSS
NC or VSS
VDD
VCXO
VSS
NC or VDD
27 MHz
Cypress Semiconductor Corporation
Document #: 38-07317 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised December 11, 2003
CY2410
Pin Descriptions for CY2410–1, –4, –5, –6, –7
Name
Pin Number
Description
XIN
1
2
3
4
5
6
7
8
Reference crystal input
Voltage supply
VDD
VCXO
VSS
Input analog control for VCXO
Ground
27 MHz
NC/VDD
NC/VSS
27-MHz clock output
No Connect or voltage supply
No Connect or ground
Reference crystal output
[1]
XOUT
Pin Description for CY2410–3
Name
Pin Number
Description
XIN
1
2
3
4
5
6
7
8
Reference crystal input
Voltage supply
VDD
SDAT
VSS
Serial data input for DCXO control
Ground
SCLK
27 MHz
NC/VSS
Serial clock input for DCXO control
27-MHz clock output
No Connect or ground
Reference crystal output
[1]
XOUT
Pullable Crystal Specifications[2]
Parameter
Description
Nominal crystal frequency
Condition
Min.
Typ.
Max.
Unit
FNOM
Parallel resonance, funda-
mental mode, AT cut
–
13.5
–
MHz
CLNOM
R1
Nominal load capacitance
–
–
3
14
–
–
25
–
pF
Equivalent series resistance (ESR)
Fundamental mode
Ω
R3/R1
Ratio of third overtone mode ESR to fundamen- Ratio used because typical
–
tal mode ESR
R1 values are much less
than the maximum spec.
DL
Crystal drive level
No external series resistor
assumed
–
0.5
2.0
mW
F3SEPHI
F3SEPLO
C0
Third overtone separation from 3*FNOM
Third overtone separation from 3*FNOM
Crystal shunt capacitance
High side
Low side
300
–
–
–
–
ppm
ppm
pF
–150
7
–
–
C0/C1
C1
Ratio of shunt to motional capacitance
Crystal motional capacitance
180
14.4
–
250
21.6
18
pF
Notes:
1. Float XOUT if XIN is externally driven.
2. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC.
Document #: 38-07317 Rev. *D
Page 2 of 7
CY2410
Serial Programmable Interface Protocol
Transition
to next bit
Data Valid
The CY2410-3 utilizes a two-wire-interface SDAT and SCLK
that operates up to 400 kbits/sec in Read or Write mode. The
basic Write serial format is as follows: start bit; 7-bit device
address (DA); R/W bit; slave clock acknowledge (ACK); 8-bit
memory address (MA); ACK; 8-bit data; ACK; 8-bit data in
MA+1 if desired; ACK; 8-bit data in MA+2; ACK; etc. until stop
bit, as illustrated in Figure 1.
SDAT
SCLK
t
t
SU
DH
1-bit
1-bit
1-bit
Slave
ACK
CLK
HIGH
1-bit
R/W = 0
Slave
Slave
SDA Write
V
IH
IL
ACK ACK
CLK
7-bit
Device
Address
8-bit
Register
Data
V
LOW
8-bit
Register
Address
Stop Signal
Start Signal
Figure 2. Data Valid and Data Transition Periods
Figure 1. Data Frame Architecture
Data Valid
SDAT
SCLK
Data is valid when the clock is HIGH, and may only be transi-
tioned when the clock is low as illustrated in Figure 2.
Data Frame
Every new data frame is indicated by a start and stop
sequence, as illustrated in Figure 3.
Transition
to next bit
START
STOP
Start Sequence
Figure 3. Start and Stop Frame
A start frame is indicated by SDAT going LOW when SCLK is
HIGH. Every time a start signal is given, the next 8-bit data
must be the device address (7 bits) and a R/W bit (0 for Write),
followed by register address (8 bits) and register data (8 bits).
See Figure 3.
t1
t2
CLK
50%
50%
Stop Sequence
A stop frame is indicated by SDAT going HIGH when SCLK is
HIGH. A stop frame frees the bus for writing to another part on
the same bus or writing to another random register
address. See Figure 3.
Figure 4. Duty Cycle Definition; DC = t2/t1
t4
t3
80%
20%
Acknowledge Pulse
CLK
During Write mode, the CY2410-3 will respond with an ACK
pulse after every 8 bits. This is accomplished by pulling the
SDAT line LOW during the next clock cycle after the eighth bit
is shifted in.
Figure 5. Rise and Fall Time Definitions: ER = 0.6 x
VDD / t3, EF = 0.6 x VDD / t4
Device Address
The 7-bit device address is 1101001.
Register Address
The 8-bit address for the VCXO register is 00010011.
Register Data
The register data can be any value between 00H–FFH. As you
increase the value, the capacitance on the XIN and XOUT pins
will increase, thereby decreasing the xtal frequency.
Document #: 38-07317 Rev. *D
Page 3 of 7
CY2410
Absolute Maximum Conditions
Parameter
Description
Min.
–0.5
Max.
7.0
Unit
V
VDD
TS
Supply Voltage
Storage Temperature[3]
Junction Temperature
Digital Inputs
–65
125
°C
°C
V
TJ
–
125
VSS – 0.3
VSS – 0.3
2000
VDD + 0.3
VDD + 0.3
Digital Outputs referred to VDD
Electrostatic Discharge
V
V
Recommended Operating Conditions
Parameter
Description
Min.
3.135
0
Typ.
3.3
–
Max.
Unit
V
VDD
TA
Operating Voltage
3.465
70
Ambient Temperature
Max. Load Capacitance
Reference Frequency
°C
CLOAD
fREF
tPU
–
–
15
pF
–
13.5
–
–
MHz
ms
Power up time for VDD to reach minimum speci-
fied voltage
0.05
500
(power ramp must be monotonic)
DC Electrical Specifications
Parameter
IOH
Name
Output HIGH Current –1,3,5,7
Output LOW Current –1,3,5,7
Output HIGH Current –4,6
Output LOW Current –4,6
Input Capacitance
Description
Min.
12
12
6
Typ.
Max.
Unit
mA
mA
mA
mA
pF
VOH = VDD – 0.5, VDD = 3.3V
VOL = 0.5, VDD = 3.3V
24
24
18
18
–
–
–
–
–
7
–
–
–
IOL
IOH
IOL
CIN
IIZ
VOH = VDD – 0.5, VDD = 3.3V
VOL = 0.5, VDD = 3.3V
6
–
Input Leakage Current
VCXO pullability range:–1,–3,–4,–5,–6
VCXO pullability range:–7
VCXO input range
–
5
µA
f∆XO
+150
+115
0
–
ppm
ppm
V
–
VVCXO
IVDD
–
VDD
35
Supply Current
–
30
mA
AC Electrical Specifications (V = 3.3V)[4]
DD
Parameter[4]
Name
Description
Min.
45
Typ. Max. Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 4, 50% of VDD
50
55
–
%
EROR
Rising Edge Rate –1, –3, –5, –7 Output Clock Edge Rate, Measured from 20%
0.8
1.4
V/ns
to 80% of VDD, CLOAD = 15 pF See Figure 5.
EROF
EROR
EROF
Falling Edge Rate –1, –3, –5, –7 Output Clock Edge Rate, Measured from 80%
0.8
0.7
0.7
1.4
1.1
1.1
–
–
–
V/ns
V/ns
V/ns
to 20% of VDD, CLOAD = 15 pF See Figure 5.
Rising Edge Rate –4, –6
Falling Edge Rate –4, –6
Output Clock Edge Rate, Measured from 20%
to 80% of VDD, CLOAD = 15 pF See Figure 5.
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15 pF See Figure 5.
t9
t9
Clock Jitter –1, –3, –5, –7
Clock Jitter –4, –6
PLL Lock Time
Peak-to-peak period jitter
Peak-to-peak period jitter
–
–
–
140
150
–
–
–
3
ps
ps
t10
ms
Notes:
3. Rated for ten years.
4. Not 100% tested.
Document #: 38-07317 Rev. *D
Page 4 of 7
CY2410
Serial Programming Interface Timing Specifications
Parameter
Description
Min.
Max.
Unit
kHz
µS
µS
µS
ns
fSCL
Frequency of SCLK
400
Start mode time from SDAT LOW to SCLK LOW
SCLK LOW period
0.6
1.3
0.6
100
0
CLKLOW
CLKHIGH
tSU
SCLK HIGH period
Data transition to SCLK HIGH
Data hold (SCLK LOW to data transition)
Rise time of SCLK and SDAT
Fall time of SCLK and SDAT
tDH
ns
300
300
ns
ns
Stop mode time from SCLK HIGH to SDA HIGH
Stop mode to start mode
0.6
1.3
µs
µs
Test and Measurement Set-up
VDD
CLK out
0.1 µF
CLOAD
OUTPUTS
GND
Ordering Information
Operating
Range
Operating
Voltage
Ordering Code
Package Type
8-pin SOIC
Features
CY2410SC–1
Commercial 3.3V
Linear VCXO control curve
Linear VCXO control curve
Digital VCXO control
CY2410SC–1T 8-pin SOIC - Tape and Reel Commercial 3.3V
CY2410SC–3 8-pin SOIC Commercial 3.3V
CY2410SC–3T 8-pin SOIC - Tape and Reel Commercial 3.3V
CY2410SC–4 8-pin SOIC Commercial 3.3V
CY2410SC–4T 8-pin SOIC - Tape and Reel Commercial 3.3V
CY2410SC–5 8-pin SOIC Commercial 3.3V
Digital VCXO control
Lower drive strength (reduced EMI)
Lower drive strength (reduced EMI)
Matches nonlinear MK3727A VCXO control
curve
CY2410SC–5T 8-pin SOIC - Tape and Reel Commercial 3.3V
Matches nonlinear MK3727A VCXO control
curve
CY2410SC–6
CY2410SC–6T 8-pin SOIC - Tape and Reel Commercial 3.3V
CY2410SC–7 8-pin SOIC Commercial 3.3V
8-pin SOIC
Commercial 3.3V
Lower drive strength version of CY2410–5
Lower drive strength version of CY2410–5
Matches MK3727C nonlinear VCXO control
curve
CY2410SC–7T 8-pin SOIC - Tape and Reel Commercial 3.3V
Matches MK3727C nonlinear VCXO control
curve
Document #: 38-07317 Rev. *D
Page 5 of 7
CY2410
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07317 Rev. *D
Page 6 of 7
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2410
Document History Page
Document Title: CY2410 MPEG Clock Generator with VCXO
Document Number: 38-07317
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
111553
114937
121418
126905
02/12/02
09/24/02
12/06/02
06/17/03
CKN
CKN
CKN
RGL
New Data Sheet
*A
Added -6 to data sheet, Advance Information to Final
*B
Updated the Pullable Crystal Specifications table on page 2
*C
Added -7 part to data sheet
Added new parameter on the Pullable Crystal table
Power-up requirements added to the operating conditions
*D
131100
01/20/03
RGL
Added VCXO –7 pullability range in the DC Specs with min. value of ±115ppm
Document #: 38-07317 Rev. *D
Page 7 of 7
相关型号：
CY2410SXC-1T
Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8
CYPRESS
CY2410SXC-5
Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8
CYPRESS
CY2410SXC-5T
Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8
CYPRESS
©2020 ICPDF网 联系我们和版权申明