CY24204ZC-5T_技术文档

CY24204

MediaClock™

DTV, S

TB Clock Generator

Features

Benefits

• Integrated phase-locked loop (PLL)

• Low jitter, high-accuracy outputs

• VCXO with Analog Adjust

• 3.3V operation

• Internal PLL with up to 400-MHz internal operation

• Meets critical timing requirements in complex system

designs

• Large ±150-ppm range, better linearity

• Enables application compatibility

Part Number Outputs

Input Frequency

Output Frequency Range

CY24204-3

4

27-MHz Crystal Input

Two copies of 27-MHz reference clock output, two copies of

27/27.027/74.250/74.17582418 MHz (frequency selectable)

CY24204-4

4

27-MHz Crystal Input

Two copies of 27-MHz reference clock output, two copies of

27/27.027/74.250/74.17582418 MHz (frequency selectable,

Increased VCXO pull range)

CY24204-5

4

27-MHz Crystal Input

Two copies of 27-MHz reference clock output, two copies of

27/27.027/74.250/74.17582418 MHz (frequency selectable,

Increased output drive strength)

Pin Configurations

Block Diagram

16-pin TSSOP

XIN

Q

OSC.

Φ

VCO

OUTPUT

XOUT

1

2

3

4

5

6

7

8

16

15

14

13

12

XIN

VDD

AVDD

MULTIPLEXER

AND

CLK1

CLK2

OE

FS1

VSS

CLK1

VDDL

P

VCXO

DIVIDERS

PLL

VCXO

AVSS

VSSL

REFCLK1

11

10

REFCLK2

(-3,-4,-5)

REFCLK2

REFCLK1

FS0

CLK2

FS0

FS1

OE

9

VSSL

VSS

VDD

AVDD AVSS

VDDL

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07450 Rev. *C

Revised January 19, 2005

CY24204

Frequency Select Options

OE

FS1

FS0

CLK1/CLK2^[1]

REFCLK 1/2

Unit

MHz

0

off

27

0

1

off

0

1

0

off

0

1

off

1

0

27

1

0

1

0

1

27.027

74.250

74.17582418

Pin Description

Name

XIN

Pin Number

Description

1

2

Reference Crystal Input.

Voltage Supply.

V_DD

AV_DD

VCXO

AV_SS

3

4

5

Analog Voltage Supply.

Input Analog Control for VCXO.

Analog Ground.

V_SSL

6

CLK Ground.

REFCLK2

REFCLK1

CLK1

FS0

V_DDL

CLK2

V_SS

FS1

OE

7

8

9

10

11

12

13

14

15

16

Reference Clock Output.

27/27.027/74.250/74.17582418-MHz Clock Output (Frequency Selectable).

Frequency Select 0, Weak Internal Pull-up.

CLK Voltage Supply.

27/27.027/74.250/74.17582418-MHz Clock Output (Frequency Selectable).

Ground.

Frequency Select 1, Weak Internal Pull-up.

Output Enable, Weak Internal Pull-up.

Reference Crystal Output.

XOUT

Note:

1. “off” = output is driven HIGH.

Document #: 38-07450 Rev. *C

Page 2 of 6

CY24204

Storage Temperature (Non-Condensing).... –55°C to +125°C

Junction Temperature................................. –40°C to +125°C

Data Retention @ Tj=125°C..................................> 10 years

Package Power Dissipation...................................... 350 mW

ESD (Human Body Model) MIL-STD-883.................... 2000V

Absolute Maximum Conditions

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Supply Voltage (V_DD, AV_DDL, V_DDL)..................–0.5 to +7.0V

DC Input Voltage...................................... –0.5V to V_DD+ 0.5

Pullable Crystal Specifications

Parameter

Description

Comments

Min. Typ. Max. Unit

F_NOM

Nominal crystal frequency

Parallel resonance, fundamental mode, AT

–

27.0

–

MHz

cut

C_LNOM

R₁

R₃/R₁

Nominal load capacitance

Equivalent series resistance (ESR)

–

3

14

–

25

–

pF

Ω

Fundamental mode

Ratio of third overtone mode ESR to Ratio used because typical R₁values are

–

fundamental mode ESR

Crystal drive level

much less than the maximum spec

No external series resistor assumed

DL

–

300

–

180

14.4

0.5

–

2

–

mW

ppm

F_3SEPHI

F_3SEPLO

C₀

C₀/C₁

C₁

Third overtone separation from 3*F_NOMHigh side

Third overtone separation from 3*F_NOMLow side

Crystal shunt capacitance

Ratio of shunt to motional capacitance

Crystal motional capacitance

–150 ppm

7

250

21.6

pF

fF

18

Recommended Operating Conditions

Parameter

V_DD/AV_DDL/V_DDL

Description

Min.

3.135

0

–

0.05

Typ.

3.3

–

Max.

3.465

70

15

Unit

V

°C

pF

ms

Operating Voltage

T_A

Ambient Temperature

Max. Load Capacitance

C_LOAD

t_PU

Power-up time for all V_DDs to reach minimum specified

–

500

voltage (power ramps must be monotonic)

DC Electrical Specifications

Parameter^[2]

Name

Description

Min.

Typ.

Max.

Unit

I_OH1

Output High Current for V_OH= V_DD– 0.5, V_DD/V_DDL= 3.3V

12

24

–

mA

-3,-4,

I_OL1

Output Low Current for

-3,-4

V_OL= 0.5, V_DD/V_DDL= 3.3V

12

24

–

mA

I_OH2

I_OL2

V_IH

Output High Current for -5 V_OH= V_DD– 0.5, V_DD/V_DDL= 3.3V

Output Low Current for -5 V_OL= 0.5, V_DD/V_DDL= 3.3V

18

0.7

–

±150

–

0

–

26

–

±200

–

0.3

25

20

7

–

V_DD

150

mA

V_DD

mA

pF

ppm

V

Input High Voltage

Input Low Voltage

Supply Current

CMOS levels, 70% of V_DD

CMOS levels, 30% of V_DD

AV_DD/V_DDCurrent

V_IL

I_VDD

I_VDDL

C_IN

f_∆XO

V_VCXO

Supply Current

V_DDLCurrent (V_DDL= 3.47V)

Input Capacitance

V_CXOpullability range

V_CXOinput range

Nominal pullability for -1,-2,-3,-5,-6

Extended pullability for -4

R_UP

Pull-up resistor on inputs V_DD= 3.14 to 3.47V, measured at V_IN= 0V

100

kΩ

Note:

2. Not 100% tested.

Document #: 38-07450 Rev. *C

Page 3 of 6

CY24204

AC Electrical Specifications

Parameter^[2]

DC

Name

Output Duty Cycle

Description

Min.

Typ.

50

Max.

55

Unit

%

Duty Cycle is defined in Figure 1; t1/t2, 50% of V_DD45

ER₁

Rising Edge Rate for -3,-4 Output Clock Edge Rate, Measured from 20% to

0.8

1.0

1.4

–

V/ns

80% of V_DD, C_LOAD= 15 pF See Figure 2.

EF₁

ER₂

EF₂

Falling Edge Rate for

-3,-4

Output Clock Edge Rate, Measured from 80% to

1.4

1.8

–

V/ns

20% of V_DD, C_LOAD= 15 pF See Figure 2.

Rising Edge Rate for -5 Output Clock Edge Rate, Measured from 20% to

80% of V_DD, C_LOAD= 15 pF See Figure 2.

Falling Edge Rate for -5 Output Clock Edge Rate, Measured from 80% to

20% of V_DD, C_LOAD= 15 pF See Figure 2.

t₉

t₁₀

Clock Jitter

PLL Lock Time

CLK1, CLK2 Peak-Peak period jitter

–

120

–

3

ps

ms

Test and Measurement Set-up

V_DDs

Outputs

C_LOAD

0.1 F

µ

DUT

GND

Voltage and Timing Definitions

t₁

t₂

V_DD

50% of V_DD

0V

Clock

Output

Figure 1. Duty Cycle Definition

t₄

t₃

V _DD

80% of V_DD

20% of V_DD

0V

Clock

Output

Figure 2. ER = (0.6 x V_DD) /t3, EF = (0.6 x V_DD) /t4

Document #: 38-07450 Rev. *C

Page 4 of 6

CY24204

Ordering Information

Ordering Code

Package Name

Package Type

Operating Range

Operating Voltage

Standard

CY24204ZC-3

CY24204ZC-3T

CY24204ZC-4

CY24204ZC-4T

CY24204ZC-5

CY24204ZC-5T

Lead-free

Z16

16-Pin TSSOP

Commercial

3.3V

CY24204ZXC-3

CY24204ZXC-3T

CY24204ZXC-4

CY24204ZXC-4T

CY24204ZXC-5

CY24204ZXC-5T

Z16

16-Pin TSSOP

Commercial

3.3V

Package Drawing and Dimensions

16-lead TSSOP 4.40 MM Body Z16.173

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN.

1

MAX.

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.05gms

6.25[0.246]

6.50[0.256]

4.30[0.169]

4.50[0.177]

16

0.65[0.025]

BSC.

0.25[0.010]

BSC

0.19[0.007]

0.30[0.012]

1.10[0.043] MAX.

GAUGE

PLANE

0°-8°

0.076[0.003]

0.50[0.020]

0.70[0.027]

0.05[0.002]

0.15[0.006]

0.85[0.033]

0.95[0.037]

0.09[[0.003]

0.20[0.008]

SEATING

PLANE

4.90[0.193]

5.10[0.200]

51-85091-*A

MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document

may be the trademarks of their respective holders.

Document #: 38-07450 Rev. *C

Page 5 of 6

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY24204

Document History Page

Document Title: CY24204 MediaClock™ DTV, STB Clock Generator

Document Number: 38-07450

Orig. of

REV.

**

*A

*B

*C

ECN NO. Issue Date Change

Description of Change

123842

128775

214080

310573

04/10/03

09/0803

See ECN

CKN

IJA

RGL

New Data Sheet

Added -4 and -5 parts

Added -6 part

Removed -1,-2 and -6 parts

Added Lead-free devices for -3, -4, and -5 parts

Document #: 38-07450 Rev. *C

Page 6 of 6


型号：	CY24204ZC-5T
厂家：	CYPRESS
描述：	MediaClock⑩ DTV, STB Clock Generator MediaClock ™ DTV ， STB时钟发生器晶体时钟发生器微控制器和处理器外围集成电路电视光电二极管
文件：	总6页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY24204ZC-5T [CYPRESS]

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