CY25000SC-W [CYPRESS]
Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8;
| 型号： | CY25000SC-W |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总10页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25000
Programmable Spread Spectrum
Clock Generator for EMI Reduction
Benefits
Features
• Wide operating output (SSCLK) frequency range
— 3–200 MHz
• Services most PC peripherals, networking, and consumer
applications.
• Provides wide range of spread percentages for maximum
EMI reduction, to meet regulatory agency Electro Magnetic
Compliance (EMC) requirements. Reduces development
and manufacturing costs and time-to-market.
• Programmable spread spectrum with nominal 30-kHz
modulation frequency
— Center spread: ±0.25% to ±2.5%
— Down spread: –0.5% to –5.0%
• Input frequency range
• Eliminates the need for expensive and difficult to use higher
order crystals.
• Internal PLL to generate up to 200-MHz output. Able to
generate custom frequencies from an external crystal or a
driven source.
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
• Integrated phase-locked loop (PLL)
• Programmable crystal load capacitor tuning array
• Low cycle-to-cycle Jitter
• 3.3V operation
• Spread spectrum On/Off function
• Power-down or Output Enable function
• Enables fine-tuning of output clock frequency by adjusting
C
Load of the crystal. Eliminates the need for external CLoad
capacitors.
• Suitable for most PC, consumer, and networking applica-
tions
• Application compatibility in standard and low-power
systems.
• Provides ability to enable or disable spread spectrum with
an external pin.
• Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
XIN/CLKIN
XOUT
1
8
OSC.
CXIN
PLL
Pin Configuration
with
CXOUT
CY25000
Modulation Control
8-pin SOIC
Output
Dividers
6
REFCLK
SSCLK
Programmable Configuration
XOUT
1
2
3
4
XIN/CLKIN
and
8
7
6
5
MUX
SSON
REFCLK
VDD
PD#/OE
VSS
5
SSCLK
PD#/OE
SSON
3
7
2
4
VDD VSS
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07424 Rev. *B
Revised September 26, 2003
CY25000
Pin Descriptions
Pin
1
2
Name
XIN/CLKIN
VDD
Description
Crystal input or reference clock input.
3.3V voltage supply.
Power-down pin. Active LOW. If PD# = 0, SSCLK and REFCLK are three-stated.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled.
User has the option of choosing either PD# or OE function.
3
PD#/OE
4
5
6
7
8
VSS
SSCLK
REFCLK
SSON
GND.
Spread spectrum clock output.
Buffered reference output.
Spread spectrum control. 1 = Spread on. 0 = Spread off.
Crystal output. Leave this pin floating if external clock is used.
XOUT
The spread % is factory programmed to either center spread
or down spread with various spread percentages. The range
General Description
The CY25000 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing Electro Magnetic Inter-
ference (EMI) found in today’s high-speed digital electronic
systems.
The device uses a Cypress-proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency requirements (EMC) and improve time to
market without degrading system performance.
for center spread is from ±0.25% to ±2.50%. The range for
down spread is from –0.5% to –5.0%. Contact the factory for
smaller or larger spread % amounts if required.
The input to the CY25000 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz,
and for clock signals is 8–166 MHz.
The CY25000 has two clock outputs, REFCLK and SSCLK.
The non-spread spectrum REFCLK output has the same
frequency as the input of the CY25000. The frequency
modulated SSCLK output can be programmed from 3–200
MHz.
The CY25000 products are available in an 8-pin SOIC
(150-mil) package with a commercial operating temperature
range of 0 to 70°C.
The CY25000 uses a factory-programmable configuration
memory array to synthesize output frequency, spread %,
crystal load capacitor, reference clock on/off and PD#/OE
options.
Document #: 38-07424 Rev. *B
Page 2 of 10
CY25000
Junction Temperature................................ –40°C to +125°C
Data Retention @ Tj=125°C................................. > 10 Years
Package Power Dissipation...................................... 350 mW
Absolute Maximum Rating
Supply Voltage (VDD)........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-Condensing)....–55°C to +125°C
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
Parameter
Description
Min.
3.13
0
Typ.
3.30
Max.
3.45
70
Unit
V
°C
VDD
TA
Supply Voltage
Ambient Temperature
CLOAD
Fref
Max. Load Capacitance @ pin 5 and pin 6
15
30
pF
MHz
External Reference Crystal
8
(Fundamental tuned crystals only)
External Reference Clock
SSCLK output frequency, CLOAD = 15 pF
REFCLK output frequency, CLOAD = 15 pF
8
3
8
166
200
166
500
MHz
MHz
MHz
ms
FSSCLK
FREFCLK
tPU
Power-up time for all VDDs to reach minimum
0.05
specified voltage (power ramps must be monotonic)
DC Electrical Characteristics
Parameter
IOH
IOL
VIH
VIL
IIH
Description
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Condition
Min.
10
10
Typ.
14
14
Max.
Unit
VOH = VDD – 0.5, VDD = 3.3V (source)
VOL = 0.5, VDD= 3.3V (sink)
CMOS levels, 70% of VDD
mA
mA
V
V
µA
0.7VDD
CMOS levels, 30% of VDD
0.3VDD
10
Input High Current, PD#/OE Vin = VDD
and SSON pins
IIL
Input Low Current, PD#/OE Vin = VSS
and SSON pins
10
10
µA
IOZ
CXIN/CXOUT
Output Leakage Current
Three-state output, PD#/OE = 0
–10
µA
pF
pF
pF
[1, 2]
ProgrammableCapacitance Capacitance at minimum setting
12
60
5
at pin 1 and pin 8
Capacitance at maximum setting
[1]
CIN
Input Capacitance at pin 3 Input pins excluding XIN and XOUT
7
and pin 7
IVDD
Supply Current
Stand by current
VDD = 3.45V, Fin = 30 MHz,
25
15
35
mA
REFCLK = 30 MHz, SSCLK = 66 MHz,
CLOAD = 15 pF, PD#/OE = SSON = VDD
IDDS
VDD = 3.45V, Device powered down with
30
µA
PD#/OE = 0V
AC Electrical Characteristics[1]
Parameter
DC
Description
Output Duty Cycle
Output Duty Cycle
Condition
SSCLK, Measured at VDD/2
Min.
45
40
Typ.
50
50
Max.
55
60
Unit
%
%
REFCLK, Measured at VDD/2
Duty Cycle of CLKIN = 50%.
SR1
Rising Edge Slew Rate
Falling Edge Slew Rate
SSCLK from 3 to 100 MHz; REFCLK from
10 to 100 MHz. 20%–80% of VDD
0.7
0.7
1.1
1.1
1.5
1.5
V/ns
V/ns
SR2
SSCLK from 3 to 100 MHz; REFCLK from
10 to 100 MHz. 80%–20% of VDD
Notes:
1. Guaranteed by characterization, not 100% tested.
2. Contact factory for desired crystal load programming.
Document #: 38-07424 Rev. *B
Page 3 of 10
CY25000
AC Electrical Characteristics[1]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
SR3
Rising Edge Slew Rate
SSCLK from 100 to 200 MHz; REFCLK
1.2
1.6
2.0
V/ns
from 100 to 166 MHz 20%–80% of VDD
SR4
tj1
Falling Edge Slew Rate
SSCLK from 100 to 200 MHz; REFCLK
from 100 to 166 MHz 80%–20% of VDD
1.2
1.6
2.0
V/ns
Peak Cycle-to-Cycle Jitter. SSCLK = 200 MHz. Spread on
100
150
200
100
200
300
400
200
ps
ps
ps
ps
SSCLK pin
SSCLK = 66 MHz. Spread on
SSCLK = 14.3 MHz. Spread on
tj2
Peak Cycle-to-Cycle Jitter, REFCLK output only
REFCLK
tSTP
TOE1
TOE2
tPU1
tPU2
Power-down Time
(pin3 = PD#)
Time from falling edge on PD# to stopped
outputs (Asynchronous)
150
150
150
3
300
300
300
5
ns
ns
Output Disable Time
Time from falling edge on OE to stopped
(pin3 = OE)
outputs (Asynchronous)
Output Enable Time
(pin3 = OE)
Time from rising edge on OE to outputs at
a valid frequency (Asynchronous)
ns
Power-up Time,
Time from rising edge on PD# to outputs
ms
ms
Crystal is used
at valid frequency (Asynchronous)
Power-up Time,
Time from rising edge on PD# to outputs
at valid frequency (Asynchronous)
2
3
Reference clock is used
Table 1.
Pin
Input
CXIN and
Output
Spread
Percent
Reference
Output
Power-down or
Output Enable
Frequency
Modulation
Function
Frequency
CXOUT
Frequency
Pin Name
XIN and XOUT
XIN and
SSCLK
SSCLK
REFOUT
PD#/OE
SSCLK
XOUT
Pin#
Units
1 and 8
MHz
1 and 8
pF
5
MHz
5
%
6
3
5
kHz
30
On or Off
Select PD# or OE
PROGRAM
ENTER DATA ENTER DATA ENTER DATA ENTER ENTER DATA ENTER DATA
VALUE
DATA
CXIN = CXOUT = 2CL - CP
Programming Description
The customers planning to use the CY25000 need to provide
the programming information described as “ENTER DATA” in
Table 1 and should contact local Cypress Sales.
Where CL is the crystal load capacitor as specified by the
crystal manufacturer and CP is the parasitic PCB capacitance.
For example, if a fundamental 16-MHz crystal with CL of 16 pF
is used and CP is 2 pF, CXIN and CXOUT can be calculated as:
Additional information on the CY25000 can be obtained from
CXIN = CXOUT = (2 x 16) – 2 = 30 pF.
the Cypress web site at www.cypress.com.
If using a driven reference, set CXIN and CXOUT to the
Product Functions
minimum value 12 pF.
Input Frequency (XIN, pin 1 and XOUT pin 8)
Output Frequency, SSCLK Output (SSCLK, pin 5)
,
The input to the CY25000 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock
signal is 8 to 166 MHz.
The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON digital control input (SSON = LOW, no
modulation). If modulation is stopped, the clock frequency is
the nominal value of the synthesized frequency without
modulation (spread % = 0). The range of synthesized clock is
from 3–200 MHz.
CXIN and CXOUT (pin 1 and pin 8)
The load capacitors at pin 1 (CXIN) and pin 8 (CXOUT) can be
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
Spread Percentage (SSCLK, pin 5)
The SSCLK frequency can be programmed at any percentage
value from ±0.25% to ±2.5% for Center Spread and from
–0.5% to –5.0% Down Spread.
The required values of CXIN and CXOUT can be calculated
using the following formula:
Document #: 38-07424 Rev. *B
Page 4 of 10
CY25000
Reference Output (REFOUT, pin 6)
Frequency Modulation
The reference clock output has the same frequency and the
same phase as the input clock. This output can be
programmed to be enabled (clock on) or disabled (High-Z,
clock off). If this output is not needed, it is recommended that
users request the disabled (High-Z, Clock Off) option.
The frequency modulation is programmed at 30 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher modulation frequency is required.
Power-down or Output Enable (PD# or OE, pin 3):
Users can select either PD# or OE function which are also
factory programmable.
Application Circuit[3, 4, 5]
Crystal
Power
XIN
XOUT
8
1
SSON
VDD
7
2
3
VDD
0.1µF
PD#/OE
VSS
REFCLK
6
VDD
SSCLK
5
4
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B
)
t
1B
t
1A
OUTPUT
Output Rise/Fall Time (SSCLK and REFCLK)
OUTPUT
VDD
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x V )/SR1 (or SR3)
DD
Output Fall time (Tf) = (0.6 x V )/SR2 (or SR4)
DD
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Power-down Timing and Power-up Timing
VDD
VIH
POWER-
DOWN
VIL
tPU
0V
High Impedance
CLKOUT
(Asynchronous
)
tSTP
Notes:
3. Since the load capacitors (C
and C
) are provided by the CY25000, no external capacitors are needed on the XIN and XOUT pins to match the crystal load
XOUT
XIN
capacitor (C ). Only a single 0.1-µF bypass capacitor is required on the V pin.
L
DD
4. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected).
5. If SSON (pin 7) is LOW (V ), the frequency modulation will be stopped on SSCLK pin (pin 5).
SS
Document #: 38-07424 Rev. *B
Page 5 of 10
CY25000
Switching Waveforms (continued)
Output Enable/Disable Timing
VDD
VIH
OUTPUT
TOE2
ENABLE
VIL
0V
High Impedance
CLKOUT
(Asynchronous
)
TOE1
Informational Graphs
172.5
171.5
170.5
169.5
168.5
167.5
166.5
165.5
164.5
163.5
162.5
169.5
169
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= +/-1%
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= -4%
168.5
168
167.5
167
166.5
Fnominal
166
165.5
Fnominal
165
164.5
164
163.5
161.5
160.5
159.5
163
162.5
0
20
40
60
80
100 120 140
Time (us)
160 180 200
0
20
40
60
80
100
120
140 160 180
200
Time (us)
68.5
68
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= -4%
67.5
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= +/-1%
67
66.5
66
67.5
67
66.5
Fnominal
66
Fnominal
65.5
65
65.5
64.5
64
63.5
65
64.5
0
20
40
60
80
100
120
140 160
180
200
0
20
40
60 80
100 120 140 160 180 200
Time (us)
Time (us)
Document #: 38-07424 Rev. *B
Page 6 of 10
CY25000
Informational Graphs (continued)
Duty Cycle vs. REFCLK
IDDvs. SSCLK
Temperature=25C, VDD=3.3V, CLOAD=15pF
(VDD=3.0V, Temperature=25C, CLOAD = 15pF)
60
58
56
54
52
50
48
46
44
42
40
70
60
50
40
30
20
10
0
0
50
100
150
200
250
SSCLK (M Hz)
REFCLK=SSCLK
REFCLK=30MHz
0
50
100
150
200
REFCLK (MHz)
Measured Spread% vs. VDD over Temperature
(Target Spread = 0.5%, Fout=100MHz, CLOAD=15pF)
Measured Spread% vs. VDD over
Temperature
(Target Spread = 5.0%, Fout=100MHz, CLOAD=15pF)
0.60%
0.55%
0.50%
0.45%
0.40%
6.00%
5.50%
5.00%
4.50%
4.00%
-40C
25C
85C
-40C
25C
85C
2.7
3
3.3
3.6
3.9
2.7
3
3.3
3.6
3.9
VDD (V)
VDD (V)
SSCLK Attenduation vs. VDD over Temperature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=0.5%, CLOAD=15pF)
SSCLK Attenduation vs. VDD over Temperature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=5.0%, CLOAD=15pF)
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-40C
25C
85C
-40C
25C
85C
-10
2.7
3
3.3
3.6
3.9
2.7
3
3.3
3.6
3.9
VDD (V)
VDD (V)
Document #: 38-07424 Rev. *B
Page 7 of 10
CY25000
Informational Graphs (continued)
Max Cycle-Cycle Jitter on SSCLK vs.
SSCLK Attenuation vs. Spread%
(Temp=25C, VDD=3.3V, SSCLK=100MHz, Measured
on Cypress Characterization board w ith
CLOAD=15pF)
Temperature
(SSCLK=100MHz, VDD=3.3V, CLOAD=15pF)
200
175
150
125
100
75
0
-2
-4
-6
-8
-10
-12
-14
-16
50
25
0
-60
-40
-20
0
20
40
60
80
100
0.0% 0.5%
1.0% 1.5% 2.0%
2.5% 3.0% 3.5% 4.0%
4.5% 5.0%
Temp (deg C)
Spread %
Request Form” at www.cypress.com) must be completed.
Once the request has been processed, you will receive a new
part number, samples and data sheet with the programmed
values. This part number will be used for additional sample
requests and production orders.
Custom Configuration Request Procedure
The CY25000 is a memory programmable device that is
configured in the factory. All requests must be submitted to the
local Cypress Field Application Engineer (FAE) or sales repre-
sentative. A sample request form (refer to “CY25000 Sample
Ordering Information
Part Number[6]
CY25XXXSC-W
CY25XXXSC-WT
Package Type
8-pin Small Outline Integrated Circuit (SOIC)
8-pin Small Outline Integrated Circuit (SOIC)–Tape and Reel
Product Flow
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Document #: 38-07424 Rev. *B
Page 8 of 10
CY25000
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
51-85066-*C
0.0138[0.350]
0.0192[0.487]
Note:
6. “XXX” denotes the assigned product number. “W” denotes the different programmed spread % values. The user can request different spread % values.
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07424 Rev. *B
Page 9 of 10
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY25000
Document History Page
Document Title: CY25000 Programmable Spread Spectrum Clock Generator for EMI Reduction
Document Number: 38-07424
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
**
*A
*B
115076
121901
129855
06/20/02
12/14/02
10/01/03
CKN
RBI
RGL
New Data Sheet
Power-up requirements added to Operating Conditions Information
Removed “PRELIMINARY”
Changed IOH and IOL min. from 12 mA to 10 mA and typical from 24 mA to 14 mA
Document #: 38-07424 Rev. *B
Page 10 of 10
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