CY25100SXIXXX [CYPRESS]
Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8;
| 型号： | CY25100SXIXXX |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8 时钟发生器 |
| 文件： | 总11页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25100
Field- and Factory-Programmable Spread Spectrum
Clock Generator for EMI Reduction
Benefits
Features
• Wide operating output (SSCLK) frequency range
— 3–200 MHz
• Services most PC peripherals, networking, and consumer
applications.
• Provides wide range of spread percentages for maximum
electromagnetic interference (EMI) reduction, to meet
regulatory agency electromagnetic compliance (EMC)
requirements. Reduces development and manufacturing
costs and time-to-market.
• Programmable spread spectrum with nominal 31.5-kHz
modulation frequency
— Center spread: ±0.25% to ±2.5%
— Down spread: –0.5% to –5.0%
• Input frequency range
• Eliminates the need for expensive and difficult to use
higher-order crystals.
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
• Integrated phase-locked loop (PLL)
• Field-programmable
— CY25100SCF and CY25100SIF, 8-pin SOIC
— CY25100ZCF and CY25100ZIF, 8-pin TSSOP
• Programmable crystal load capacitor tuning array
• Low cycle-to-cycle jitter
• Internal PLL to generate up to 200-MHz output. Able to
generate custom frequencies from an external crystal or a
driven source.
• In-house programming of samples and prototype quantities
is available using the CY3672 programming kit and
CY3690 (TSSOP) or CY3691 (SOIC) socket adapter.
Production quantities are available through Cypress’s
value-added distribution partners or by using third-party
programmers from BP Microsystems, HiLo Systems, and
others.
• 3.3V operation
• Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal. Eliminates the need for external CLoad
capacitors.
• Commercial and Industrial operation
• Spread Spectrum On/Off function
• Power-down or Output Enable function
• Suitable for most PC, consumer, and networking applica-
tions
• Application compatibility in standard and low-power
systems
• Provides ability to enable or disable spread spectrum with
an external pin.
• Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
Pin Configuration
CY25100
8-pin SOIC/TSSOP
RFB
PLL
with
3
MODULATION
CONTROL
1
2
VDD
8
SSON#
SSCLK
XIN
CXIN
6
7
XOUT
OUTPUT
DIVIDERS
and
PROGRAMMABLE
CONFIGURATION
2
REFCLK
XOUT
3
XIN/CLKIN
PD#/OE
REFCLK 6
VSS 5
MUX
CXOUT
7
4
4
SSCLK
PD# or OE
8
SSON#
1
5
VDD
VSS
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07499 Rev. *D
Revised March 24, 2004
CY25100
Pin Description
Pin
Name
Description
1
2
3
4
VDD
XOUT
XIN/CLKIN
PD#/OE
3.3V power supply.
Crystal output. Leave this pin floating if external clock is used.
Crystal input or reference clock input.
Power-down pin: Active LOW. If PD# = 0, the PLL and Xtal are powered down,
and outputs are weakly pulled low.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled.
User has the option of choosing either PD# or OE function.
5
6
7
8
VSS
Power supply ground.
Buffered reference output.
Spread spectrum clock output.
Spread spectrum control. 0 = Spread on. 1 = Spread off.
REFCLK
SSCLK
SSON#
The spread% is programmed to either center spread or down
spread with various spread percentages. The range for center
General Description
The CY25100 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing EMI found in today’s
high-speed digital electronic systems.
spread is from ±0.25% to ±2.50%. The range for down spread
is from –0.5% to –5.0%. Contact the factory for smaller or
larger spread % amounts if required.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency (EMC) requirements and improve
time-to-market without degrading system performance.
The CY25100 uses a factory/field-programmable configu-
ration memory array to synthesize output frequency, spread%,
crystal load capacitor, reference clock output on/off, spread
spectrum on/off function and PD#/OE options.
The input to the CY25100 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz,
and for clock signals is 8–166 MHz.
The CY25100 has two clock outputs, REFCLK and SSCLK.
The non-spread spectrum REFCLK output has the same
frequency as the input of the CY25100. The frequency
modulated SSCLK output can be programmed from 3–200
MHz.
The CY25100 products are available in an 8-pin SOIC and
TSSOP packages with commercial and industrial operating
temperature ranges.
Table 1.
Total Xtal
Spread Percent
(0.5% – 5%,
Pin
Input
Load
Output
Reference Power-down or Frequency
Function
Frequency Capacitance Frequency 0.25% Intervals)
Output
Output Enable Modulation
Pin Name
XIN and
XIN and XOUT
SSCLK
SSCLK
REFOUT
PD#/OE
SSCLK
XOUT
Pin#
Unit
3 and 2
MHz
3 and 2
pF
7
MHz
7
%
6
4
7
kHz
31.5
On or Off Select PD# or OE
Program ENTER DATA ENTER DATA
ENTER
ENTER DATA
ENTER
ENTER DATA
Value
DATA
DATA
Document #: 38-07499 Rev. *D
Page 2 of 11
CY25100
Programming Description
Product Functions
Field-Programmable CY25100
Input Frequency (XIN, pin 3 and XOUT pin 2)
,
The CY25100 is programmed at the package level, i.e., in a
programmer socket. The CY25100 is flash-technology based,
so the parts can be reprogrammed up to 100 times. This allows
for fast and easy design changes and product updates, and
eliminates any issues with old and out-of-date inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer with CY3690 (TSSOP) or
CY3691 (SOIC) socket adapter.
The input to the CY25100 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock
signals is 8 to 166 MHz.
CXIN and CXOUT (pin 3 and pin 2)
The load capacitors at Pin 1 (CXIN) and Pin 8 (CXOUT) can be
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
CyberClocks Online Software
The required values of CXIN and CXOUT can be calculated
CyberClocks Online Software is a web-based software appli-
cation that allows the user to custom-configure the CY25100.
All the parameters in Table 1 given as “Enter Data” can be
programmed into the CY25100. CyberClocks Online outputs
an industry-standard JEDEC file used for programming the
CY25100. CyberClocksOnline is available at www.cyberclock-
sonline.com website through user registration. To register,
fillout the registration form and make sure to check the
“non-standard devices” box. For more information on the
registration process refer to CY3672 datasheet
For information regarding Spread Spectrum software
programming solutions, please contact your local Cypress
Sales or Field Application Engineer (FAE), representative for
details.
using the following formula:
CXIN = CXOUT = 2CL – CP
where CL is the crystal load capacitor as specified by the
crystal manufacturer and CP is the parasitic PCB capacitance.
For example, if a fundamental 16-MHz crystal with CL of 16-pF
is used and CP is 2 pF, CXIN and CXOUT can be calculated as:
CXIN = CXOUT = (2 x 16) – 2 = 30 pF.
If using a driven reference, set CXIN and CXOUT to the
minimum value 12 pF.
Output Frequency, SSCLK Output (SSCLK, pin 7)
The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON# digital control input (SSON# = HIGH, no
modulation). If modulation is stopped, the clock frequency is
the nominal value of the synthesized frequency without
modulation (spread % = 0). The range of synthesized clock is
from 3–200 MHz.
CY3672FTGProgrammingKitandCY3690/CY3691Socket
Adapter
The Cypress CY3672 FTG programmer and CY3690/CY3691
Socket Adapter are needed to program the CY25100. The
CY3690 enables user to program CY25100ZCF and
CY25100ZIF (TSSOP) and CY3691 gives the user the ability
to program CY25100SCF and CY25100SIF (SOIC). Each
socket adapter comes with small prototype quantities of
CY25100. The CY3690/CY3691 is a separate orderable item,
so the existing users of the CY3672 FTG development kit or
CY3672-PRG programmer need to order only the socket
adapters to program the CY25100.
Spread Percentage (SSCLK, pin 7)
The SSCLK spread can be programmed at any percentage
value from ±0.25% to ±2.5% for Center Spread and from
–0.5% to –5.0% Down Spread.
Reference Output (REFOUT, pin 6)
The reference clock output has the same frequency and the
same phase as the input clock. This output can be
programmed to be enabled (clock on) or disabled (High-Z,
clock off). If this output is not needed, it is recommended that
users request the disabled (High-Z, Clock Off) option.
Factory-Programmable CY25100
Factory programming is available for volume manufacturing by
Cypress. All requests must be submitted to the local Cypress
Field Application Engineer (FAE) or sales representative. A
sample request form (refer to “CY25100 Sample Request
Form” at www.cypress.com) must be completed. Once the
request has been processed, you will receive a new part
number, samples, and data sheet with the programmed
values. This part number will be used for additional sample
requests and production orders.
Frequency Modulation
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher-modulation frequency is required.
Power-down or Output Enable (PD# or OE, pin 4):
The part can be programmed to include either PD# or OE
function. PD# function powers down the oscillator and PLL.
The OE function disables the outputs.
Additional information on the CY25100 can be obtained from
the Cypress web site at www.cypress.com.
Document #: 38-07499 Rev. *D
Page 3 of 11
CY25100
Junction Temperature................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Absolute Maximum Rating
Supply Voltage (VDD)........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-condensing).....–55°C to +125°C
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter
FNOM
CLNOM
R1
R3/R1
Description
Nominal Crystal Frequency
Nominal Load Capacitance
Comments
Parallel resonance, fundamental mode, AT cut
Internal load caps
Min. Typ. Max. Unit
8
6
–
3
–
–
–
–
30 MHz
30
25
–
pF
Ω
–
Equivalent Series Resistance (ESR) Fundamental mode
Ratio of Third Overtone Mode ESR to Ratio used because typical R1 values are much
Fundamental Mode ESR
Crystal Drive Level
less than the maximum spec
No external series resistor assumed
DL
–
0.5
2
mW
Operating Conditions
Parameter
Description
Min.
3.13
0
–40
–
Typ.
3.30
–
–
–
Max.
3.45
70
85
15
30
Unit
V
°C
°C
pF
MHz
VDD
TA
Supply Voltage
Ambient Commercial Temperature
Ambient Industrial Temperature
Max. Load Capacitance @ pin 6 and pin 7
CLOAD
Fref
External Reference Crystal
8
–
(Fundamental tuned crystals only)
External Reference Clock
8
3
8
30.0
0.05
–
–
–
31.5
–
166
200
166
33.0
500
MHz
MHz
MHz
kHz
ms
FSSCLK
FREFCLK
FMOD
SSCLK output frequency, CLOAD = 15 pF
REFCLK output frequency, CLOAD = 15 pF
Spread Spectrum Modulation Frequency
TPU
Power-up time for all VDDs to reach minimum spec-
ified voltage (power ramp must be monotonic)
DC Electrical Characteristics
Parameter
Description
Condition
= V – 0.5, V = 3.3V (source)
Min. Typ. Max. Unit
I
I
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
V
V
10
10
12
12
–
mA
mA
V
OH
OH
DD
DD
= 0.5, V = 3.3V (sink)
OL
OL
DD
V
V
CMOS levels, 70% of V
CMOS levels, 30% of V
0.7V
V
DD
IH
IL
DD
DD
DD
–
–
–
–
0.3V
10
V
µA
DD
I
I
I
Input High Current, PD#/OE and
V
= V
IH
in
DD
SSON# pins
Input Low Current, PD#/OE and
SSON# pins
Output Leakage Current
V
= V
–
–
10
µA
IL
in
SS
Three-state output, PD#/OE = 0
–10
–
–
10
–
–
µA
pF
pF
pF
OZ
[1]
C
or C
ProgrammableCapacitanceatpin Capacitance at minimum setting
12
60
5
XIN
XOUT
2 and pin 3
Capacitance at maximum setting
[1]
C
Input Capacitance at pin 4 and pin Input pins excluding XIN and XOUT
–
7
IN
8
I
I
Supply Current
Standby current
V
= 3.45V, Fin = 30 MHz,
–
–
25
15
35
30
mA
VDD
DD
REFCLK = 30 MHz, SSCLK = 66 MHz,
= 15 pF, PD#/OE = SSON# = V
C
LOAD
DD
V
= 3.45V, Device powered down with
DD
µA
DDS
PD# = 0V (driven reference pulled down)
Notes:
1. Guaranteed by characterization, not 100% tested.
Document #: 38-07499 Rev. *D
Page 4 of 11
CY25100
AC Electrical Characteristics[1]
Parameter
DC
Description
Output Duty Cycle
Output Duty Cycle
Condition
SSCLK, Measured at VDD/2
Min. Typ.
Max.
55
60
Unit
%
%
45
50
REFCLK, Measured at VDD/2
40
50
Duty Cycle of CLKIN = 50% at input bias
SR1
SR2
SR3
SR4
Rising Edge Slew Rate
Falling Edge Slew Rate
Rising Edge Slew Rate
Falling Edge Slew Rate
SSCLK from 3 to 100 MHz; REFCLK from 3 to 100
0.7
0.7
1.2
1.2
1.1
1.1
1.6
1.6
3.6
3.6
4.0
4.0
V/ns
V/ns
V/ns
V/ns
MHz. 20%–80% of VDD
SSCLK from 3 to 100 MHz; REFCLK from 3 to 100
MHz. 80%–20% of VDD
SSCLK from 100 to 200 MHz; REFCLK from 100 to
166 MHz 20%–80% of VDD
SSCLK from 100 to 200 MHz; REFCLK from 100 to
166 MHz 80%–20% of VDD
[2]
TCCJ1
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK off
CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK off
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK off
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK on
CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK on
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK on
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK on
CLKIN = SSCLK = 66 MHz, 2% spread REFCLK on
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK on
–
–
–
–
–
–
–
–
–
–
90
120
130
170
130
140
260
100
130
180
350
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
100
130
100
105
200
80
100
135
150
[2]
TCCJ2
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
[2]
TCCJ3
Cycle-to-Cycle Jitter
REFCLK (Pin 6)
tSTP
TOE1
TOE2
tPU1
tPU2
Power-down Time
(pin 4 = PD#)
Time from falling edge on PD# to stopped outputs
(Asynchronous)
Output Disable Time
Time from falling edge on OE to stopped outputs
(Asynchronous)
–
–
–
–
150
150
3.5
2
350
350
5
ns
ns
(pin 4 = OE)
Output Enable Time
(pin 4 = OE)
Time from rising edge on OE to outputs at a valid fre-
quency (Asynchronous)
Power-up Time,
Time from rising edge on PD# to outputs at valid fre-
quency (Asynchronous)
Time from rising edge on PD# to outputs at valid fre-
quency (Asynchronous), reference clock at correct
frequency
ms
ms
Crystal is used
Power-up Time,
3
Reference clock is used
Application Circuit[3, 4, 5]
P o w e r
8
7
6
5
1
2
3
4
V D D
S S O N #
S S C L K
0 .1 u F
X O U T
C Y 2 5 1 0 0
X IN /C L K IN
R E F C L K
P D # /O E
V S S
V D D
2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, spread percentage, temper-
ature, and output load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at
http://www.cypress.com/clock/appnotes.html, or contact your local Cypress Field Application Engineer.
3. Since the load capacitors (C
and C
) are provided by the CY25100, no external capacitors are needed on the XIN and XOUT pins to match the crystal load
XOUT
XIN
capacitor (C ). Only a single 0.1-µF bypass capacitor is required on the V pin.
L
DD
4. If an external clock is used, apply the clock to XIN (pin 3) and leave XOUT (pin 2) floating (unconnected).
5. If SSON# (pin 8) is LOW (V ), the frequency modulation will be on at SSCLK pin (pin 7).
SS
Document #: 38-07499 Rev. *D
Page 5 of 11
CY25100
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B
)
t
1B
t
1A
OUTPUT
Output Rise/Fall Time (SSCLK and REFCLK)
OUTPUT
VDD
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x V )/SR1 (or SR3)
DD
Output Fall time (Tf) = (0.6 x V )/SR2 (or SR4)
DD
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Power-down Timing and Power-up Timing
VDD
VIH
POWER-
DOWN
VIL
tPU
0V
High Impedance
CLKOUT
(Asynchronous
)
tSTP
Output Enable/Disable Timing
VDD
VIH
OUTPUT
TOE2
ENABLE
VIL
0V
High Impedance
CLKOUT
(Asynchronous
)
TOE1
Document #: 38-07499 Rev. *D
Page 6 of 11
CY25100
Informational Graphs [6]
172.5
171.5
170.5
169.5
168.5
167.5
166.5
165.5
164.5
163.5
162.5
161.5
160.5
159.5
169.5
169
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= +/-1%
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= -4%
168.5
168
167.5
167
166.5
Fnominal
166
165.5
Fnominal
165
164.5
164
163.5
163
162.5
0
20
40
60
80
100 120 140
Time (us)
160 180 200
0
20
40
60
80
100
120
140 160 180
200
Time (us)
68.5
68
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= -4%
67.5
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= +/-1%
67
66.5
66
67.5
67
66.5
Fnominal
66
Fnominal
65.5
65
65.5
64.5
64
65
63.5
64.5
0
20
40
60
80
100
120
140 160
180
200
0
20
40
60 80
100 120 140 160 180 200
Time (us)
Time (us)
IDD vs. SSCLK
Tem perature=25C, VDD=3.3V, CLOAD=15pF, SS off,
Refclk = 30M Hz
Duty Cycle vs. REFCLK
( CLOAD=15pF)
30
25
20
15
10
5
60
58
56
54
52
50
48
46
44
42
40
0
0
50
100
150
200
0
50
100
150
200
REFCLK (MHz)
SSCLK (M Hz)
Note:
6. The “Informational Graphs” are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on
pages 4 and 5 for device specifications.
Document #: 38-07499 Rev. *D
Page 7 of 11
CY25100
Informational Graphs (continued)[6]
Measured Spread% vs. VDD over Temperature
(Target Spread = 0.5%, Fout=100MHz, CLOAD=15pF)
Measured Spread% vs. VDD over
Temperature
(Target Spread = 5.0%, Fout=100MHz, CLOAD=15pF)
0.60%
0.55%
0.50%
0.45%
0.40%
6.00%
5.50%
5.00%
4.50%
4.00%
-40C
25C
85C
-40C
25C
85C
2.7
3
3.3
3.6
3.9
2.7
3
3.3
3.6
3.9
VDD (V)
VDD (V)
SSCLK Attenuation vs. VDD over Temperature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=0.5%, CLOAD=15pF)
SSCLK Attenuation vs. VDD over Temperature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=5.0%, CLOAD=15pF)
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-40C
25C
85C
-40C
25C
85C
-10
2.7
3
3.3
3.6
3.9
2.7
3
3.3
3.6
3.9
VDD (V)
VDD (V)
SSCLK EMI Attenuation vs. Spread%
Max Cycle-Cycle Jitter on SSCLK vs.
Temperature
(SSCLK=100MHz, VDD=3.3V, CLOAD=15pF, +/-
2%spread, REFCLK off)
(Measured at 7th Harmonic Temp=25C, VDD=3.3V,
SSCLK=100MHz, Measured on Cypress
Characterization board w ith CLOAD=15pF)
0
-2
200
175
150
125
100
75
-4
-6
-8
-10
-12
-14
-16
50
25
0
0.0% 0.5%
1.0% 1.5% 2.0%
2.5% 3.0% 3.5% 4.0%
4.5% 5.0%
-40
-20
0
20
40
60
80
100
Spread %
Temperature (deg C)
Document #: 38-07499 Rev. *D
Page 8 of 11
CY25100
Ordering Information
Part Number[7]
Package description
Product Flow
CY25100SCF
CY25100SXCF
CY25100SIF
CY25100SXIF
CY25100ZCF
CY25100ZXCF
CY25100ZIF
8-pin Small Outline Integrated Circuit(SOIC)
8-pin Small Outline Integrated Circuit (SOIC) - Lead Free
8-pin Small Outline Integrated Circuit (SOIC)
8-pin Small Outline Integrated Circuit (SOIC) - Lead Free
8-pin Thin Shrunk Small Outline Package (TSSOP)
8-pin Thin Shrunk Small Outline Package (TSSOP) - Lead Free
8-pin Thin Shrunk Small Outline Package (TSSOP)
8-pin Thin Shrunk Small Outline Package (TSSOP)- Lead Free
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
CY25100ZXIF
CY25100SXC-XXXW 8-pin Small Outline Integrated Circuit (SOIC)- Lead Free
CY25100SXC-XXXWT 8-pin Small Outline Integrated Circuit (SOIC) – Tape and Reel- Lead Free
CY25100SXI-XXXW
CY25100SXI-XXXWT 8-pin Small Outline Integrated Circuit (SOIC)–Tape and Reel- Lead Free
CY25100ZXC-XXXW 8-pin Thin Shrunk Small Outline Package (TSSOP)- Lead Free
8-pin Small Outline Integrated Circuit (SOIC)- Lead Free
CY25100ZXC-XXXWT 8-pin Thin Shrunk Small Outline Package (TSSOP)–Tape and Reel- Lead Free Commercial, 0 to 70°C
CY25100ZXI-XXXW 8-pin Thin Shrunk Small Outline Package (TSSOP)- Lead Free Industrial, –40 to 85°C
CY25100ZXI-XXXWT 8-pin Thin Shrunk Small Outline Package (TSSOP)–Tape and Reel- Lead Free Industrial, –40 to 85°C
CY3672
CY3672-PRG
CY3690
FTG Development Kit
FTG programmer
CY25100ZCF Socket adapter (TSSOP)
CY25100SCF Socket adapter (SOIC)
n/a
n/a
n/a
n/a
CY3691
Package Diagrams
8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
51-85066-*C
0.0138[0.350]
0.0192[0.487]
Note:
7. “XXX” denotes the assigned product dash number. “W” denotes the different programmed frequency and/or spread % options.
Document #: 38-07499 Rev. *D
Page 9 of 11
CY25100
Package Diagrams (continued)
8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
2.90[0.114]
3.10[0.122]
51-85093-*A
CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07499 Rev. *D
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY25100
Document History Page
Document Title: CY25100 Field-and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
Document Number: 38-07499
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
126578
128753
130342
06/27/03
08/29/03
12/02/03
CKN
New Data Sheet
IJATMP Changes to reflect field programmability
*B
RGL
RGL
RGL
Changes to Application Circuit diagram and correction to the package de-
scription listed under the Ordering Information table for CY3690 and CY3691.
*C
*D
204121
215392
See ECN
See ECN
Add Industrial Temperature Range
Corrected the Ordering Information to match the DevMaster
Added Lead Free devices
Document #: 38-07499 Rev. *D
Page 11 of 11
相关型号：
CY25100ZCF
Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
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CY25100ZIF
Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
CYPRESS
CY25100ZXC-XXXW
Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
CYPRESS
CY25100ZXC-XXXWT
Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
CYPRESS
CY25100ZXCF
Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
CYPRESS
CY25100ZXI-XXXW
Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
CYPRESS
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