CY25245OXCT [CYPRESS]
Frequency-multiplying, Peak-reducing EMI Solution; 频率倍增，峰值降低EMI解决方案
| 型号： | CY25245OXCT |
| 厂家： | 
CYPRESS |
| 描述： | Frequency-multiplying, Peak-reducing EMI Solution |
| 文件： | 总11页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25245
Frequency-multiplying, Peak-reducing
EMI Solution
Features
Key Specifications
• Cypress PREMIS™ SMARTSPREAD™ family offering
Supply voltages: .......................................VDD = 3.3V ± 0.3V
or VDD = 5V ± 10%
• Generates an electromagnetic interference (EMI)
optimized clocking signal at the output
Frequency range:............................ 13 MHz ≤ Fin ≤ 166 MHz
Cycle-to-cycle jitter: ......................................... 250 ps (max)
Output duty cycle: ................................ 40/60% (worst case)
• Selectable output frequency range
• Single 1.25%, 2.5%, 5%, or 10% down or center spread
output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 20-pin Small Shrunk Outline Package
(SSOP)
Pin Configuration[1, 2]
Simplified Block Diagram
3.3V or 5.0V
SSOP
X1
X1
X2
AVDD
MW0^
SDATA
OR1^
SCLK
GND
REFOUT
VDD
GND
IR1*
IR2*
SSOUT
MW1*
GND
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
XTAL
Input
X2
Spread Spectrum
Output
(EMI suppressed)
CY25245
SDATA
SCLK
Serial Interface
3.3V or 5.0V
VDD
MW2^
OR2*
SSON#^
10
Oscillator or
Reference Input
X1
Spread Spectrum
CY25245
Output
SDATA
SCLK
(EMI suppressed)
Serial Interface
Notes:
1. Pins marked with ^ are internal pull-down resistors with weak 250 kΩ.
2. Pins marked with * are internal pull-up resistors with weak 80 kΩ.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07124 Rev. *B
RevisedFebruary2, 2005
CY25245
Pin Definitions
Pin Name Pin No. Pin Type
Pin Description
SSOUT
15
O
Output Modulated Frequency. Frequency modulated copy of the input clock (SSON#asserted).
REFOUT
20
O
Non-modulated Output. This pin provides a copy of the reference frequency. This output will
not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#.
X1
1
2
I
I
I
I
Crystal Connection or External Reference Frequency Input. This pin has dual functions. It
may either be connected to an external crystal, or to an external reference clock.
X2
Crystal Connection. Input connection for an external crystal. If using an external reference, this
pin must be left unconnected.
SSON#
MW0:2
10
Spread Spectrum Control (Active LOW). Asserting this signal (active LOW) turns the internal
modulation waveform on. This pin has an internal pull-down resistor.
4, 11, 14
Modulation Width Selection. When Spread Spectrum feature is turned on, these pins are used
to select the amount of variation and peak EMI reduction that is desired on the output signal.
MW0:Down, MW1:Up, MW2:Down (see Table 2).
IR1:2
17, 16
6, 9
I
I
Reference Frequency Selection. The logic level provided at this input indicates to the internal
logic what range the reference frequency is in and determines the factor by which the device
multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors.
Output Frequency Selection Bits. These pins select the frequency operation for the output.
Refer to Table 1. The OR2 pin has an internal pull-up resistor. The OR1 pin has internal pull-down
resistors.
OR1:2
SCLK
SData
VDD
AVDD
GND
7
5
I
I/O
P
P
G
Clock Pin for SMBus Circuitry.
Data Pin for SMBus Circuitry.
Power Connection. Connected to 3.3V or 5V power supply.
Analog Power Connection. Connected to 3.3V or 5V power supply.
Ground Connection. Connect all ground pins to the common ground plane.
12, 19
3
8, 13, 18
Table 1. Frequency Configuration (Frequencies in MHz)
Multiplier
Output/
Input
Modulation and
Range of Fin Frequency
Settings
Range of Fout Required R Settings Power-down Settings
Min.
14
14
14
25
25
25
50
50
50
Max.
41.7
41.7
41.7
83.3
83.3
83.3
166
OR2
OR1
Min.
14
28
56
13
25
50
13
25
Max.
41.7
83.3
166
41.7
83.3
166
41.7
83.3
166
N/A
N/A
N/A
N/A
IR2
0
0
0
1
1
1
1
1
IR1
1
1
1
0
0
0
1
1
MW2
MW1
Table 2
0
1
1
0
1
1
0
1
1
0
0
0
0
1
0
1
1
0
1
1
0
1
0
0
0
0
1
2
4
0.5
1
2
0.25
0.5
1
N/A
N/A
N/A
N/A
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
166
166
50
1
1
Reserved
N/A
N/A
N/A
N/A
As Set
As Set
As Set
As Set
As Set
As Set
As Set
As Set
1
1
0
0
0
1
0
1
Power-down Hi-Z
Power-down 0
Power-down 1
Document #: 38-07124 Rev. *B
Page 2 of 11
CY25245
Table 2. Modulation Width Selection Table
Bandwith Limit Frequencies as a % Value of Fout
MW0 = 0 MW0 = 1
EMI Reduction
Modulation Setting
MW2
MW1
Low
High
100%
100%
100%
100%
Low
99.375%
98.75%
97.5%
95%
High
100.625%
101.25%
102.5%
105%
Minimum EMI Control
Suggested Setting
Alternate Setting
Maximum EMI reduction
0
0
1
1
0
1
0
1
98.75%
97.5%
95.0%
90.0%
Overview
The CY25245 product is one of a series of devices in the
Cypress PREMIS family. The PREMIS family incorporates the
latest advances in PLL spread spectrum frequency synthe-
sizer techniques. By frequency modulating the output with
a low-frequency carrier, peak EMI is greatly reduced. Use of
this technology allows systems to pass increasingly difficult
EMI testing without resorting to costly shielding or redesign.
times the reference frequency.[3] The unique feature of the
Spread Spectrum Frequency Timing Generator is that a
modulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a
predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum
process has little impact on system performance.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The
Simplified Block Diagram shows a simple implementation.
Frequency Selection With SSFTG
In spread spectrum frequency timing generation, EMI
reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pins
MW0:2 as shown in Table 2.
A larger spreading percentage improves EMI reduction.
However, large spread percentages may either exceed
system maximum frequency ratings or lower the average
frequency to a point where performance is affected. For these
reasons, spreading percentage options are provided.
Functional Description
The CY25245 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
V
DD
Clock Input
CLKOUT
(EMI suppressed)
Freq.
Divider
Q
Phase
Charge
Pump
Post
Reference Input
VCO
Σ
Detector
Dividers
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
Note:
3. For the CY25245, the output frequency is nominally equal to the input frequency.
Document #: 38-07124 Rev. *B
Page 3 of 11
CY25245
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the ampli-
tudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread.
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is as described in Table 2.
Figure 3 details the Cypress spreading pattern. Cypress does
offer options with more spread and greater EMI reduction.
Contact your local Sales representative for details on these
devices.
EMI Reduction
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Down Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
Document #: 38-07124 Rev. *B
Page 4 of 11
CY25245
power management functions. Table 3 summarizes the control
Serial Data Interface
functions of the serial data interface.
The CY25245 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions. Upon power-up, the CY25245
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
Operation
Data is written to the CY25245 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
Writing Data Bytes
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable Any individual clock output(s) can be disabled.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to unused
PCI slots.
Disabled outputs are actively held LOW.
CPUClockFrequency Provides CPU/PCI frequency selections through For alternate microprocessors and power
Selection
software. Frequency is changed in a smooth and management options. Smooth frequency transition
controlled fashion.
allows CPU frequency change under normal system
operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output three-state
(Reserved)
Puts clock output into a high-impedance state.
Reserved function for future device revision or
production device testing.
Production PCB testing.
No user application. Register bit must be written as 0.
Table 4. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the CY25245 to accept the bits in Data Bytes 0–6 for internal register
configuration. Since other devices may exist on the same common serial data
bus, it is necessary to have a specific slave address for each potential receiver.
The slave receiver address for the CY25245 is 11010010. Register setting will
not be made if the Slave Address is not correct (or is for an alternate slave
receiver).
2
3
Command Code Don’t Care
Unused by the CY25245, therefore bit values are ignored (“don’t care”). This byte
must be included in the data write sequence to maintain proper byte allocation.
The Command Code Byte is part of the standard serial communication protocol
and may be used when writing to another addressed slave receiver on the serial
data bus.
Unused by the CY25245, therefore bit values are ignored (“don’t care”). This byte
must be included in the data write sequence to maintain proper byte allocation.
The Byte Count Byte is part of the standard serial communication protocol and may
be used when writing to another addressed slave receiver on the serial data bus.
Byte Count
Don’t Care
4
5
6
7
8
9
10
11
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Refer to Table 5 The data bits in Data Bytes 0–7 set internal CY25245 registers that control device
operation. The data bits are only accepted when the Address Byte bit sequence
is 11010010, as noted above. For description of bit control functions, refer to
Table 5, Data Byte Serial Configuration Map.
Document #: 38-07124 Rev. *B
Page 5 of 11
CY25245
Table 5. Data Bytes 0–7 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 0
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Data Byte 1
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Data Byte 2
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Data Byte 3
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Data Byte 4
7
6
5
4
3
2
16
17
9
6
–
IR2
IR1
OR2
OR1
–
MSB of Input Range Select
LSB of Input Range Select
MSB of Output Range Select
LSB of Output Range Select
Hardware/Software Frequency Select
Stop Function
Refer to Table 1
Refer to Table 1
Refer to Table 1
Refer to Table 1
0
1
1
0
0
0
Hardware
Normal
Software
Stop
–
–
Document #: 38-07124 Rev. *B
Page 6 of 11
CY25245
Table 5. Data Bytes 0–7 Serial Configuration Map (continued)
Affected Pin
Bit Control
Bit(s)
1
0
Pin No.
Pin Name
SSON#
MW0
Control Function
Spread Spectrum
LSB of Modulation Width Selection
0
1
Default
10
4
Spread On
Spread Off
0
0
Refer to Table 2
Data Byte 5
7
6
5
4
3
2
1
0
11
14
20
15
–
–
–
–
MW2
MW1
MSB of Modulation Width Selection
Modulation Width Selection Bit
Refer to Table 2
Refer to Table 2
0
1
1
1
0
0
0
0
REFOUT Output Enable
SSOUT
Disabled
Enabled
Output Enable
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Disabled
Enabled
–
–
–
–
–
–
–
–
–
–
–
–
Data Byte 6
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Data Byte 7
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
Document #: 38-07124 Rev. *B
Page 7 of 11
CY25245
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Parameter
VDD, VIN
TSTG
TA
TB
PD
Description
Voltage on Any Pin with Respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±0.3V[4]
Parameter
IDD
tON
Description
Supply Current
Power-up Time
Test Condition
Min.
Typ.
18
Max.
32
5
Unit
mA
ms
First locked clock cycle after Power
Good
VIL
VIH
VOL
VOH
IIL
Input Low Voltage
0.8
0.4
V
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
2.4
2.4
–50
–50
V
Note 4
Note 4
@ 0.4V, VDD = 3.3V
@ 2.4V, VDD = 3.3V
50
50
µA
µA
mA
mA
pF
kΩ
Ω
IIH
IOL
IOH
CI
RP
ZOUT
15
15
7
250
25
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10%
Parameter
IDD
tON
Description
Supply Current
Power-up Time
Test Condition
Min.
Typ.
30
Max.
50
5
Unit
mA
ms
First locked clock cycle after
Power Good
VIL
VIH
VOL
VOH
IIL
Input Low Voltage
0.15VDD
0.4
V
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-up Resistor
Clock Output Impedance
0.7VDD
2.4
–50
–50
V
Note 4
Note 4
@ 0.4V, VDD = 5V
@ 2.4V, VDD = 5V
50
50
µA
µA
mA
mA
pF
kΩ
Ω
IIH
IOL
IOH
CI
RP
ZOUT
24
24
7
250
25
Note:
4. Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor.
Document #: 38-07124 Rev. *B
Page 8 of 11
CY25245
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±0.3V or 5V±10%
Parameter
fIN
fOUT
tR
tF
tOD
tID
Description
Input Frequency
Test Condition
Input Clock
Spread Off
15-pF load, 0.8V–2.4V
15-pF load, 2.4V–0.8V
15-pF load
Min.
14
13
Typ.
Max.
166
166
5
5
60
Unit
MHz
MHz
ns
ns
%
Output Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle
Input Duty Cycle
Jitter, Cycle-to-cycle
2
2
40
40
60
300
%
ps
tJCYC
250
Ordering Information
Ordering Code
CY25245PVC
CY25245PVCT
Lead-free
Package Type
20-pin Plastic SSOP
20-pin Plastic SSOP —Tape and Reel
Product Flow
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
CY25245OXC
CY25245OXCT
20-pin Plastic SSOP
20-pin Plastic SSOP —Tape and Reel
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Layout Example
+3.3V Supply
FB
0.005 µF
G
VDDQ3
µF
C3
G
1
2
20
19
G
V
G
G
G
V
3
4
5
18
17
16
G
G
6
7
15
14
13
12
G
G
G
8
9
V
G
G
11
10
µF
µF
C2 = 0.005
Ceramic Caps C1 = 10–22
FB = Vishay ILB1206 – 300 (300Ω @ 100 MHz) or TDK ACB2012L-120 or Murata BLM21B601
= VIA to GND plane layer V =VIA to respective supply plane layer
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1 µF ceramic.
Document #: 38-07124 Rev. *B
Page 9 of 11
CY25245
Package Drawing and Dimension
20-pin (5.3 mm) Shrunk Small Outline Package O20
51-85077-*C
PREMIS and SMARTSPREAD are trademarks of Cypress Semiconductor Corporation. All product and company names men-
tioned in this document are the trademarks of their respective holders.
Document #: 38-07124 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY25245
Document History Page
Document Title: CY25245 Frequency-multiplying, Peak-reducing EMI Solution
Document Number: 38-07124
Issue
Date
11/13/01
01/08/03
See ECN
Orig. of
Change
IKA
RGL
RGL
REV.
**
*A
ECN NO.
109865
122550
318273
Description of Change
New data sheet
Added SMARTSPREAD in the features area
Added Lead-free devices
*B
Document #: 38-07124 Rev. *B
Page 11 of 11
相关型号：
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