CY25402SXIT [CYPRESS]
Two PLL Programmable Clock Generator with Spread Spectrum; 两个PLL可编程时钟发生器，带有扩频
| 型号： | CY25402SXIT |
| 厂家： | 
CYPRESS |
| 描述： | Two PLL Programmable Clock Generator with Spread Spectrum |
| 文件： | 总14页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25402/CY25422/CY25482
Two PLL Programmable Clock Generator
with Spread Spectrum
■ AbilitytosynthesizenonstandardfrequencieswithFractional-N
capability
Features
■ Two fully integrated phase locked loops (PLLs)
■ Three clock outputs with programmable drive strength
■ Glitch-free outputs while frequency switching
■ 8-pin small outline integrated circuit (SOIC) package
■ Commercial and Industrial temperature ranges
■ Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
■ Reference clock input voltage range
❐ 2.5 V, 3.0 V, and 3.3 V for CY25482
❐ 1.8 V for CY25402 and CY25422
Benefits
■ Wide operating output frequency range
❐ 3 to 166 MHz
■ Multiple high performance PLLs allow synthesis of unrelated
frequencies
■ Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■ Programmable spread spectrum with center and down spread
option and lexmark and linear modulation profiles
■ VDD supply voltage options:
❐ 2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐ 1.8 V for CY25422
■ Application specific programmableEMIreduction usingspread
spectrum for clocks
■ Programmable PLLs for system frequency margin tests
■ Selectable output clock voltages independent of VDD
❐ 2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐ 1.8 V for CY25422
:
■ Meets critical timing requirements in complex system designs
■ Suitability for PC, consumer, portable, and networking
applications
■ Frequency select feature with option to select four different
frequencies
■ Capable of zero parts per million (PPM) frequency synthesis
■ Power-down, Output Enable, and SS ON/OFF controls
■ Low jitter, high accuracy outputs
error
■ Uninterrupted system operation during clock frequency switch
■ Application compatibility in standard and low power systems
Block Diagram
Crossbar
XIN/
CLK1
Output
Switch
EXCLKIN
PLL 1
(SS)
OSC
Dividers
and
XOUT
MUX
and
REFOUT
CLK2
Drive
PLL 2
(SS)
Control
Logic
Strength
Control
FS0
FS1
SSON
PD#/OE
Cypress Semiconductor Corporation
Document #: 001-12565 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 20, 2011
CY25402/CY25422/CY25482
Contents
Pin Description .................................................................3
General Description .........................................................5
2 Configurable PLLs ....................................................5
Input Reference Clocks ...............................................5
VDD Power Supply Options ........................................5
Output Source Selection .............................................5
Spread Spectrum Control ............................................5
Frequency Select ........................................................5
Glitch-Free Frequency Switch .....................................5
PD#/OE Mode .............................................................5
Output Drive Strength ..................................................5
Generic Configuration and Custom Frequency ...........5
Absolute Maximum Conditions .......................................6
Recommended Operating Conditions ............................6
DC Electrical Specifications ............................................7
AC Electrical Specifications ............................................8
Recommended Crystal Specification for SMD Package 8
Test and Measurement Setup ..........................................9
Voltage and Timing Definitions .......................................9
Recommended Crystal Specification for
Thru-Hole Package ...........................................................9
Possible Configurations .............................................10
Ordering Code Definitions .........................................11
Package Drawing and Dimensions ...............................11
Acronyms ........................................................................12
Document Conventions .................................................12
Units of Measure .......................................................12
Document History Page .................................................13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC® Solutions .......................................................14
Document #: 001-12565 Rev. *F
Page 2 of 14
CY25402/CY25422/CY25482
Table 1. Device Selector Guide
Device
CY25402
CY25482
CY25422
Crystal Input
EXCKLKIN Input
VDD
Yes
No
1.8 V LVCMOS
2.5 V, 3.0 V, 3.3 V
2.5 V, 3.0 V, 3.3 V LVCMOS
1.8 V LVCMOS
2.5 V, 3.0 V, 3.3 V
1.8 V
Yes
Pin Description
Figure 1. Pin Diagram - CY25402 8-LD SOIC
XIN/
EXCLKIN
XOUT
8
1
VDD
GND
7
6
5
2
3
4
CY25402
CLK1
CLK2/SSON
PD#/OE/FS1
REFOUT/
FS0
Table 2. Pin Definition - CY25402 (2.5 V, 3.0 V, or 3.3 V Supply)
Pin Number
Name
IO
Description
1
XIN/EXCLKIN Input
Crystal input or 1.8 V External clock input
Power supply: 2.5 V, 3.0 V, or 3.3 V
2
3
4
5
VDD
Power
Output
CLK1
Programmable clock output with spread spectrum
REFOUT/FS0 Output/input
PD#/OE/FS1 Input
Multifunction programmable pin: Reference clock output or frequency select pin
Multifunction programmable pin: Power-down, output enable or Frequency select
pin
6
CLK2/SSON
Output/input
Multifunction programmable pin: Programmable clock output with spread spectrum
or Spread spectrum ON/OFF control pin
7
8
GND
Power
Output
Power supply ground
Crystal output
XOUT
Document #: 001-12565 Rev. *F
Page 3 of 14
CY25402/CY25422/CY25482
Figure 2. Pin Diagram - CY25482 8-LD SOIC
EXCLKIN
DNU
GND
8
1
VDD
7
6
5
2
3
4
CY25482
CLK1
CLK2/SSON
PD#/OE/FS1
REFOUT/
FS0
Table 3. Pin Definition - CY25482 (2.5 V, 3.0 V, or 3.3 V Supply)
Pin Number
Name
EXCLKIN
VDD
IO
Description
1
Input
2.5 V, 3.0 V, or 3.3 V external clock input
2
3
4
5
Power
Power Supply: 2.5 V, 3.0 V, or 3.3 V
CLK1
Output
Programmable clock output with spread spectrum
Multifunction programmable pin: Reference clock output or frequency select pin
REFOUT/FS0 Output/input
PD#/OE/FS1 Input
Multifunction programmable pin: Power-down, output enable or frequency select
pin
6
CLK2/SSON
Output/input
Multifunction Programmable pin: Programmable clock output with spread spectrum
or spread spectrum ON/OFF control pin
7
8
GND
DNU
Power
Output
Power supply ground
Do not use this pin
Figure 3. Pin Diagram - CY25422 8-LD SOIC
XIN/
EXCLKIN
XOUT
8
1
VDD
GND
7
6
5
2
3
4
CY25422
CLK1
CLK2/SSON
PD#/OE/FS1
REFOUT/
FS0
Table 4. Pin Definition - CY25422 (1.8 V Supply)
Pin Number
Name
IO
Description
1
XIN/EXCLKIN Input
Crystal input or 1.8 V external clock input
2
3
4
5
VDD
Power
Output
Power supply: 1.8 V
CLK1
Programmable clock output with spread spectrum
Multifunction programmable pin: reference clock output or frequency select pin
REFOUT/FS0 Output/input
PD#/OE/FS1
Input
Multifunction programmable pin: power-down, output enable or frequency select
pin
6
CLK2/SSON
Output/input
Multifunction programmable pin: programmable clock output with spread spectrum
or spread spectrum ON/OFF control pin
7
8
GND
Power
Output
Power supply ground
Crystal output
XOUT
Document #: 001-12565 Rev. *F
Page 4 of 14
CY25402/CY25422/CY25482
General Description
2 Configurable PLLs
Glitch-Free Frequency Switch
The CY25402, CY25422, and CY25482 have two programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having two PLLs is that a
single device generates two independent frequencies from a
single crystal.
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched using output dividers. This feature enables
uninterrupted system operation while clock frequency is being
switched.
Input Reference Clocks
PD#/OE Mode
The input reference clock can be either a crystal or a clock signal,
for CY25402 and CY25422 while just a clock signal for CY25482.
The input frequency range for crystal (XIN) is 8 MHz to 48 MHz
and that for external reference clock (EXCLKIN) is 8 MHz to 166
MHz. The voltage range of the reference clock input for CY25482
is 2.5 V/3.0 V/3.3 V while that for CY25402 and CY25422 is
1.8 V. This gives user an option for this device to be compatible
for different input clock voltage levels in the system.
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
VDD Power Supply Options
Output Drive Strength
These devices have programmable power supply options. The
CY25402/CY25482 is a high voltage part that can be
programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V while
CY25422 is a low voltage part that can operate at 1.8 V.
The DC drive strength of the individual clock output can be
programmed for different values. Table 4 on page 4 shows the
typical rise and fall times for different drive strength settings.
Output Source Selection
Table 5. Output Drive Strength
These devices have programmable input sources for each of its
clock outputs. There are three available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock
source selection is done by using three out of three crossbar
switch. Thus, any one of these three available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have two independent clock outputs.
Rise/Fall Time (ns)
Output Drive Strength
(Typical Value)
Low
Mid Low
Mid High
High
6.8
3.4
2.0
1.0
Spread Spectrum Control
Generic Configuration and Custom Frequency
Both PLLs (PLL1 and PLL2) have spread spectrum capability for
EMI reduction in the system. The device uses a Cypress
proprietary PLL and spread spectrum clock (SSC) technology to
synthesize and modulate the frequency of the PLL. The spread
spectrum feature can be turned on or off using a multifunction
control pin (CLK2/SSON). It can be programmed to either center
spread range from ±0.125% to ±2.50% or down spread range
from –0.25% to –5.0% with lexmark or linear profile.
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY25402, CY25422, and CY25482 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
field application engineer (FAE) or sales representative.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
REFOUT/FS0 and PD#/OE/FS1 which if programmed as
frequency select inputs, can be used to select among these
arbitrarily programmed frequency settings. Each output has
programmable output divider options.
Document #: 001-12565 Rev. *F
Page 5 of 14
CY25402/CY25422/CY25482
Absolute Maximum Conditions
Parameter
VDD
Description
Supply voltage for CY25402/CY25482
Supply voltage for CY25422
Input voltage for CY25402/CY25482
Input voltage for CY25422
Temperature, Storage
Condition
Min
–0.5
–0.5
–0.5
–0.5
–65
2000
–
Max
4.5
Unit
V
–
–
VDD
2.6
V
VIN
Relative to VSS
VDD+0.5
2.2
V
VIN
Relative to VSS
V
TS
Non Functional
+150
–
°C
V
ESDHBM
UL-94
MSL
ESD protection (human body model)
Flammability rating
JEDEC EIA/JESD22-A114-E
V-0 at1/8 in.
10
ppm
Moisture sensitivity level
SOIC package
3
Recommended Operating Conditions
Parameter
Description
VDD Operating voltage for CY25402/CY25482
Min
2.25
1.65
0
Typ
Max
3.60
1.95
+70
+85
15
Unit
V
V
–
1.8
–
DD
VDD
VDD Operating voltage for CY25422
Commercial ambient temperature
Industrial ambient temperature
Maximum load capacitance
V
T
°C
°C
pF
ms
AC
T
–40
–
--
AI
C
–
LOAD
t
Power-up time for all V to reach minimum specified voltage
0.05
–
500
PU
DD
(power ramps must be monotonic)
Document #: 001-12565 Rev. *F
Page 6 of 14
CY25402/CY25422/CY25482
DC Electrical Specifications
Parameter
Description
Output low voltage
Conditions
Min
Typ
Max
Unit
V
IOL = 2 mA, drive strength = [00]
–
–
0.4
V
OL
OH
IL1
I
I
OL = 3 mA, drive strength = [01]
OL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
IOH = –2 mA, drive strength = [00]
V
V
Output high voltage
VDD – 0.4
–
–
–
V
V
I
OH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
I
OH = –12 mA, drive strength = [11]
–
Input low voltage of PD#/OE, FS0, FS1
and SSON
–
0.2*VDD
V
V
Input low voltage of EXCLKIN
–
–
–
–
–
0.18
–
V
V
IL2
Input High Voltage of PD#/OE, FS0,
FS1 and SSON
0.8*VDD
IH1
V
V
Input high voltage of EXCLKIN for
CY25402/CY25422
–
–
1.62
–
–
2.2
–
V
V
IH2
IH3
Input high voltage of EXCLKIN for
CY25482
0.8*VDD
IIL
Input low current, PD#/OE/FS1
Input high current, PD#/OE/FS1
VIN = 0V
–
–
–
–
–
–
10
10
10
µA
µA
µA
IIH
VIN = VDD
IILDN
Input low current, SSON and FS0 pins VIN = 0V (Internal pull down resistor
= 160k typ.)
IIHDN
RDN
Input high current, SSON and FS0 pins VIN = VDD (Internal pull down
resistor = 160k typ.)
14
–
36
µA
Pull-down resistor of CLK1,
Output clocks in off state by setting
100
160
250
k
REFOUT/FS0 and CLK2/SSON pins PD# = Low
[1,2]
I
Supply current for CY25422
PD# = High, No load
–
–
–
–
12
14
3
–
–
–
7
mA
mA
µA
pF
DD
Supply current for CY25402/CY25482 PD# = High, No load
[1]
I
Standby current
PD# = Low
DDS
[2]
C
Input capacitance
SSON, PD#/OE/FS1 and FS0 pins
–
IN
Notes
1. Guaranteed by design but not 100% tested
2. Configuration dependent.
Document #: 001-12565 Rev. *F
Page 7 of 14
CY25402/CY25422/CY25482
AC Electrical Specifications
Parameter
Description
Conditions
Min
8
Typ
–
Max
48
Unit
MHz
MHz
F
F
(crystal) Crystal Frequency, XIN
IN
IN
(clock)
Input Clock Frequency
(EXCLKIN)
8
–
166
F
Output Clock Frequency
3
166
55
MHz
%
–
CLK
DC
Output Duty Cycle, All
Clocks except Ref Out
Duty Cycle is defined in Figure 5 on page 9; t /t ,
45
50
1
2
measured at 50% of V
DD
DC
Ref Out Duty Cycle
Ref In Min 45%, Max 55%
40
–
–
60
–
%
[3]
TRF1
Output Rise/Fall Time
Measured from 20% to 80% of VDD, as shown in
Figure 6 on page 9, CLOAD = 15 pF, drive strength [00]
6.8
ns
[3]
TRF2
TRF3
TRF4
TCCJ
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Measured from 20% to 80% of VDD, as shown in
Figure 6 on page 9, CLOAD = 15 pF, drive strength [01]
–
–
–
–
–
3.4
2.0
1.0
100
1
–
–
–
–
3
ns
ns
ns
ps
ms
[3]
Measured from 20% to 80% of VDD, as shown in
Figure 6 on page 9, CLOAD = 15 pF, drive strength [10]
[3]
Measured from 20% to 80% of VDD, as shown in
Figure 6 on page 9, CLOAD = 15 pF, drive strength [11]
[3,4]
[4]
Cycle-to-cycle Jitter
(peak)
Configuration dependent. See Table 5
TLOCK
PLL Lock Time
Measured from 90% of the applied power supply level
Table 6. Configuration Example for C-C Jitter
CLK1 Output
CLK2 Output
Ref. Frequency
(MHz)
Freq. (MHz)
C-C Jitter Typ (ps)
Freq. (MHz)
C-C Jitter Typ (ps)
14.3181
19.2
27
8.0
74.25
48
134
99
48
8
92
91
67
166
166
103
137
48
48
93
Recommended Crystal Specification for SMD Package
Parameter
Fmin
Description
Range 1
Range 2 Range 3
Unit
MHz
MHz
Minimum frequency
8
14
135
4
14
28
50
4
28
48
30
2
Fmax
R1
Maximum frequency
Motional resistance (ESR)
Shunt capacitance
C0
pF
CL
Parallel load capacitance
18
300
14
300
12
300
pF
DL(max)
Maximum crystal drive level
µW
Notes
3. Guaranteed by design but not 100% tested
4. Configuration dependent.
Document #: 001-12565 Rev. *F
Page 8 of 14
CY25402/CY25422/CY25482
Recommended Crystal Specification for Thru-Hole Package
Parameter
Fmin
Description
Range 1 Range 2 Range 3
Unit
MHz
MHz
Minimum frequency
8
14
14
24
24
32
Fmax
R1
Maximum frequency
Motional resistance (ESR)
Shunt capacitance
90
50
30
C0
7
7
7
pF
CL
Parallel load capacitance
Maximum crystal drive level
18
12
12
pF
DL(max)
1000
1000
1000
µW
Test and Measurement Setup
Figure 4. Test and Measurement Setup
VDD
Outputs
CLOAD
0.1 F
DUT
GND
Voltage and Timing Definitions
Figure 5. Duty Cycle Definition
t1
t2
VDD
50% of VDD
0V
Clock
Output
Figure 6. Rise Time = TRF, Fall Time = TRF
T
T
RF
RF
VDD
80% of VDD
20% of VDD
0V
Clock
Output
Document #: 001-12565 Rev. *F
Page 9 of 14
CY25402/CY25422/CY25482
Ordering Information
Part Number
Pb-free
Type
Package
Supply Voltage
Production Flow
CY25402SXC
CY25402SXCT
CY25422FSXC
CY25422FSXCT
CY25482SXC
CY25482SXCT
CY25402SXI
Field Programmable
Field Programmable
Field Programmable
Field Programmable
Field Programmable
Field Programmable
Field Programmable
Field Programmable
Field Programmable
Field Programmable
Field Programmable
Field Programmable
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
8-pin SOIC
8-pin SOIC -Tape and reel 1.8 V
8-pin SOIC
8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
1.8 V
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25402SXIT
CY25422FSXI
CY25422FSXIT
CY25482SXI
8-pin SOIC
8-pin SOIC -Tape and reel 1.8 V
8-pin SOIC
1.8 V
Industrial, -40 °C to +85 °C
Industrial, -40 °C to +85 °C
2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
CY25482SXIT
Programmer
8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
CY3675-CLKMAKER1
CY3675-SOIC8A
Programming kit
Socket Adapter Board, for programming CY25402, CY25403, CY25422,
CY25423, CY25482 and CY25483
Possible Configurations
Some product offerings are factory programmed customer specific devices with customized part numbers.The Possible Configurations
table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for
more information.
Part Number[5]
Pb-free
Type
Package
Supply Voltage
Production Flow
CY25402SXC-xxx
CY25402SXC-xxxT
CY25422SXC-xxx
CY25422SXC-xxxT
CY25482SXC-xxx
CY25482SXC-xxxT
CY25402SXI-xxx
CY25402SXI-xxxT
CY25422SXI-xxx
CY25422SXI-xxxT
CY25482SXI-xxx
CY25482SXI-xxxT
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
Factory Programmed
8-pin SOIC
2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
8-pin SOIC
8-pin SOIC -Tape and reel 1.8 V
8-pin SOIC
8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
1.8 V
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
8-pin SOIC
8-pin SOIC -Tape and reel 1.8 V
8-pin SOIC
8-pin SOIC -Tape and reel 2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
1.8 V
Industrial, -40 °C to +85 °C
Industrial, -40 °C to +85 °C
2.5 V, 3.0 V, or 3.3 V Industrial, -40 °C to +85 °C
Note
5. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative
Document #: 001-12565 Rev. *F
Page 10 of 14
CY25402/CY25422/CY25482
Ordering Code Definitions
SX C/I - xxx T
CY254x2
Package Type: (T = Tape and Reel)
Customer specific identification code
Temperature code (C=Commercial or I=Industrial)
8-Pin SOIC package
Marketing Code: CY25402/22/82 = Device Number
Package Drawing and Dimensions
Figure 7. 8-Pin (150-Mil) SOIC S8
51-85066 *D
Document #: 001-12565 Rev. *F
Page 11 of 14
CY25402/CY25422/CY25482
Acronyms
Acronym
Description
drive level
DL
DNU
DUT
EMI
do not use
device under test
electromagnetic interference
electrostatic discharge
field application engineer
frequency select
ESD
FAE
FS
JEDEC EIA
joint electron devices
engineeringcouncilelectronic
industries alliance
LVCMOS
low voltage complemetary
metal oxide semiconductor
OE
output enable
OSC
PD
oscillator
power down
PLL
PPM
SS
phase locked loop
parts per million
spread spectrum
spread spectrum clock
spread spectrum on
SSC
SSON
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
fF
degrees Celsius
femtofarads
mA
MHz
s
milliampere
megahertz
microseconds
millisecond
microwatts
nanoseconds
picofarads
parts per million
picoseconds
volts
ms
W
ns
pF
ppm
ps
V
ohms
W
watts
Document #: 001-12565 Rev. *F
Page 12 of 14
CY25402/CY25422/CY25482
Document History Page
Document Title: CY25402/CY25422/CY25482 Two PLL Programmable Clock Generator with Spread Spectrum
Document Number: 001-12565
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
690296
815788
1428744
See ECN
See ECN
RGL
RGL
New Data Sheet
Minor Change: To post on web
*A
*B
See ECN RGL/AESA Changed data sheet format to match generic part, CY2544/46
Added new device and specification for high ref. input voltage part, CY25482
Removed Preliminary from Title page
Replaced CLK2 with REFOUT
*C
*D
2748211
2898568
08/10/09
06/02/10
TSAI
KVM
Posting to external web.
Updated the Ordering Information table and package diagram.
Moved ‘xxx’ parts to Possible Configurations table.
Updated template.
*E
*F
3110175 12/14/2010
3235621 04/20/2011
BASH
CXQ
Updated as per new template
Added Units of Measure table
Changed part number from CY25422SXC to CY25422FSXC, from
CY25422SXCT to CY25422FSXCT, from CY25422SXI to CY25422FSXI,
and from CY25422SXIT to CY25422FSXIT.
Document #: 001-12565 Rev. *F
Page 13 of 14
CY25402/CY25422/CY25482
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
®
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-12565 Rev. *F
Revised April 20, 2011
Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
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