CY25404 [CYPRESS]
Quad PLL Programmable Clock Generator with Spread Spectrum; 四PLL可编程时钟发生器，带有扩频
| 型号： | CY25404 |
| 厂家： | 
CYPRESS |
| 描述： | Quad PLL Programmable Clock Generator with Spread Spectrum |
| 文件： | 总13页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25404
Quad PLL Programmable Clock Generator
with Spread Spectrum
Features
■ Four fully integrated phase-locked loops (PLLs)
■ Commercial and Industrial temperature ranges
■ Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
Benefits
■ Multiple high performance PLLs allow synthesis of unrelated
frequencies
■ Wide operating output frequency range
❐ 3 to 166 MHz
■ Nonvolatile programming for personalization of PLL
frequencies,spreadspectrumcharacteristics,drivestrength,
crystal load capacitance, and output frequencies
■ Programmable spread spectrum with center and down
spread option and lexmark and linear modulation profiles
■ Application specific programmable electromagnetic
interference (EMI) reduction using spread spectrum for
clocks
■ Selectable VDD supply voltage options:
❐ 2.5 V, 3.0 V, and 3.3 V
■ Selectableoutputclockvoltages,independentofVDD supply:
❐ 2.5 V, 3.0 V, and 3.3 V
■ Programmable PLLs for system frequency margin tests
■ Meets critical timing requirements in complex system
designs
■ Frequency select feature with option to select eight different
frequencies over nine clock outputs
■ Suitability for PC, consumer, portable, and networking
applications
■ Output enable, and SS ON/OFF controls
■ Low jitter, high accuracy outputs
■ Capable of zero parts per million (PPM) frequency synthesis
error
■ Ability to synthesize nonstandard frequencies with
Fractional-N capability
■ Uninterrupted system operation during clock frequency
switch
■ Up to nine clock outputs with programmable drive strength
■ Glitch-free outputs while frequency switching
■ 20-pin TSSOP package
■ Application compatibility in standard and low power systems
Block Diagram
CLK1
Crossbar
XIN/
EXCLKIN
Bank
1
CLK2
Switch
OSC
Output
PLL1
PLL2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
XOUT
Dividers
and
Bank
2
MUX
and
Drive
FS 0
FS 1
FS 2
Strength
Control
Bank
3
Control
Logic
PLL3
(SS)
PLL4
(SS)
OE
SSON
Cypress Semiconductor Corporation
Document #: 001-43258 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 11, 2011
CY25404
Contents
General Description .........................................................4
Four Configurable PLLs ..............................................4
Input Reference Clocks ...............................................4
VDD Power Supply Options .........................................4
Output Bank Settings ..................................................4
Output Source Selection .............................................4
Spread Spectrum Control ............................................4
Frequency Select ........................................................4
Glitch-Free Frequency Switch .....................................4
Output Enable Mode ...................................................4
Output Drive Strength ..................................................4
Generic Configuration and Custom Frequency ...........4
Absolute Maximum Conditions....................................... 5
Recommended Operating Conditions ............................5
DC Electrical Specifications ............................................6
Recommended Crystal Specification
Recommended Crystal Specification
for Thru-Hole Package .....................................................7
AC Electrical Specifications ............................................7
Test and Measurement Setup ..........................................8
Voltage and Timing Definitions .......................................8
Ordering Information ........................................................9
Possible Configurations ...............................................9
Ordering Code Definitions ...........................................9
Package Drawing and Dimensions ...............................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................13
Worldwide Sales and Design Support .......................13
Products ....................................................................13
PSoC Solutions .........................................................13
for SMD Package ..............................................................7
Document #: 001-43258 Rev. *C
Page 2 of 13
CY25404
Figure 1. Pin Diagram - CY25404 20 LD TSSOP
VDD
1
2
CLK9
20
19
XOUT
VSS
XIN/EXCLKIN
CLK8
18
3
4
5
VSS
17 VDD_CLK_B3
16 CLK7/SSON
CLK1
CY25404
VDD_CLK_B1
CLK2
6
7
VDD_CLK_B2
15
CLK6
VSS
14
13
12
VSS
8
CLK3/FS0
OE/FS1
9
CLK5
CLK4/FS2
10
11
Table 1. Pin Definition - CY25404 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number Name IO
Description
1
VDD
Power
Power supply: 2.5 V/3.0 V/3.3 V
Crystal output
2
3
4
5
6
7
8
9
XOUT
Output
Input
XIN/EXCLKIN
VSS
Crystal Input or 1.8 V external clock input
Power supply ground
Power
CLK1
Output
Power
Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
Power supply for Bank1, (CLK1, CLK2, CLK3) outputs: 2.5 V/3.0 V/3.3 V
Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
Power supply ground
VDD_CLK_B1
CLK2
Output
Power
VSS
CLK3/FS0
Output/Input
Multifunction programmable pin: Programmable clock output or frequency select
input pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage
10
11
OE/FS1
Input
Multifunction programmable pin: High-true output enable or frequency select pin
CLK4/FS2
Output/Input
Multifunction programmable pin: Programmable clock output or frequency select
input pin. Output voltage of CLK4 depends on VDD_CLK_B2 Voltage
12
13
14
15
16
CLK5
VSS
Output
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
Power supply ground
Power
CLK6
Output
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
Power supply for Bank2, (CLK4, CLK5, CLK6) outputs: 2.5 V/3.0 V/3.3 V
VDD_CLK_B2
Power
CLK7/SSON
Output/Input
Multifunction programmable pin. Programmable clock output or spread spectrum
On/OFF control input pin. Output voltage of CLK7 depends on VDD_CLK_B3
voltage
17
18
19
20
V
DD_CLK_B3
Power
Output
Power
Output
Power supply for Bank3, (CLK7, CLK8, CLK9) outputs: 2.5 V/3.0 V/3.3 V
Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
Power supply ground
CLK8
VSS
CLK9
Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
Document #: 001-43258 Rev. *C
Page 3 of 13
CY25404
General Description
Four Configurable PLLs
Frequency Select
The CY25404 has four programmable PLLs that can be used to
generate output frequencies ranging from 3 to 166 MHz. The
advantage of having four PLLs is that a single device generates
up to four independent frequencies from a single crystal.
There are three multifunction frequency select pins (FS0, FS1
and FS2) that provide an option to select eight different sets of
frequencies among each of the four PLLs. Each output has
programmable output divider options.
Input Reference Clocks
Glitch-Free Frequency Switch
The input to the CY25404 can be either a crystal or a clock
signal. The input frequency range for crystals is 8 MHz to 48
MHz, while that for clock signals is 8 MHz to 166 MHz. The
required voltage level for the input reference clock (EXCLKIN) is
shown in the DC and AC Electrical Specification tables.
When the frequency select pin (FS) is used to switch frequency,
the outputs are glitch-free provided frequency is switched using
output dividers. This feature enables uninterrupted system
operation while clock frequency is being switched.
Output Enable Mode
V
Power Supply Options
DD
There is a multifunction programmable pin 10, OE/FS1 that can
be programmed to operate as output enable (OE) mode. OE is
a high-true input and individual clock outputs can be
programmed to be sensitive to this OE pin. If activated it shuts
off the output drivers, resulting in minimum power consumption
for the device.
This device has programmable power supply option and it can
be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V.
Output Bank Settings
There are nine clock outputs grouped in three output driver
banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1,
CLK2, CLK3), (CLK4, CLK5, CLK6), and (CLK7, CLK8, CLK9)
respectively. Separate power supplies are used for each of these
banks and they can be any of 2.5 V, 3.0 V, or 3.3 V. These
voltages are independent of VDD power supply used, giving user
multiple choice of output clock voltage levels.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 2 shows the typical rise
and fall times for different drive strength settings.
Table 2. Output Drive Strength
Output Source Selection
Rise/Fall Time (ns)
Output Drive Strength
(Typical Value)
These devices have programmable input sources for each of its
nine clock outputs (CLK1–9). There are five available clock
sources for these outputs. These clock sources are:
XIN/EXCLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock source
selection is done using four out of five crossbar switch. Thus, any
one of these five available clock sources can be arbitrarily
selected for the clock outputs. This gives user a flexibility to have
up to four independent clock outputs.
Low
Mid Low
Mid High
High
6.8
3.4
2.0
1.0
Generic Configuration and Custom Frequency
Spread Spectrum Control
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
device, CY25404 can be custom programmed to any desired
frequencies and listed features. For customer specific
programming, please contact local cypress field application
engineer (FAE) or sales representative.
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Document #: 001-43258 Rev. *C
Page 4 of 13
CY25404
Absolute Maximum Conditions
Parameter
VDD
VDD_CLK_BX
VIN
Description
Condition
Min
–0.5
–0.5
–0.5
–65
2000
–
Max
4.5
Unit
V
Supply voltage
–
–
Output bank supply voltage
Input voltage
4.5
V
Relative to VSS
VDD+0.5
+150
V
TS
Temperature, storage
ESD protection (human body model)
Flammability rating
Non functional
°C
ESDHBM
UL-94
MSL
JEDEC EIA/JESD22-A114-E
volts
ppm
V-0 at 1/8 in.
–
10
Moisture sensitivity level
3
Recommended Operating Conditions
Parameter
VDD
VDD_CLK_BX
TAC
Description
Min
Typ
–
Max
3.60
3.60
+70
+85
15
Unit
V
VDD operating voltage
2.25
2.25
0
Output driver voltage for Bank 1, 2 and 3
Commercial ambient temperature
Industrial ambient temperature
Maximum load capacitance
–
V
–
°C
°C
pF
ms
TAI
–40
–
--
CLOAD
tPU
–
Power-up time for all VDD to reach minimum specified voltage (power ramps must 0.05
be monotonic)
–
500
Notes
1. Guaranteed by design but not 100% tested.
2. Configuration dependent.
Document #: 001-43258 Rev. *C
Page 5 of 13
CY25404
DC Electrical Specifications
Parameter
VOL
Description
Output low voltage
Conditions
Min
Typ
Max
Unit
IOL = 2 mA, drive strength = [00]
–
–
0.4
V
I
I
OL = 3 mA, drive strength = [01]
OL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
IOH = –2 mA, drive strength = [00]
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
VOH
Output high voltage
VDD_CLK_BX
– 0.4
–
–
–
V
V
I
OH = –12 mA, drive strength = [11]
–
VIL1
Input low voltage of FS0, OE/FS1, FS2,
and SSON
–
0.2*VDD
VIL2
VIH1
Input low voltage of EXCLKIN
–
–
–
–
–
0.18
–
V
V
Input high voltage of FS0, OE/FS1,
FS2, and SSON
0.8*VDD
VIH2
IIL1
Input high voltage of EXCLKIN
Input low current of OE/FS1 pin
Input high current of OE/FS1 pin
–
1.62
–
–
–
–
2.2
10
10
10
V
VIL = 0V
–
–
–
µA
µA
µA
IIH1
IIL2
VIH = VDD
Input low current of SSON, FS0 and
FS2 pins
VIL = 0V (Internal pull dn = 160k typ)
IIH2
Input high current of SSON, FS0, and VIH = VDD (Internal pull dn = 160k typ)
FS2 pins
14
–
36
µA
RDN
Pull down resistor of SSON, FS0, and Clockoutputsinoff-statebysettingOE
100
160
22
250
k
FS2 and off state (CLK1-CLK9) pins
Supply current for CY25404
Input capacitance
= Low
[1,2]
IDD
CIN
OE = High, No load
–
–
–
7
mA
pF
[1]
SSON,CLKIN,FS0,OE/FS1,andFS2
pins
Document #: 001-43258 Rev. *C
Page 6 of 13
CY25404
AC Electrical Specifications
Parameter
Description
Conditions
Min
8
Typ Max Unit
F
IN (crystal)
Crystal frequency, XIN
–
–
–
48
MHz
FIN (clock)
FCLK
Input clock frequency, EXCLKIN
Output clock frequency
8
166 MHz
166 MHz
–
–
3
–
DC1
Output duty cycle, All clocks
except Ref Out
Duty cycle is defined in Figure 3 on page 8; t1/t2,
45
50
55
%
measured at 50% of VDD
_
CLK_BX
DC2
Ref out duty cycle
Output rise/fall time
Ref In Min 45%, Max 55%
40
–
–
60
–
%
[1]
TRF1
Measured from 20% to 80% of VDD
_CLK_BX, as
6.8
ns
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [00]
[1]
TRF2
Output rise/fall time
Output rise/fall time
Output rise/fall time
Measured from 20% to 80% of VDD
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [01]
_
CLK_BX, as
–
–
–
3.4
2.0
1.0
–
–
–
ns
ns
ns
[1]
TRF3
Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [10]
[1]
TRF4
Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [11]
[1,2]
TCCJ
Cycle-to-cycle jitter (peak)
PLL lock time
Configuration dependent. See Table 3
–
–
100
1
–
3
ps
[1]
TLOCK
Measured from 90% of the applied power supply
level
ms
Table 3. Configuration Example for C-C Jitter
CLK1 Output
CLK2 Output
CLK3 Output
CLK4 Output
CLK5 Output
Ref. Freq.
(MHz)
Freq.
C-C Jitter
Typ (ps)
Freq.
C-C Jitter
Typ (ps)
Freq.
C-C Jitter
Typ (ps)
Freq.
C-C Jitter
Typ (ps)
Freq.
C-C Jitter
Typ (ps)
(MHz)
(MHz)
(MHz)
(MHz)
(MHz)
14.3181
19.2
27
8.0
134
99
166
166
27
103
94
48
92
91
74.25
27
81
110
97
Not Used
74.25
48
8
48
75
67
109
123
166
166
103
137
74.25
166
Not Used
48
48
93
27
138
8
103
Recommended Crystal Specification for SMD Package
Parameter
FIN
Description
Range 1 Range 2 Range 3
Unit
MHz
Crystal frequency
Maximum motional resistance (ESR)
8 – 14
135
14 – 28 28 – 48
R1
CL
50
30
Parallelloadcapacitance(devicehas internalloadcapacitanceadjustment 8 – 18
feature)
8 – 14
8 – 12
pF
DL(max)
Maximum crystal drive level
300
300
300
µW
Recommended Crystal Specification for Thru-Hole Package
Parameter
FIN
Description
Range 1 Range 2 Range 3
Unit
MHz
Crystal frequency
8 – 14
90
14 – 24 24 – 32
R1
CL
Maximum motional resistance (ESR)
50
30
Parallel load capacitance (device has internal load capacitance
adjustment feature)
8 – 18
8 – 12
8 – 12
pF
DL(max)
Maximum crystal drive level
1000
1000
1000
µW
Document #: 001-43258 Rev. *C
Page 7 of 13
CY25404
Test and Measurement Setup
Figure 2. Test and Measurement Setup
VDD
Outputs
CLOAD
0.1 F
DUT
GND
Voltage and Timing Definitions
Figure 3. Duty Cycle Definition
t1
t2
VDD_CLK_BX
50% of V
0V
DD_CLK_BX
Clock
Output
Figure 4. Rise Time = TRF, Fall Time = TRF
TRF
TRF
V DD_CLK_BX
80% of V
DD_CLK_BX
20% of V
0V
DD_CLK_BX
Clock
Output
Document #: 001-43258 Rev. *C
Page 8 of 13
CY25404
Ordering Information
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales
representative for more information.
Possible Configurations
Part Number[3]
Type
Production Flow
Pb-free
CY25404ZXC-xxx
CY25404ZXC-xxxT
CY25404ZXI-xxx
CY25404ZXI-xxxT
20-pin TSSOP
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
20-pin TSSOP -Tape and Reel
20-pin TSSOP
20-pin TSSOP -Tape and Reel
Ordering Code Definitions
ZX C/I - xxx T
CY25404
Package Type: (T = Tape and Reel)
Customer specific identification code
Temperature code (C= Commercial or I= Industrial)
20-Pin TSSOP package
Marketing Code: CY25404 = Device Number
Note
3. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document #: 001-43258 Rev. *C
Page 9 of 13
CY25404
Package Drawing and Dimensions
Figure 5. 20-LD TSSOP, Thin Shrunk Small Outline Package (4.40 mm Body) ZZ2
51-85118 *C
Document #: 001-43258 Rev. *C
Page 10 of 13
CY25404
Acronyms
Acronym
Description
drive level
DL
EMI
electromagnetic interference
electrostatic discharge
field application engineer
frequency select
ESD
FAE
FS
JEDEC EIA
joint electron devices
engineeringcouncilelectronic
industries alliance
OE
output enable
OSC
PD
oscillator
power-down
PLL
phase-locked loop
parts per million
spread spectrum
spread spectrum clock
spread spectrum on
PPM
SS
SSC
SSON
TSSOP
thin shrunk small outline
package
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
fF
degrees Celsius
femtofarads
mA
MHz
s
milliampere
megahertz
microseconds
millisecond
microwatts
nanoseconds
picofarads
parts per million
picoseconds
volts
ms
W
ns
pF
ppm
ps
V
ohms
W
watts
Document #: 001-43258 Rev. *C
Page 11 of 13
CY25404
Document History Page
Document Title: CY25404 Quad PLL Programmable Clock Generator with Spread Spectrum
Document Number: 001-43258
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
1793805
2748211
2899300
See ECN
08/10/09
DPF/AESA New data sheet
*A
*B
TSAI
CXQ
Posting to external web.
03/26/2010
Updated Ordering Information. Added note regarding Possible Configura-
tions in Ordering Information section.
Added Possible Configurations table for “xxx’ parts.
Updated Package Drawing and Dimensions
*C
3308261
07/11/2011
BASH
Added Ordering Code Definitions
Updated Package Drawing and Dimensions
Added Acronyms
Added Units of Measure
Added Contents
Document #: 001-43258 Rev. *C
Page 12 of 13
CY25404
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-43258 Rev. *C
Revised July 11, 2011
Page 13 of 13
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