CY25814ZXC [CYPRESS]
Spread Spectrum Clock Generator; 扩频时钟发生器
| 型号： | CY25814ZXC |
| 厂家： | 
CYPRESS |
| 描述： | Spread Spectrum Clock Generator |
| 文件： | 总11页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25811/12/14
Spread Spectrum Clock Generator
Features
Applications
• 4- to 32-MHz input frequency range
• 4- to 128-MHz output frequency range
• Accepts clock, crystal, and resonator inputs
• 1x, 2x, and 4x frequency multiplication:
— CY25811: 1x; CY25812: 2x; CY25814: 4x
• Center and down spread modulation
• Low power dissipation:
• Printers and MFPs
• LCD panels
• Digital copiers
• PDAs
• CD-ROM, VCD, and DVD
• Networking, LAN/WAN
• Scanners
— 3.3V = 52 mW-typ @ 6MHz
• Modems
— 3.3V = 60 mW-typ @ 12MHz
• Embedded digital systems
— 3.3V = 72 mW-typ @ 24MHz
• Low cycle-to cycle jitter:
Benefits
• Peak EMI reduction by 8 to 16 dB
• Fast time to market
• Cost reduction
— 8 MHz = 450 ps-max
— 16 MHz = 225 ps-max
— 32 MHz = 150 ps-max
• Available in 8-pin SOIC and TSSOP packages
• Commercial and industrial temperature ranges
Block Diagram
Pin Configuration
300K
REFERENCE
DIVIDER
PD and
CP
1
8pF
LF
XIN
1
2
3
4
8
7
6
5
XIN/CLKIN
VSS
XOUT
VDD
8
8pF
XOUT
CY25811
CY25812
CY25814
VCO
COUNTE
R
MODULATION
CONTROL
VCO
FRSEL
SSCLK
S1
7
2
VDD
VSS
INPUT
DECODER
LOGIC
COUNTER
S0
and
5
MUX
SSCLK
6
3
4
8-pin SOIC/TSSOP
S0
S1
FRSEL
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07112 Rev. *E
Revised June 03, 2004
CY25811/12/14
Pin Definitions
Pin No.
Name
Xin/CLK
VSS
S1
S0
SSCLK
FRSEL
VDD
Type
Description
Crystal, ceramic resonator or clock input pin.
Power supply ground.
Digital Spread% control pin. 3-Level input (H-M-L). Default = M.
Digital Spread% control pin. 3-Level input (H-M-L). Default = M.
Spread Spectrum output clock.
Input frequency range selection digital control input. 3-Level input (H-M-L). Default = M.
Positive power supply.
1
2
3
4
5
6
7
8
XOUT
Crystal or ceramic resonator output pin.
Spread % for each Spread Mode with the option of a
Non-Spread mode for system test and verification purposes.
Functional Description
The CY25811/12/14 products are Spread Spectrum Clock
Generator (SSCG) ICs used for the purpose of reducing
electromagnetic interference (EMI) found in today’s
high-speed digital electronic systems.
The devices use a Cypress proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the
fundamental and harmonic frequencies is greatly reduced.
The CY25811/12/14 products are available in an 8-pin SOIC
(150-mil.) package with a Commercial operating temperature
range of 0 to 70°C and Industrial Temperature range of –40 to
85°C. Refer to CY25568 for multiple clock output options such
as modulated and unmodulated clock outputs or Power-down
function.
For
Automotive
applications,
refer
to
CY25811/12/14SE data sheet.
Input Frequency Range and Selection
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements and
improve time to market without degrading system perfor-
mance.
The input frequency range is 4 to 32 MHz and accepts clock,
crystal and ceramic resonator inputs. The output clock can be
selected to produce 1x, 2x, or 4x multiplication of the input
frequency with Spread Spectrum Frequency Modulation.
The use of 2x or 4x frequency multiplication eliminates the
need for higher order crystals and enables the user to
generate up to 128-MHz Spread Spectrum Clock (SSC) by
using only first order crystals. This will reduce the cost while
improving the system clock accuracy, performance and
complexity.
The CY25811/12/14 input frequency range is 4 to 32 MHz.
This range is divided into three segments and controlled by
3-Level FRSEL pin as given in Table 1.
Table 1. Input Frequency Selection
FRSEL
Input Frequency Range
4.0 to 8.0 MHz
0
1
8.0 to 16.0 MHz
M
16.0 to 32.0 MHz
Spread% Selection
The CY25811/12/14 SSCG products provide Center-Spread,
Down-Spread and No-Spread functions. The amount of
Spread% is selected by using 3-Level S0 and S1 digital inputs
and Spread% values are given in Table 2.
Center Spread or Down Spread frequency modulation can be
selected by the user based on four discrete values of
Table 2. Spread% Selection
XIN
S1 = 0
S1 = 0
S0 = M
S1 = 0
S0 = 1
S1 = M
S0 = 0
S1 = 1
S0 = 1
S1 = 1
S0 = 0
S1 = M
S0 = 1
S1 = 1
S0 = M
S1 = M
S0 = M
(MHz)
FRSEL
S0 = 0
Center
(%)
Center
Center
Center
Down
Down
Down
Down
(%)
(%)
(%)
(%)
(%)
(%)
(%)
No Spread
4-5
5-6
6-7
0
0
0
0
1
1
1
1
M
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
±1.4
± 1.2
± 1.1
± 0.9
± 0.9
±1.2
±1.1
± 0.9
± 0.9
±1.2
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
–3.0
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
–1.9
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
–0.7
0
0
0
0
0
0
0
0
0
7-8
8-10
10-12
12-14
14-16
16-20
Document #: 38-07112 Rev. *E
Page 2 of 11
CY25811/12/14
Table 2. Spread% Selection (continued)
XIN
S1 = 0
S1 = 0
S1 = 0
S0 = 1
S1 = M
S0 = 0
S1 = 1
S0 = 1
S1 = 1
S0 = 0
S1 = M
S0 = 1
S1 = 1
S0 = M
S1 = M
S0 = M
(MHz)
FRSEL
S0 = 0
S0 = M
20-24
24-28
28-32
M
M
M
±1.3
±1.2
±1.1
±1.1
± 0.9
± 0.9
± 0.5
± 0.5
± 0.4
± 0.4
± 0.4
± 0.3
–2.7
–2.5
–2.3
–1.9
–1.8
–1.7
–1.7
–1.5
–1.4
–0.6
–0.6
–0.5
0
0
0
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0” and
Middle “M”. With this 3-Level digital input logic, the 3-Level
Logic is able to detect 9 different logic states.
S0, S1 and FRSEL pins include an on chip 20K (10K/10K)
resistor divider. No external application resistors are needed
to implement the 3-Level logic levels as shown below:
Logic Level “0”: 3–Level logic pin connected to GND.
Logic Level “M”: 3–Level logic pin left floating (no connection).
Logic Level “1”: 3–Level logic pin connected to VDD
.
Figure 1 illustrates how to implement 3–Level Logic.
LOGIC
LOGIC
LOGIC
MIDDLE (M)
LOW (0)
HIGH (H)
S0, S1
and
S0, S1
and
S0, S1
and
FRSEL
FRSEL
to VSS
FRSEL
to VDD
UNCONNECTED
VSS
Figure 1. 3–Level Logic
Modulation Rate
Table 3. Modulation Rate Divider Ratios
Input Frequency Range
Divider Ratio
(DR)
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax) and
minimum frequency of the clock (fmin) determine this band of
frequencies. The time required to transition from fmin to fmax
and back to fmin is the period of the Modulation Rate. The
Modulation Rate of SSCG clocks are generally referred to in
terms of frequency, or
FRSEL
(MHz)
4 to 8
0
128
256
512
1
M
8 to 16
16 to 32
Input and Output Frequency Selection
fmod = 1/Tmod.
The relationship between input frequency versus output
frequency in terms of device selection and FRSEL setting is
given in Table 4. As shown, the input frequency range is
selected by FRSEL and is the same for CY25811, CY25812,
and CY25814. The selection of CY25811 (1x), CY25812 (2x)
or CY25814 (4x) determines the frequency multiplication at
the output (SSCLK, Pin 5) with respect to input frequency
(XIN, Pin-1).
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
In the case of CY25811/2/4 devices, the (Spread Spectrum)
modulation Rate, fmod, is given by the following formula:
fmod = fin/DR
where; fmod is the Modulation Rate, fin is the Input Frequency
and DR is the Divider Ratio as given in Table 3. Notice that
Input Frequency Range is set by FRSEL.
Document #: 38-07112 Rev. *E
Page 3 of 11
CY25811/12/14
Table 4. Input and Output Frequency Selection
Input Frequency Range
Output Frequency Range
(MHz)
(MHz)
4 to 8
FRSEL
Product
CY25811
CY25811
CY25811
CY25812
CY25812
CY25812
CY25814
CY25814
CY25814
Multiplication
0
1x
1x
1x
2x
2x
2x
4x
4x
4x
4 to 8
8 to 16
16 to 32
8 to 16
16 to 32
32 to 64
16 to 32
32 to 64
64 to 128
8 to 16
16 to 32
4 to 8
1
M
0
8 to 16
16 to 32
4 to 8
1
M
0
8 to 16
16 to 32
1
M
Absolute Maximum Conditions (both Commercial and Industrial Grades)[1,2]
Parameter
VDD
VIN
TS
TA1
TA2
TJ
Description
Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Operating Ambient
Temperature, Junction
Condition
Min.
–0.5
–0.5
–65
0
Max.
4.6
VDD + 0.5
150
Unit
V
VDC
°C
°C
°C
Relative to V SS
Non Functional
Functional, C-Grade
Functional, I-Grade
Functional
70
85
150
–40
–
°C
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
V
Flammability Rating
@1/8 in.
V–0
1
Moisture Sensitivity Level
DC Electrical Specifications (Commercial Grade)
Parameter
VDD
Description
3.3 Operating Voltage
Condition
Min.
3.135
Max.
3.465
Unit
V
3.3 ± 5%
VIL
VIM
VIH
VOL1
VOL2
VOH1
VOH2
CIN1
CIN2
CL
Input Low Voltage
Input Middle Voltage
Input High Voltage
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
IOL = 4 ma, SSCLK Output
IOL = 10 ma, SSCLK Output
IOH = 4 ma, SSCLK Output
IOH = 6 ma, SSCLK Output
XIN (Pin 1) and XOUT (Pin 8)
All Digital Inputs
0
0.15VDD
V
V
V
V
V
V
V
pF
pF
pF
mA
mA
mA
0.40VDD 0.60VDD
0.85VDD
VDD
0.4
1.2
–
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Input Pin Capacitance
Input Pin Capacitance
Output Load Capacitor
Dynamic Supply Current
Dynamic Supply Current
Dynamic Supply Current
–
–
2.4
2.0
6.0
3.5
–
–
–
–
–
9.0
6.0
15
25
30
35
SSCLK Output
IDD1
IDD2
IDD3
Fin = 12 MHz, no load
Fin = 24 MHz, no load
Fin = 32 MHz, no load
Notes:
1. Operation at any Absolute Maximum Rating is not implied.
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
Document #: 38-07112 Rev. *E
Page 4 of 11
CY25811/12/14
AC Electrical Specifications (Commercial Grade)
Parameter
FIN
TR1
TF1
TR2
TF2
TDCIN
TDCOUT
TCCJ1
TCCJ2
TCCJ3
TCCJ4
TCCJ5
TCCJ6
TSU
Description
Input Frequency Range
Clock Rise Time
Clock Fall Time
Clock Rise Time
Condition
Min.
4
Max.
32
Unit
MHz
ns
ns
ns
ns
%
%
ps
ps
ps
ps
ps
ps
ms
Clock, Crystal or Ceramic Resonator Input
SSCLK, CY25811 and CY25812
SSCLK, CY25811 and CY25812
SSCLK, only CY25814 when FRSEL = M
SSCLK, only CY25814 when FRSEL = M
XIN
2.0
2.0
1.0
1.0
40
40
–
–
–
–
–
5.0
4.4
2.2
2.2
60
Clock Fall Time
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
PLL Lock Time
SSCLK
60
Fin = 4 MHz, Fout = 4 MHz, CY25811
Fin = 8 MHZ, Fout = 8 MHz, CY25811
Fin = 8 MHz, Fout = 16 MHz, CY25812
Fin = 16 MHz, Fout = 32 MHz, CY25812
Fin = 16 MHz, Fout = 64 MHz, CY25814
Fin = 32 MHz, Fout = 128 MHz, CY25814
Fom VDD 3.0V to valid SSCLK
800
450
400
380
380
380
3
–
–
DC Electrical Specifications (Industrial Grade)
Parameter
VDD
VIL
VIM
Description
3.3 Operating Voltage
Input Low Voltage
Input Middle Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Input Pin Capacitance
Input Pin Capacitance
Output Load Capacitor
Dynamic Supply Current
Dynamic Supply Current
Dynamic Supply Current
Condition
Min.
3.135
0
0.40VDD 0.60VDD
0.85VDD
Max.
3.465
0.13VDD
Unit
V
V
V
V
V
V
V
V
pF
pF
pF
mA
mA
mA
3.3 ± 5%
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
IOL = 4 ma, SSCLK Output
IOL = 10 ma, SSCLK Output
IOH = 4 ma, SSCLK Output
IOH = 6 ma, SSCLK Output
XIN (Pin 1) and XOUT (Pin 8)
All Digital Inputs
VIH
VDD
0.4
1.2
–
VOL1
VOL2
VOH1
VOH2
CIN1
CIN2
CL
IDD1
IDD2
IDD3
–
–
2.4
2.0
6.0
3.5
–
–
–
–
–
9.0
6.0
15
26
32
37
SSCLK Output
Fin = 12 MHz, no load
Fin = 24 MHz, no load
Fin = 32 MHz, no load
AC Electrical Specifications (Industrial Grade)
Parameter
FIN
TR1
TF1
TR2
TF2
TDCIN
TDCOUT
TCCJ1
TCCJ2
TCCJ3
TSU
Description
Input Frequency Range
Clock Rise Time
Clock Fall Time
Clock Rise Time
Condition
Clock, Crystal or Ceramic Resonator Input
SSCLK, CY25811 and CY25812
SSCLK, CY25811 and CY25812
SSCLK, only CY25814 when FRSEL = M
SSCLK, only CY25814 when FRSEL = M
XIN
Min.
4
Max.
32
Unit
MHz
ns
ns
ns
ns
%
%
ps
2.0
2.0
1.0
1.0
40
40
–
–
–
–
5.0
4.4
2.2
2.2
60
Clock Fall Time
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
PLL Lock Time
SSCLK
60
Fin = 6MHz, CY25811/12/14
Fin = 12MHZ, CY25811/12/14
Fin = 24MHz, CY25811/12/14
From VDD 3.0V to valid SSCLK
650
400
400
4
ps
ps
ms
Document #: 38-07112 Rev. *E
Page 5 of 11
CY25811/12/14
Characteristic Curves
The following curves demonstrate the characteristic behavior
of the CY25811/12/14 when tested over a number of environ-
mental and application-specific parameters. These are typical
performance curves and are not meant to replace any
parameter specified in DC and AC Specification tables.
600
500
400
300
200
100
0
2.75
2.5
6.0 MHz
32.0 MHz
2.25
2
1.75
4
8
12
16
20
24
28
32
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temp (C)
Input Frequency (MHz)
Jitter vs. Input Frequency (No Load)
Bandwidth % vs. Temperature
30
28
26
24
22
20
18
16
14
12
10
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
FRSEL = M
16 - 32 MHz
4.0 MHz
FRSEL = 1
8 - 16 MHz
8.0 MHz
FRSEL = 0
4 - 8 MHz
1.9
1.8
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
4.5
5
5.5
6
6.5
7
7.5
8
Frequency (MHz), no load, normalized to FRSEL = 0, (4 - 8 MHz).
VDD (volts)
IDD vs. Frequency (FRSEL = 0, 1, M)
Bandwidth % vs. VDD
Figure 2. Characteristic Curves
Document #: 38-07112 Rev. *E
Page 6 of 11
CY25811/12/14
SSCG Profiles
CY25811/12/14 SSCG products use a non-linear “optimized”
frequency profile as shown In Figure 3. The use of Cypress
proprietary “optimized” frequency profile maintains flat energy
distribution over the fundamental and higher order harmonics.
This results in additional EMI reduction in electronic systems.
Xin = 6.0 MHz
S1, S0 = 0
SSCLK1 = 6.0 MHz
P/N = CY25811
Xin = 24.0 MHz
S1, S0 = 0
SSCLK1 = 24.0 MHz
P/N = CY25811
FRSEL = 0
FRSEL = M
Xin = 24.0 MHz
S1, S0 = 0
SSCLK1 = 96.0 MHz
P/N = CY25814
Xin = 12.0 MHz
S1, S0 = 0
SSCLK1 = 48.0 MHz
P/N = CY25814
FRSEL = M
FRSEL = 1
Figure 3. Spread Spectrum Profiles (Frequency vs. Time)
Document #: 38-07112 Rev. *E
Page 7 of 11
CY25811/12/14
Application Schematic
VDD
C3
0.1 uF
7
C2
VDD
1
XIN
25 MHz (CY25811)
50 MHz (CY25812)
100 MHz (CY25814)
5
27 pF
C3
SSCLK
Y1
25 MHz
8
XOUT
27 pF
CY25811
CY25812
CY25814
3
4
S1
S0
6
N/C
FRSEL
VSS
2
Ordering Information
Part Number
Package Type
Product Flow
CY25811SC
CY25811SCT
CY25811SI
CY25811SIT
CY25811ZC
CY25811ZCT
CY25812SC
CY25812SCT
CY25812SI
CY25812SIT
CY25812ZC
CY25812ZCT
CY25814SC
CY25814SCT
CY25814SI
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin TSSOP
8-pin TSSOP – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin TSSOP
8-pin TSSOP – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin SOIC
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
CY25814SIT
CY25814ZC
8-pin SOIC – Tape and Reel
8-pin TSSOP
8-pin TSSOP – Tape and Reel
CY25814ZCT
Lead Free Devices
CY25811SXC
CY25811SXCT
CY25811SXI
CY25811SXIT
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin SOIC
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
8-pin SOIC – Tape and Reel
Document #: 38-07112 Rev. *E
Page 8 of 11
CY25811/12/14
Ordering Information (continued)
CY25811ZXC
CY25811ZXCT
CY25812SXC
CY25812SXCT
CY25812SXI
CY25812SXIT
CY25812ZXC
CY25812ZXCT
CY25814SXC
CY25814SXCT
CY25814SXI
8-pin TSSOP
8-pin TSSOP – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin TSSOP
8-pin TSSOP – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin SOIC
8-pin SOIC – Tape and Reel
8-pin TSSOP
8-pin TSSOP – Tape and Reel
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
CY25814SXIT
CY25814ZXC
CY25814ZXCT
Package Drawing and Dimensions
8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
51-85066-*C
0.0138[0.350]
0.0192[0.487]
Document #: 38-07112 Rev. *E
Page 9 of 11
CY25811/12/14
8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
2.90[0.114]
3.10[0.122]
51-85093-*A
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07112 Rev. *E
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY25811/12/14
Document History Page
Document Title: CY25811/12/14 Spread Spectrum Clock Generator
Document Number: 38-07112
Issue
Date
Orig. of
Change
REV. ECN NO.
Description of Change
**
*A
*B
107516 06/14/02
108002 06/29/02
121578 01/29/03
NDP Converted from IMI to Cypress
NDP Deleted Junction Temp. in Absolute Maximum Ratings
RGL Converted from Word to FrameMaker
Added 8-pin TSSOP package in Commercial Temp. only
Added an Industrial Temperature Range to all existing 8-pin SOIC packages
*C
*D
*E
125550 05/14/03
131941 12/24/03
231057 See ECN
RGL Changed IDD values from 19.6/22/27.2 to 25/30/35 in Commercial Grade DC Specs
table
Changed IDD values from 24/26.5/33 to 26/32/37 in Industrial grade DC Specs table
Changed TCCJ1/2 values from 675/260 to 800/450 in Commercial grade AC Specs table
Changed TCCJ1 value from 350 to 650 in Industrial grade AC Specs table
RGL Removed automotive in the Applications section
Changed the Output Clock Duty Cycle (TDCOUT) from min. 45 and max. 55 to 40 and
60% respectively for both industrial and commercial grade
Changed the min. Input Low Voltage (VIL) from 0.15VDD to 0.13VDD
Removed preliminary from the industrial AC/DC Electrical Specifications table
RGL Added Lead Free Devices
Document #: 38-07112 Rev. *E
Page 11 of 11
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