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CY26121ZC

更新时间：2024-09-18 01:52:56
品牌：CYPRESS
描述：PacketClock Spread Spectrum Clock Generator

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CY26121ZC 概述

PacketClock Spread Spectrum Clock Generator PacketClock扩频时钟发生器 时钟发生器

CY26121ZC 规格参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：4.40 MM, TSSOP-16
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.85JESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：5 mm
端子数量：16最高工作温度：70 °C
最低工作温度：最大输出时钟频率：66.66 MHz
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V主时钟/晶体标称频率：25 MHz
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Clock Generators最大压摆率：60 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

CY26121ZC 数据手册

通过下载CY26121ZC数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

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CY26121  
PacketClock™Spread SpectrumClockGenerator  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
High-performance PLL tailored for Spread Spectrum appli-  
cation  
• Low jitter, high-accuracy outputs  
Meets critical timing requirements in complex system  
designs  
• 3.3V operation  
Enables application compatibility  
• 25-MHz input frequency  
Works with commonly available crystal or driven reference  
• 66.66-MHz or 33.33-MHz selectable output frequency  
(orig, -3,-11,-31)  
Downspread Spread Spectrum with 30-kHz nominal  
modulation frequency  
• 33.33-MHz or 25-MHz selectable output frequency  
(-2,-21)  
Frequency Table for CLKA-D  
Part Number  
CY26121  
CLKSEL=0  
66.66 MHz  
33.33 MHz  
66.66 MHz  
66.66 MHz  
33.33 MHz  
66.66 MHz  
CLKSEL=1  
33.33  
Spread%  
–2.8%  
–2.8%  
–1.4%  
–2.8%  
–2.8%  
–1.4%  
Parallel Crystal Load  
6 pF  
CY26121-2  
CY26121-3  
CY26121-11  
CY26121-21  
CY26121-31  
25.00  
6 pF  
33.33  
6 pF  
33.33  
15 pF  
15 pF  
15 pF  
25.00  
33.33  
Logic Block Diagram  
VDDL  
25 MHz XIN  
XOUT  
PLL  
OSC.  
CLKA  
CLKB  
with  
Modulation Control  
SSON  
CLKC  
CLKD  
OUTPUT  
MULTIPLEXER  
AND  
Flash Configuration  
DIVIDERS  
VSSL  
CLKSEL  
REF  
VDD AVDD AVSS VSS  
CY26121  
16-pin TSSOP  
Pin Configuration  
XOUT  
1
XIN  
16  
V
15  
14  
13  
12  
11  
10  
NC  
2
3
4
5
6
7
8
DD  
REF  
AVDD  
CLKSEL  
AVSS  
VSS  
CLKD  
VDDL  
VSSL  
CLKA  
CLKB  
SSON  
CLKC  
9
Cypress Semiconductor Corporation  
Document #: 38-07350 Rev. **  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised February 11, 2003  
CY26121  
Pin Description  
Name  
Pin Number  
Description  
XIN  
1
2
3
Reference input or crystal input  
3.3V voltage supply  
VDD  
AVDD  
CLKSEL  
CLKSEL  
AVSS  
VSSL  
CLK(A:D)  
SSON  
VDDL  
VSS  
3.3V analog voltage  
4 (orig., -11,-3,-31)  
0 = 66.66MHz out, 1 = 33.33 MHz out. Weak pull-up.  
0 = 33.33MHz out, 1 = 25 MHz out. Weak pull-up.  
Analog ground  
4 (-2, -21)  
5
6
CLK ground  
7,8,9,12  
10  
Clock outputs at VDDL level  
Spread Spectrum enable pin 0 = SS off; 1 = SS on. Weak pull-up.  
3.3V clock voltage supply  
Ground  
11  
13  
REF  
14  
Reference output at VDD level  
No Connect  
NC  
15  
XOUT[1]  
16  
Crystal Output  
Data Retention @ Tj = 125°C................................> 10 years  
Absolute Maximum Conditions  
Package Power Dissipation...................................... 350 mW  
Supply Voltage (VDD, AVDD, VDDL) ...................–0.5 to +7.0V  
DC Input Voltage...................................... –0.5V to VDD + 0.5  
Static Discharge Voltage.......................................... > 2000V  
(per MIL-STD-883, Method 3015)  
Storage Temperature  
(Non-condensing) .......................................–55°C to +125°C  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Junction Temperature ................................ –40°C to +125°C  
Recommended Operating Conditions  
Parameter  
VDD, AVDD  
Description  
Min.  
3.135  
3.135  
0
Typ.  
3.30  
3.30  
Max.  
3.465  
3.465  
70  
Unit  
V
Supply voltage  
VDDL  
TA  
Supply voltage for CLK (A-D)  
V
Ambient temperature (commercial temp. grade)  
Ambient Temperature (industrial temp grade)  
Max. output load capacitance  
° C  
° C  
pF  
TA  
-40  
85  
CLOAD  
Fref  
15  
Reference frequency  
25  
MHz  
Crystal Specification[2]  
Parameter  
Name  
Min.  
Typ  
6
Max.  
Unit  
pF  
pF  
Ω
CRload  
CRload  
Crystal load capacitance (original, -2, -3)  
Crystal load capacitance (-11,-21,-31)  
Equivalent series resistance  
15  
ESR  
50  
Notes:  
1. Float XOUT if XIN is externally driven.  
2. A fundamental parallel resonant crystal must be used  
Document #: 38-07350 Rev. **  
Page 2 of 6  
CY26121  
DC Electrical Specifications  
Parameter  
Description  
Output High Current  
Output Low Current  
Input High Current  
Input Low Current  
Input High Voltage  
Input Low Voltage  
Input Capacitance  
Condition  
VOH = VDD – 0.5, VDD/VDDL=3.3V  
VOL = 0.5, VDD/VDDL = 3.3V  
VIH = VDD  
Min.  
12  
Typ.  
24  
24  
5
Max.  
Unit  
mA  
mA  
µA  
IOH  
IOL  
IIH  
12  
10  
50  
IIL  
VIL = 0V  
µA  
VIH  
CMOS levels  
0.7  
80  
VDD  
VDD  
pF  
VIL  
CMOS levels  
0.3  
7
[3]  
CIN  
Input pins excluding XIN  
[3]  
RUP  
Pull-up resistor on input pins VDD = 3.14 to 3.47V, measured at VIN = 0V  
100  
42  
150  
60  
kΩ  
IDD  
Supply Current  
AVDD/VDD/VDDL Current.  
mA  
AC Electrical Specifications[3]  
Parameter  
DC  
Description  
Output Duty Cycle  
Rising Edge Rate  
Condition  
Min.  
Typ.  
Max.  
Unit  
%
Duty Cycle is defined in Figure 1, 50% of VDD  
45  
50  
55  
ER  
Output Clock Edge Rate, Measured from 20%  
0.8  
1.4  
V/ns  
to 80% of VDD, CLOAD = 15 pF See Figure 2.  
EF  
tj  
Falling Edge Rate  
Output Clock Edge Rate, Measured from 80%  
to 20% of VDD, CLOAD = 15 pF See Figure 2.  
0.8  
1.4  
15  
V/ns  
ps  
RMS Clock Cycle-to-Cycle  
Jitter  
RMS cycle-to-cycle jitter with Spread on.  
Measured at VDD/2.  
40  
Voltage and Timing Definitions  
t1  
t2  
VDD  
50% of VDD  
0V  
Clock  
Output  
Figure 1. Duty Cycle Definition  
t4  
t3  
V DD  
80% of VDD  
20% of VDD  
0V  
Clock  
Output  
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4  
Notes:  
3. Guaranteed by Characterization, not 100% tested.  
Document #: 38-07350 Rev. **  
Page 3 of 6  
CY26121  
Ordering Information  
Ordering Code  
CY26121ZC  
Package Type  
Operating Range  
16-pin TSSOP  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
Industrial, –40°C to 85°C  
Industrial, –40°C to 85°C  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
Industrial, –40°C to 85°C  
Industrial, –40°C to 85°C  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
Industrial, –40°C to 85°C  
Industrial, –40°C to 85°C  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
Industrial, –40°C to 85°C  
Industrial, –40°C to 85°C  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
Industrial, –40°C to 85°C  
Industrial, –40°C to 85°C  
Commercial, 0°C to 70°C  
Commercial, 0°C to 70°C  
Industrial, –40°C to 85°C  
Industrial, –40°C to 85°C  
CY26121ZCT  
CY26121ZI  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
CY26121ZIT  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
CY26121ZC-2  
CY26121ZC-2T  
CY26121ZI-2  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
CY26121ZI-2T  
CY26121ZC-3  
CY26121ZC-3T  
CY26121ZI-3  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
CY26121ZI-3T  
CY26121ZC-11  
CY26121ZC-11T  
CY26121ZI-11  
CY26121ZI-11T  
CY26121ZC-21  
CY26121ZC-21T  
CY26121ZI-21  
CY26121ZI-21T  
CY26121ZC-31  
CY26121ZC-31T  
CY26121ZI-31  
CY26121ZI-31T  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
16-pin TSSOP – Tape and Reel  
16-pin TSSOP  
16-pin TSSOP – Tape and Reel  
Document #: 38-07350 Rev. **  
Page 4 of 6  
CY26121  
Package Drawing and Dimensions  
16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16  
51-85091-**  
Inches  
Millimeters  
Parameter  
Min.  
–
Nom.  
Max.  
0.047  
0.006  
0.041  
0.012  
0.008  
0.201  
0.177  
Min.  
–
Nom.  
Max.  
1.20  
0.15  
1.05  
0.30  
0.20  
5.10  
4.50  
A
–
–
A
0.002  
0.031  
0.007  
0.004  
0.193  
0.169  
–
0.05  
0.80  
0.19  
0.09  
4.90  
4.30  
–
1.00  
–
1
A2  
B
C
D
E
e
0.039  
–
–
–
0.197  
0.173  
0.026 BSC  
0.252  
0.024  
–
5.00  
4.40  
0.65 BSC  
6.40  
0.60  
–
H
L
0.244  
0.018  
0°  
0.260  
0.030  
8°  
6.20  
0.45  
0°  
6.60  
0.75  
8°  
a
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-07350 Rev. **  
Page 5 of 6  
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CY26121  
Document History Page  
Document Title: CY26121 PacketClock™ Spread Spectrum Clock Generator  
Document Number: 38-07350  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
121669  
02/11/03  
CKN  
New Data Sheet  
Document #: 38-07350 Rev. **  
Page 6 of 6  

CY26121ZC 相关器件

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CY26121ZC-2T CYPRESS PacketClock Spread Spectrum Clock Generator 获取价格
CY26121ZC-3 CYPRESS PacketClock Spread Spectrum Clock Generator 获取价格
CY26121ZC-31 CYPRESS PacketClock Spread Spectrum Clock Generator 获取价格
CY26121ZC-31T CYPRESS PacketClock Spread Spectrum Clock Generator 获取价格
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