CY29351_08 [CYPRESS]
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay; 2.5V或3.3V ， 200 MHz时， 9路输出零延迟
| 型号： | CY29351_08 |
| 厂家： | 
CYPRESS |
| 描述： | 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay |
| 文件： | 总10页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY29351
2.5V or 3.3V, 200 MHz,
9-Output Zero Delay
Features
Functional Description
■ Output frequency range: 25 MHz to 200 MHz
■ Input frequency range: 25 MHz to 200 MHz
■ 2.5V or 3.3V operation
The CY29351 is a low voltage high performance 200 MHz
PLL-based zero delay buffer designed for high speed clock distri-
bution applications.
The CY29351 features LVPECL and LVCMOS reference clock
inputs and provides 9 outputs partitioned in four banks of one,
one, two, and five outputs. Bank A divides the VCO output by two
or four while the other banks divide by four or eight per SEL(A:D)
settings (Table 3, “Function Table,” on page 3). These dividers
allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each
LVCMOS compatible output can drive 50Ω series or parallel
terminated transmission lines. For series terminated trans-
mission lines, each output can drive one or two traces giving the
device an effective fanout of 1:18.
■ Split 2.5V/3.3V outputs
■ ±2.5% max Output duty cycle variation
■ 9 clock outputs: Drive up to 18 clock lines
■ Two reference clock inputs: LVPECL or LVCMOS
■ 150-ps max output-output skew
■ Phase-locked loop (PLL) bypass mode
■ Spread Aware™
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 25 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider (Table 2,
“Frequency Table,” on page 3).
■ Output enable/disable
■ Pin-compatible with MPC9351
■ Industrial temperature range: –40°C to +85°C
■ 32-pin 1.0-mm TQFP package
When PLL_EN# is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
VCO
200 -
500 MHz
Phase
Detector
QA
QB
÷2 / ÷4
÷4 / ÷8
PECL_CLK
LPF
FB_IN
SELB
QC0
QC1
÷4 / ÷8
÷4 / ÷8
SELC
OE#
QD0
QD1
SELD
QD2
QD3
QD4
Cypress Semiconductor Corporation
Document Number: 38-07475 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 21, 2008
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PRELIMINARY
CY29351
Pinouts
Figure 1. Pin Diagram - 32 Pin TQFP Package
AVDD
FB_IN
SELA
SELB
SELC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QC0
VDDQC
QC1
VSS
QD0
VDDQD
QD1
VSS
CY29351
SELD
AVSS
PECL_CLK
Table 1. Pin Definitions - 32 Pin TQFP Package
Pin[1]
Name
IO
Type
Description
8
PECL_CLK
I, PU
LVPECL LVPECL reference clock input
9
PECL_CLK# I, PU/PD LVPECL LVPECL reference clock input. Weak pull up to VDD/2.
30
28
26
TCLK
QA
I, PD
O
LVCMOS LVCMOS/LVTTL reference clock input
LVCMOS Clock output bank A
QB
O
LVCMOS Clock output bank B
22, 24
QC(1,0)
O
LVCMOS Clock output bank C
12, 14, 16, 18, 20 QD(4:0)
O
LVCMOS Clock output bank D
2
FB_IN
I, PD
LVCMOS Feedback clock input. Connect to an output for normal operation. This
input should be at the same voltage rail as input reference clock
10
OE#
I, PD
I, PU
LVCMOS Output enable/disable input
LVCMOS PLL enable/disable input
LVCMOS Reference select input
31
PLL_EN
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
32
I, PD
3, 4, 5, 6
I, PD
LVCMOS Frequency select input, bank (A:D)
27
23
15, 19
1
Supply
Supply
Supply
Supply
Supply
Supply
Supply
VDD
VDD
VDD
VDD
VDD
2.5V or 3.3V power supply for bank B output clock[2,3]
2.5V or 3.3V power supply for bank C output clocks[2,3]
2.5V or 3.3V power supply for bank D output clocks[2,3]
2.5V or 3.3V power supply for PLL[5,6]
11
VDD
2.5V or 3.3V power supply for core, inputs, and bank A output clock[2,3]
7
AVSS
Ground Analog ground
Ground Common ground
13, 17, 21, 25, 29 VSS
Notes
1. PU = Internal pull up, PD = Internal pull down.
2. A 0.1-μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, the
high-frequency filtering characteristics are cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins.
4.
V
(DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the V
range and the input swing
CMR
CMR
is within the V (DC) specification.
PP
5. Driving one 50Ω parallel terminated transmission line to a termination voltage of V . Alternatively, each output drives up to two 50Ω series terminated transmission
TT
lines.
6. Inputs have pull up or pull down resistors that affect the input current.
Document Number: 38-07475 Rev. *B
Page 2 of 10
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PRELIMINARY
CY29351
Table 2. Frequency Table
Feedback Output Divider
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
VCO
(AVDD = 2.5V)
100 MHz to 190 MHz
50 MHz to 95 MHz
÷2
÷4
÷8
Input Clock * 2
Input Clock * 4
Input Clock * 8
100 MHz to 200 MHz
50 MHz to 125 MHz
25 MHz to 62.5 MHz
25 MHz to 47.5 MHz
Table 3. Function Table
Control
REF_SEL
PLL_EN
Default
0
1
0
1
PCLK
TCLK
Bypass mode, PLL disabled. The input clock PLL enabled. The VCO output connects to the output
connects to the output dividers
Outputs enabled
dividers
OE#
0
Outputs disabled (three-state), VCO running at its
minimum frequency
SELA
SELB
SELC
SELD
0
0
0
0
÷ 2 (bank A)
÷ 4 (bank B)
÷ 4 (bank C)
÷ 4 (bank D)
÷ 4 (bank A)
÷ 8 (bank B)
÷ 8 (bank C)
÷ 8 (bank D)
Absolute Maximum Conditions
Parameter
VDD
VDD
VIN
Description
DC supply voltage
Condition
Functional
Min
–0.3
2.375
–0.3
–0.3
–
Max
5.5
Unit
V
DC operating voltage
3.465
VDD + 0.3
VDD + 0.3
VDD ÷ 2
–
V
DC input voltage
Relative to VSS
Relative to VSS
V
VOUT
VTT
DC output voltage
V
Output termination voltage
Latch-up immunity
V
LU
Functional
200
–
mA
mVp-p
°C
RPS
TS
Power supply ripple
Ripple frequency < 100 kHz
Non Functional
Functional
150
Temperature, storage
Temperature, operating ambient
Temperature, junction
Dissipation, junction to case
Dissipation, junction to ambient
ESD protection (human body model)
Failure in time
–65
–40
–
+150
TA
+85
°C
TJ
Functional
+150
°C
ØJC
ØJA
ESDH
FIT
Functional
42
°C/W
°C/W
Volts
ppm
Functional
105
2000
–
Manufacturing test
10
Document Number: 38-07475 Rev. *B
Page 3 of 10
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PRELIMINARY
CY29351
DC Electrical Specifications
(V = 2.5V ± 5%, T = –40°C to +85°C)
DD
A
Parameter
VIL
Description
Condition
LVCMOS
Min
–
Typ.
–
Max
Unit
Input voltage, low
0.7
V
VIH
Input voltage, high
LVCMOS
1.7
250
1.0
–
–
VDD+0.3
V
mV
V
VPP
VCMR
VOL
VOH
IIL
Peak-Peak input voltage
Common mode range[4]
Output voltage, low[5]
Output voltage, high[5]
Input current, low[6]
LVPECL
–
1000
LVPECL
–
VDD – 0.6
IOL = 15mA
–
0.6
–
V
IOH = –15mA
1.8
–
–
V
VIL = VSS
–
–100
100
10
7
μA
μA
mA
mA
mA
IIH
Input current, high[6]
VIL = VDD
–
–
IDDA
IDDQ
IDD
PLL supply current
AVDD only
–
5
Quiescent supply current
Dynamic supply current
All VDD pins except AVDD
Outputs loaded at 100 MHz
Outputs loaded at 200 MHz
–
–
–
180
210
4
–
–
–
CIN
Input pin capacitance
Output impedance
–
–
pF
ZOUT
14
18
22
Ω
DC Electrical Specifications
(V = 3.3V ± 5%, T = –40°C to +85°C)
DD
A
Parameter
VIL
Description
Condition
LVCMOS
Min
–
Typ.
–
Max
Unit
V
Input voltage, low
0.8
VIH
Input voltage, high
LVCMOS
2.0
250
1.0
–
–
VDD + 0.3
V
VPP
Peak-Peak input voltage
Common mode range[4]
Output Voltage, Low[5]
LVPECL
–
1000
mV
V
VCMR
VOL
LVPECL
–
VDD – 0.6
IOL = 24 mA
–
0.55
0.30
–
V
I
OL = 12 mA
–
–
VOH
IIL
Output voltage, high[5]
Input current, low[6]
Input current, high[6]
IOH = –24 mA
2.4
–
–
V
VIL = VSS
–
–100
100
10
7
μA
μA
mA
mA
mA
IIH
VIL = VDD
–
–
IDDA
IDDQ
IDD
PLL supply current
AVDD only
–
5
Quiescent supply current
Dynamic supply current
All VDD pins except AVDD
Outputs loaded at 100 MHz
Outputs loaded at 200 MHz
–
–
–
270
300
4
–
–
–
CIN
Input pin capacitance
Output impedance
–
–
pF
ZOUT
12
15
18
Ω
Document Number: 38-07475 Rev. *B
Page 4 of 10
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PRELIMINARY
CY29351
AC Electrical Specifications
(V = 2.5V ± 5%, T = –40°C to +85°C)[7]
DD
A
Parameter
Description
Condition
Min
200
100
50
25
0
Typ.
–
Max
Unit
MHz
MHz
fVCO
VCO frequency
Input frequency
380
190
95
fin
÷2 feedback
–
÷4 feedback
–
÷8 feedback
–
47.5
200
75
Bypass mode (PLL_EN = 0)
–
frefDC
VPP
Input duty cycle
25
500
1.2
–
–
%
mV
V
Peak-Peak input voltage
Common mode range[8]
TCLK input rise/fall time
Maximum output frequency
LVPECL
–
1000
VDD – 0.6
1.0
190
95
VCMR
tr , tf
LVPECL
–
0.7V to 1.7V
÷2 output
÷4 output
÷8 output
–
ns
fMAX
100
50
25
47.5
45
0.1
–100
–100
–
–
MHz
–
–
47.5
52.5
55
DC
Output duty cycle
f
MAX < 100 MHz
MAX > 100 MHz
–
%
f
–
tr , tf
t(φ)
Output rise/fall times
0.6V to 1.8V
–
1.0
100
100
150
10
ns
ps
Propagation delay (static phase offset) TCLK to FB_IN
PCLK to FB_IN
–
–
tsk(O)
Output-to-Output skew
–
ps
ns
tPLZ, HZ
tPZL, ZH
BW
Output disable time
–
–
Output enable time
–
–
10
ns
PLL closed loop bandwidth (–3dB)
÷2 feedback
–
2.2
0.85
0.6
–
–
MHz
÷4 feedback
–
–
÷8 feedback
–
–
tJIT(CC)
Cycle-to-Cycle jitter
Period jitter
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
–
150
250
100
175
–
ps
ps
–
–
tJIT(PER)
–
–
–
–
tJIT(φ)
tLOCK
IO phase jitter
–
175
–
ps
Maximum PLL lock time
–
1
ms
Notes
7. AC characteristics apply for parallel output termination of 50Ω to V . Parameters are guaranteed by characterization and are not 100% tested.
TT
8.
V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
range and the input swing lies
CMR
CMR
within the V (AC) specification. Violation of V
or V impacts static phase offset t(φ).
PP
CMR
PP
Document Number: 38-07475 Rev. *B
Page 5 of 10
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PRELIMINARY
CY29351
AC Electrical Specifications
(V = 3.3V ± 5%, T = –40°C to +85°C)[7]
DD
A
Parameter
Description
Condition
Min
200
100
50
25
0
Typ.
–
Max
Unit
MHz
MHz
fVCO
VCO frequency
Input frequency
500
200
125
62.5
200
75
fin
÷2 feedback
–
÷4 feedback
–
÷8 feedback
–
Bypass mode (PLL_EN = 0)
–
frefDC
VPP
Input duty cycle
25
500
1.2
–
–
%
mV
V
Peak-Peak input voltage
Common mode range[8]
TCLK input rise/fall time
Maximum output frequency
LVPECL
–
1000
VDD – 0.9
1.0
VCMR
tr , tf
LVPECL
–
0.8V to 2.0V
÷2 output
÷4 output
÷8 output
–
ns
fMAX
100
50
25
47.5
45
0.1
–100
–100
–
–
200
125
62.5
52.5
55
MHz
–
–
DC
Output duty cycle
f
MAX < 100 MHz
MAX > 100 MHz
–
%
f
–
tr , tf
t(φ)
Output rise/fall times
0.8V to 2.4V
–
1.0
ns
ps
Propagation delay (static phase
offset)
TCLK to FB_IN, same VDD
PCLK to FB_IN, same VDD
Banks at same voltage
Banks at different voltages
–
100
100
150
350
10
–
tsk(O)
Output-to-Output skew
Bank-to-Bank skew
–
ps
ps
tsk(B)
tPLZ, HZ
tPZL, ZH
BW
–
–
Output disable time
–
–
ns
Output enable time
–
–
10
ns
PLL closed loop bandwidth (–3dB)
÷2 feedback
–
2.2
0.85
0.6
–
–
MHz
÷4 feedback
–
–
÷8 feedback
–
–
tJIT(CC)
Cycle-to-Cycle jitter
Period jitter
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
IO same VDD
–
150
250
100
150
–
ps
ps
–
–
tJIT(PER)
–
–
–
–
tJIT(φ)
tLOCK
IO phase jitter
–
175
–
ps
Maximum PLL lock time
–
1
ms
Document Number: 38-07475 Rev. *B
Page 6 of 10
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PRELIMINARY
CY29351
Figure 2. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm
Zo = 50 ohm
P ulse
G enerator
Z = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
V TT
Figure 3. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm
D ifferential
Pulse
Zo = 50 ohm
G enerator
Z = 50 ohm
Zo = 50 ohm
R T = 50 ohm
V TT
R T = 50 ohm
VTT
Figure 4. LVPECL Propagation Delay t(f), static phase offset
PECL_CLK
VCMR
PECL_CLK
VPP
VDD
FB_IN
VDD/2
t(φ)
GND
Figure 5. LVCMOS Propagation Delay t(φ), static phase offset
VDD
LVCMOS_CLK
VDD/2
GND
VDD
FB_IN
VDD/2
t(φ)
GND
Document Number: 38-07475 Rev. *B
Page 7 of 10
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PRELIMINARY
CY29351
Figure 6. Output Duty Cycle (DC)
VDD
VDD/2
GND
tP
T0
DC = tP / T0 x 100%
Figure 7. Output-to-Output Skew, tsk(O)
VDD
VDD/2
GND
VDD
VDD/2
GND
tSK(O)
Ordering Information
Part Number
Pb-free
Package Type
Product Flow
CY29351AXI
32-pin TQFP
32-pin TQFP – tape and reel
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
CY29351AXIT
Document Number: 38-07475 Rev. *B
Page 8 of 10
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PRELIMINARY
CY29351
Package Drawing and Dimension
Figure 8. 32-Pin Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm
51-85063-*B
Document Number: 38-07475 Rev. *B
Page 9 of 10
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PRELIMINARY
CY29351
Document History Page
Document Title: CY29351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Document Number: 38-0747
REV.
**
ECN No. Issue Date Orig. of Change
Description of Change
128152
245448
07/07/03
See ECN
RGL
RGL
New Data Sheet
Re-worded Select Function Descriptions in table 2.
*A
Corrected package thickness in Figure 7 from 1.4mm to 1.0mm. In Ordering
Information, removed leaded and added Pb-free parts.
*B
2001108
See ECN PYG/KVM/AESA
© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07475 Rev. *B
Revised January 21, 2008
Page 10 of 10
Spread Aware™ is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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