CY29946AIT [CYPRESS]
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32;
| 型号： | CY29946AIT |
| 厂家： | 
CYPRESS |
| 描述： | Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32 驱动 逻辑集成电路 |
| 文件： | 总7页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
46
CY29946
2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer
Features
Description
• 2.5V or 3.3V operation
• 200-MHz clock support
The CY29946 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select one of two LVCMOS/LVTTL
compatible input clocks. These clock sources can be used to
provide for test clocks as well as the primary system clocks.
All other control inputs are LVCMOS/LVTTL compatible. The
10 outputs are LVCMOS or LVTTL compatible and can drive
50Ω series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:20.
• 2 LVCMOS-/LVTTL-compatible inputs
• 10 clock outputs: drive up to 20 clock lines
• 1X or 1/2X configurable outputs
• Output three-state control
• 250 ps max. output-to-output skew
• Pin compatible with MPC946, MPC9446
• Available in Commercial and Industrial temp. range
• 32-pin TQFP package
The CY29946 is capable of generating 1X and 1/2X signals
from a 1X source. These signals are generated and retimed
internally to ensure minimal skew between the 1X and 1/2X
signals. SEL(A:C) inputs allow flexibility in selecting the ratio
of 1X to1/2X outputs.
The CY29946 outputs can also be three-stated via MR/OE#
input. When MR/OE# is set HIGH, it resets the internal
flip-flops and three-states the outputs.
Block Diagram
Pin Configuration
TCLK_SEL
/1
TCLK0
0
/2
TCLK1
1
R
0
3
QA0:2
1
TCLK_SEL
VDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
VDDC
DSELA
DSELB
TCLK0
TCLK1
DSELA
DSELB
DSELC
VSS
0
1
3
4
QB0:2
QC0:3
CY29946
0
1
DSELC
MR/OE#
Cypress Semiconductor Corporation
Document #: 38-07286 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 22, 2002
CY29946
Pin Description[1]
Pin
Name
PWR
I/O
Description
3, 4
TCLK(0,1)
QA(2:0)
I, PU External Reference/Test Clock Input
26, 28, 30
19, 21, 23
10, 12, 14, 16
5, 6, 7
VDDC
VDDC
VDDC
O
O
O
Clock Outputs
Clock Outputs
Clock Outputs
QB(2:0)
QC(0:3)
DSEL(A:C)
I, PD Divider Select Inputs. When HIGH, selects ³2 input divider. When
LOW, selects ³1 input divider.
1
TCLK_SEL
MR/OE#
I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when
HIGH TCLK1 is selected.
32
I, PD Output Enable Input. When asserted LOW, the outputs are enabled
and when asserted HIGH, internal flip-flops are reset and the outputs
are three-stated.
9, 13, 17, 18,
22, 25, 29
VDDC
2.5V or 3.3V Power Supply for Output Clock Buffers
2
VDD
VSS
2.5V or 3.3V Power Supply
Common Ground
8, 11, 15, 20,
24, 27, 31
Note:
1. PD = Internal Pull-Down, PU = Internal Pull- UP
Document #: 38-07286 Rev. *B
Page 2 of 7
CY29946
Maximum Ratings [2]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum ESD protection ...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: .............................................±20mA
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic volt-
age level (either VSS or VDD).
DC Parameters: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, Over the specified temperature range
Parameter
Description
Input Low Voltage
Input High Voltage
Input Low Current[3]
Input High Current[3]
Output Low Voltage[4]
Conditions
Min.
VSS
2.0
Typ.
Max.
0.8
Unit
V
VIL
VIH
IIL
VDD
–100
100
0.4
V
µA
µA
V
IIH
VOL
IOL = 20 mA
VOH
Output High Voltage[4] IOH = –20 mA, VDD = 3.3V
2.5
1.8
V
IOH = –20 mA, VDD = 2.5V
IDDQ
IDD
Quiescent Supply
Current
5
7
mA
mA
Dynamic Supply
Current
VDD = 3.3V, Outputs @ 100 MHz,
CL = 30 pF
130
225
95
VDD = 3.3V, Outputs @ 160 MHz,
CL = 30 pF
VDD = 2.5V, Outputs @ 100 MHz,
CL = 30 pF
VDD = 2.5V, Outputs @ 160 MHz,
CL = 30 pF
160
ZOut
Output Impedance
Input Capacitance
VDD = 3.3V
VDD = 2.5V
12
14
15
18
4
18
22
Ω
Cin
pF
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07286 Rev. *B
Page 3 of 7
CY29946
AC Parameters[5]: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, Over the specified temperature range
Parameter
Description
Input Frequency[6]
Conditions
VDD = 3.3V
Min.
Typ.
Max.
200
170
11.5
55
Unit
Fmax
MHz
VDD = 2.5V
Tpd
TTL_CLK To Q Delay[6]
Output Duty Cycle[6, 7]
5.0
45
2
ns
%
FoutDC
Measured at VDD/2
tpZL, tpZH Output enable time (all outputs)
tpLZ, tpHZ Output disable time (all outputs)
10
ns
ns
ps
ns
ns
2
10
Tskew
Output-to-Output Skew[6, 8]
Part-to-Part Skew[9]
Output Clocks Rise/Fall Time[8] 0.8V to 2.0V,
VDD = 3.3V
150
2.0
250
4.5
1.0
Tskew(pp)
Tr/Tf
0.10
0.10
0.6V to 1.8V,
VDD = 2.5V
1.3
Notes:
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
6. Outputs driving 50Ω transmission lines.
7. 50% input duty cycle.
8. See Figure 1.
9. Part-to-Part skew at a given temperature and voltage.
Document #: 38-07286 Rev. *B
Page 4 of 7
CY29946
CY29946 DUT
Zo = 50 ohm
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK CY29946 Test Reference for VCC = 3.3V and VCC = 2.5V
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
tPD
GND
Figure 2. LVCMOS Propagation Delay (TPD) Test Reference
VCC
VCC /2
tP
GND
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (FoutDC)
VCC
VCC /2
GND
VCC
VCC /2
GND
tSK(0)
Figure 4. Output-to-Output Skew tsk(0)
Document #: 38-07286 Rev. *B
Page 5 of 7
CY29946
Ordering Information
Part Number
CY29946AI
Package Type
32 Pin TQFP
Production Flow
Industrial, –40°C to +85°C
Industrial, –40°C to +85°C
Commercial, 0°C to +70°C
Commercial, 0°C to +70°C
CY29946AIT
CY29946AC
CY29946ACT
32 Pin TQFP - Tape and Reel
32 Pin TQFP
32 Pin TQFP - Tape and Reel
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32
51-85063-B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07286 Rev. *B
Page 6 of 7
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29946
Document Title: CY29946 2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer
Document Number: 38-07286
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
111097
116780
122878
Description of Change
02/07/02
08/15/02
12/22/02
BRK
HWT
RBI
New data sheet
*A
Added the Commercial Temp. Range in the Ordering Information
Added power up requirements to Maximum Ratings
*B
Document #: 38-07286 Rev. *B
Page 7 of 7
相关型号：
©2020 ICPDF网 联系我们和版权申明