CY29972_11 [CYPRESS]
3.3 V, 125-MHz Multi-Output Zero Delay Buffer Output frequency up to 125 MHz; 3.3 V ， 125 - MHz的多输出零延迟缓冲器输出频率高达125 MHz
| 型号： | CY29972_11 |
| 厂家： | 
CYPRESS |
| 描述： | 3.3 V, 125-MHz Multi-Output Zero Delay Buffer Output frequency up to 125 MHz |
| 文件： | 总13页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY29972
3.3 V, 125-MHz Multi-Output Zero Delay
Buffer
Table 1. Frequency Table[1]
Features
VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0
FVC0
8x
■ Output frequency up to 125 MHz
■ 12 Clock outputs: frequency configurable
■ 350 ps max. output-to-output skew
■ Configurable output disable
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
12x
16x
20x
16x
24x
32x
40x
4x
■ Two reference clock inputs for dynamic toggling
■ Oscillator or crystal reference input
■ Spread-spectrum-compatible
■ Glitch-free output clocks transitioning
■ 3.3 V power supply
6x
8x
10x
8x
12x
16x
20x
■ Pin-compatible with MPC972
■ Industrial temperature range: –40 °C to +85 °C
■ 52-pin Thin quad flat package (TQFP) package
Block Diagram
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
Sync
Frz
D
Q
Q
QA0
0
1
Phase
TCLK0
VCO
0
1
QA1
QA2
Detector
TCLK1
LPF
TCLK_SEL
QA3
FB_IN
Sync
Frz
QB0
QB1
D
QB2
QB3
FB_SEL2
MR#/OE
Sync
Frz
D
D
Q
Q
QC0
QC1
Power-On
Reset
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
Sync
Frz
2
QC2
SELA(0,1)
QC3
2
2
SELB(0,1)
SELC(0,1)
0
1
Sync
Frz
FB_OUT
D
D
Q
Q
/4, /6, /8, /10
Sync Pulse
/2
Sync
Frz
2
SYNC
FB_SEL(0,1)
Data Generator
SCLK
Output Disable
Circuitry
12
SDATA
INV_CLK
Note
1. x = the reference input frequency, 200 MHz < F
< 480 MHz.
VCO
Cypress Semiconductor Corporation
Document #: 38-07290 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 3, 2011
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CY29972
Contents
Pin Configuration ..............................................................3
Pin Description...................................................................3
Description ........................................................................5
Glitch-Free Output Frequency Transitions .....................5
SYNC Output .....................................................................6
Power Management ..........................................................7
Absolute Maximum Ratings............................................. 7
DC Parameters ..................................................................8
AC Parameters ..................................................................8
Ordering Information........................................................ 9
Ordering Code Definition .............................................9
Package Drawing and Dimension ................................. 10
Acronyms ........................................................................ 11
Document Conventions .................................................11
Units of Measure ....................................................... 11
Document History Page .................................................12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Document #: 38-07290 Rev. *D
Page 2 of 13
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CY29972
Pin Configuration
52 51 50 49 48 47 46 45 44 43 42 41 40
39
VSS
VSS
MR#/OE
SCLK
1
2
3
4
5
6
7
8
QB0
38
37
36
35
34
33
32
31
30
29
28
27
VDDC
QB1
VSS
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
QB2
VDDC
QB3
CY29972
FB_IN
VSS
9
10
11
12
13
TCLK1
XIN
FB_OUT
VDDC
FB_SEL0
XOUT
VDD
14 15 16 17 18 19 20 21 22 23 24 25 26
Pin Description[2]
Pin
Name
PWR
I/O
I
Type
Description
11
XIN
–
–
–
–
Oscillator input. Connect to a crystal.
Oscillator output. Connect to a crystal.
12
XOUT
O
I
9
TCLK0
–
PU External reference/test clock input.
PU External reference/test clock input.
10
TCLK1
–
I
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
29
QA(3:0)
QB(3:0)
QC(3:0)
FB_OUT
VDDC
VDDC
VDDC
VDDC
O
O
O
O
–
–
–
–
Clock outputs. See Table 2 for frequency selections.
Clock outputs. See Table 2 on page 5 for frequency selections.
Clock outputs. See Table 2 on page 5 for frequency selections.
Feedback clock output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Table 1 on page
1. A bypass delay capacitor at this output will control Input Reference/
Output Banks phase relationships.
25
SYNC
VDDC
O
–
Synchronous pulse output. This output is used for system
synchronization. The rising edge of the output pulse is in sync with both
the rising edges of QA (0:3) and QC(0:3) output clocks regardless of
the divider ratios selected.
42, 43
40, 41
SELA(1,0)
SELB(1,0)
SELC(1,0)
–
–
–
I
I
I
PU Frequency select inputs. These inputs select the divider ratio at
QA(0:3) outputs. See Table 2.
PU Frequency select inputs. These inputs select the divider ratio at
QB(0:3) outputs. See Table 2.
19, 20
PU Frequency select inputs. These inputs select the divider ratio at
QC(0:3) outputs. See Table 2.
Note
2. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces
Document #: 38-07290 Rev. *D
Page 3 of 13
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CY29972
Pin Description[2]
Pin
Name
PWR
I/O
Type
Description
5, 26, 27
FB_SEL(2:0)
–
I
PU Feedback select inputs. These inputs select the divide ratio at
FB_OUT output. See Table 1 on page 1.
52
VCO_SEL
–
I
PU VCO divider select input. When set LOW, the VCO output is divided
by 2. When set HIGH, the divider is bypassed. See Table 1 on page 1.
31
6
FB_IN
–
–
I
I
PU Feedback clock input. Connect to FB_OUT for accessing the PLL.
PLL_EN
PU PLL enable input. When asserted HIGH, PLL is enabled; when LOW,
PLL is bypassed.
7
8
2
REF_SEL
TCLK_SEL
MR#/OE
–
–
–
I
I
I
PU Reference select input. When HIGH, the crystal oscillator is selected;
when LOW, TCLK (0,1) is the reference clock.
PU TCLK select input. When LOW, TCLK0 is selected and when HIGH
TCLK1 is selected.
PU Master reset/output enable input. When asserted LOW, resets all of
the internal flip-flops and also disables all of the outputs. When pulled
high, releases the internal flip-flops from reset and enables all of the
outputs.
14
INV_CLK
–
I
PU Inverted clock input. When set HIGH, QC(2,3) outputs are inverted.
When set LOW, the inverter is bypassed.
3
4
SCLK
–
–
I
I
PU Serial clock input. Clocks data at SDATA into the internal register.
SDATA
PU Serial data input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
17, 22, 28,
VDDC
–
–
–
3.3 V power supply for output clock buffers.
33,37, 45, 49
13
VDD
VSS
–
–
–
–
–
–
3.3 V power supply for PLL.
Common ground.
1, 15, 24, 30,
35, 39, 47, 51
Document #: 38-07290 Rev. *D
Page 4 of 13
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CY29972
The CY29972 is also capable of providing inverted output clocks.
When INV_CLK is asserted HIGH, QC2 and QC3 output clocks
are inverted. These clocks could be used as feedback outputs to
the CY29972 or a second PLL device to generate early or late
clocks for a specific design. This inversion does not affect the
output to output skew.
Description
The CY29972 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
Three independent banks of four outputs and an independent
PLL feedback output (FB_OUT) provide exceptional flexibility for
possible output configurations. The PLL is ensured stable
operation given that the VCO is configured to run between 200
MHz and 480 MHz. This allows a wide range of output
frequencies up to125 MHz.
Glitch-Free Output Frequency Transitions
Customarily, when output buffers have their internal counters
changed “on the fly,” their output clock periods will:
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input (FB_IN) is connected to the feedback output
(FB_OUT). The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select inputs
(refer to Frequency Table). The VCO frequency is then divided to
provide the required output frequencies. These dividers are set
by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see the
following Table). For situations were the VCO needs to run at
relatively low frequencies and hence might not be stable, assert
VCO_SEL low to divide the VCO frequency by 2. This maintains
the desired output relationships but provides an enhanced PLL
lock range.
1. contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the old
or new frequencies to which the cycles are being transitioned.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old or
new frequencies to which the cycles are being transitioned.
This device specifically includes logic to guarantee that runt and
stretched clock pulses do not occur if the device logic levels of
any or all of the following pins changed “on the fly” while it is
operating: SELA, SELB, SELC, and VCO_SEL.
VCO_SEL
SELA1
SELA0
QA
SELB1
SELB0
QB
SELC1
SELC0
QC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/8
VCO/12
VCO/16
VCO/24
VCO/4
VCO/6
VCO/8
VCO/12
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/8
VCO/12
VCO/16
VCO/20
VCO/4
VCO/6
VCO/8
VCO/10
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/4
VCO/8
VCO/12
VCO/16
VCO/2
VCO/4
VCO/6
VCO/8
Document #: 38-07290 Rev. *D
Page 5 of 13
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CY29972
rising edges of the QA and QC outputs. The duration and
placement of the pulse depend on the higher of the QA and QC
output frequencies. The following timing diagram illustrates
various waveforms for the SYNC output. Note that the SYNC
output is defined for all possible combinations of QA and QC
outputs, even though under some relationships the lower
frequency clock could be used as a synchronizing signal.
SYNC Output
In situations where output frequency relationships are not integer
multiples of each other, the SYNC output provides a signal for
system synchronization. The CY29972 monitors the relationship
between the QA and QC output clocks. It provides a LOW-going
pulse, one period in duration, one period prior to the coincident
Figure 1. Timing Diagram
VCO
1:1 Mode
2:1 Mode
QA
QC
SYNC
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
QA
QC
SYNC
4:1 Mode
QC
QA
SYNC
4:3 Mode
QA
QC
SYNC
6:1 Mode
QA
QC
SYNC
Document #: 38-07290 Rev. *D
Page 6 of 13
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CY29972
An output is frozen when a logic ‘0’ is programmed and enabled
when a logic ‘1’ is written. The enabling and freezing of individual
outputs is done in such a manner as to eliminate the possibility
of partial “runt” clocks.
Power Management
The individual output enable/freeze control of the CY29972
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic ‘0’
state when the freeze control bits are activated. The serial input
register contains one programmable freeze enable bit for 12 of
the 14 output clocks. The QC0 and FB_OUT outputs can not be
frozen with the serial port, this avoids any potential lock up
situation should an error occur in the loading of the serial data.
The serial input register is programmed through the SDATA input
by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable
bits. The period of each SDATA bit equals the period of the free
running SCLK signal. The SDATA is sampled on the rising edge
of SCLK.
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Table 2. Suggested Oscillator Crystal Parameters
Parameter Characteristic
TC Frequency tolerance
Min.
Typ.
–
Max.
±100
±100
5
Unit
PPM
Conditions
–
–
–
–
–
Note 3
TS
Frequency temperature stability
Aging
–
PPM
(TA –10 to +60 °C)[3]
(first 3 years at 25 °C)[3]
The crystal’s rated load.[3]
Note 4
TA
–
PPM/Yr
pF
CL
Load capacitance
20
40
–
RESR
Effective series resistance (ESR)
80
Ohms
Absolute Maximum Ratings[5]
Maximum input voltage relative to VSS:.............. VSS – 0.3 V
Maximum input voltage relative to VDD:.............. VDD + 0.3 V
Storage temperature:................................ –65 °C to +150 °C
Operating temperature: .............................. –40 °C to +85 °C
Maximum ESD protection............................................... 2 kV
Maximum power supply:................................................ 5.5 V
Maximum input current:............................................. ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, VIN and VOUT should be constrained to the range:
V
SS < (VIN or VOUT) < VDD .Unused inputs must always be tied
to an appropriate logic voltage level (either VSS or VDD).
Notes
3. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these specifications.
4. Larger values may cause this device to exhibit oscillator start-up problems.
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07290 Rev. *D
Page 7 of 13
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CY29972
DC Parameters VDD = 2.9 V to 3.6 V, VDDC = 3.3 V ±10%, TA = –40 °C to +85 °C
Parameter
VIL
Description
Input Low voltage
Test Conditions
Min
VSS
2.0
–
Typ
–
Max
0.8
VDD
–120
10
0.5
–
Unit
V
VIH
IIL
Input High voltage
Input Low current[6]
–
V
–
µA
µA
V
IIH
Input High current
–
–
VOL
VOH
IDDQ
IDDA
IDD
Output Low voltage[7]
Output High voltage[7]
Quiescent supply current
PLL supply current
Dynamic supply current
IOL = 20 mA
–
–
IOH = –20 mA
2.4
–
–
V
10
15
225
125
4
15
20
–
mA
mA
mA
VDD only
–
QA and QB at 60 MHz, QC at 120 MHz, CL = 30 pF
QA and QB at 25 MHz, QC at 50 MHz, CL = 30 pF
–
–
–
CIN
Input pin capacitance
–
–
pF
AC Parameters VDD = 2.9 V to 3.6 V, VDDC = 3.3 V ±10%, TA = –40 °C to +85 °C[8]
Parameter
Tr / Tf
Fref
Description
TCLK input rise/fall
Conditions
Min
Typ
Max
Unit
ns
–
–
–
3.0
Note 9
25
Reference input frequency
Crystal Oscillator Frequency
Reference input duty cycle
PLL VCO lock range
Note 9
MHz
MHz
%
Fxtal
see Table 2
10
–
FrefDC
Fvco
25
–
75
200
–
480
10
MHz
ms
Tlock
Maximum PLL lock time
–
–
Tr / Tf
Fout
Output clocks rise / fall time[10]
0.8 V to 2.0 V
Q (³2)
0.15
–
1.2
ns
Maximum Output Frequency
–
–
125
120
80
MHz
Q (³4)
–
–
Q (³6)
–
–
Q (³8)
–
–
60
FoutDC
Output duty cycle[10]
TCYCLE/2 – 750
–
TCYCLE/2 + 750
ps
ns
ns
ps
ps
ps
tpZL, tpZH Output enable time[10](all outputs)
tpLZ, tpHZ Output disable time[10](all outputs)
2
2
–
10
8
–
TCCJ
TSKEW
Tpd
Cycle to cycle jitter[10](peak to peak)
Any output to any output skew[10,11]
Propagation delay[11,12]
–
± 100
250
130
70
–
–
350
530
470
TCLK0
TCLK1
QFB = (³8)
–270
–330
Notes
6. Inputs have pull-up/pull-down resistors that effect input current.
7. Driving series or parallel terminated 50 (or 50 to V ) transmission lines.
DD/2
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. Maximum and minimum input reference is limited by VC0 lock range.
10. Outputs loaded with 30 pF each.
11. 50 transmission line terminated into V
.
DD/2
12. Tpd is specified for a 50-MHz input reference. Tpd does not include jitter.
Document #: 38-07290 Rev. *D
Page 8 of 13
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CY29972
Ordering Information
Part Number
CY29972AI
Package Type
52-pin TQFP
Production Flow
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
CY29972AIT
Pb-free
52-pin TQFP - Tape and Reel
CY29972AXI
CY29972AXIT
52-pin TQFP
Industrial, –40 °C to +85 °C
Industrial, –40 °C to +85 °C
52-pin TQFP - Tape and Reel
Ordering Code Definition
AX
CY 29972
X
T
T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type
AX = 52-pin TQFP
Base Device Part Number
Company ID: CY = Cypress
Document #: 38-07290 Rev. *D
Page 9 of 13
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CY29972
Package Drawing and Dimension
52-Lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85131 *A
Document #: 38-07290 Rev. *D
Page 10 of 13
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Acronyms
Acronym
I/O
Description
input/output
PLL
phase locked loop
TQFP
Thin quad flat pack
Document Conventions
Units of Measure
Symbol
°C
Units of Measure
degree celsius
micro amperes
milli amperes
milli seconds
mega hertz
nano seconds
pico farad
µA
mA
ms
MHz
ns
pF
ps
pico seconds
volts
V
Document #: 38-07290 Rev. *D
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CY29972
Document History Page
Document Title: CY29972 3.3V, 125-MHz Multi-Output Zero Delay Buffer
Document Number: 38-07290
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
111101
122882
387764
02/07/02
12/22/02
See ECN
BRK
New Data Sheet
Added power up requirements to Maximum Ratings
*A
*B
RBI
RGL
Changed the package drawing and dimension to Cypress Standard
Added Pb-free devices
*C
*D
404340
See ECN
RGL
Minor Change: corrected the package diagram
3270575 06/03/2011
BASH
Updated as per template
Updated package diagram 51-85131.
Added Acronyms and Units of Measure Table
Document #: 38-07290 Rev. *D
Page 12 of 13
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CY29972
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07290 Rev. *D
Revised June 3, 2011
Page 13 of 13
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