CY2CC1810O [CYPRESS]
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, SSOP-24;
| 型号： | CY2CC1810O |
| 厂家： | 
CYPRESS |
| 描述： | Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, SSOP-24 光电二极管 |
| 文件： | 总11页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
Product Features
Product Description
The CYPRESS ComL series of network circuits are
produced using advanced 0.35 micron CMOS
technology, achieving the industries fastest logic and
buffers.
•
Low Voltage Operation
VDD range from 3.6 to 1.65V
•
•
•
•
1:10 Fanout
Low input capacitance
Low output skew
Low propagation delay
High Speed (tpd<5.0ns)
The CYPRESS CY2CC1810 fanout buffer features
one input and ten outputs.
Designed
for
Data
Communications
clock
•
•
High Speed Operation >200MHz
management applications, the large fanout from a
single input reduces loading on the input clock.
LVTTL/LVCMOS compatible input
Output Disable to Tri-state
•
VOI ä Output Drivers for low noise
AVCMOS type outputs dynamically adjust for variable
impedance matching and eliminate the need for series
damping resistors and reduce noise overall.
Eliminates the need for series damping resistors
•
•
Industrial Operation at 0°C to +85°C
Packages available include: SOIC/SSOP
Pin Configuration
Block Diagram
23
21
5
Q1
GND
Q10
VDD
Q9
GND
Q1
OE#
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
VDD
Q2
19
18
OE#
IN
GND
GND
Q3
Q4
VDD
3,10
15,22
GND
Q8
GND
Q5
16
14
11
9
9
6
VDD
VDD
Q6
GND
10
11
12
Q7
GND
1,12,13
17,24
IN
24 pin SOIC/SSOP
GND
4
2
OUTPUT (AVCMOS)
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07055 Rev. **
5/8/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 1 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
Pin Description
Pin Number
Pin Name
Description
1,7,8,12,13,17,20,24
3,10,15,22
GND
Ground
Power
Power
V
DD
Power Supply
LVTTL /
LVCMOS
LVTTL /
LVCMOS
5
OE#
IN
Output Enable
Input
6
2,4,9,11,14,16,18,19,21,23
Q10,Q9,Q8,Q7,Q6,Q5,Q4,Q3,Q2,Q1 Output
AVC CMOS
All power pins must be connected. Input pins shall be connected or pulled by resistors to be a 1 or a zero.
Absolute Maximum Ratings:
Storage Temperature
Ambient Temperature
-65°C to 150°C
0°C to +85°C
Supply Voltage to Ground Potential
(Inputs and VDD only)
-0.5V to 4.6V
Supply Voltage to Ground Potential
(outputs and D/O only)
-0.5V to V +0.5V
DD
DC Input Voltage
DC Output Voltage
Power Dissipation
-0.5V to V +0.5V
DD
-0.5V to V +0.5V
DD
0.75W
Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07055 Rev. **
5/8/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 2 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
D.C. Electrical Characteristics: @ 3.3V
D.C. Electrical Characteristics (Over the Operating Range , TA = 0°C to +85°C, VDD=3.3V +/-5%
Parameter Description Test Conditions Min.
Typ
3.3
Max
Units
V
Output High Voltage 2.3
V
=Min., V =V or V
I
= -12mA
V
OH
OL
IH
DD
DD
IN IH
IL
IL
OH
V
V
V
Output Low Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Continuous Clamp Current
Power Down Disable
Input Hysteresis
V
=Min., V =V or V
IN IH
I
= 12mA
OL
0.2
0.5
V
V
Guaranteed Logic High Level
Guaranteed Logic Low Level
2
0.8
1
V
IL
I
I
I
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
=Max
=Max
V
V
=2.7V
=0.5V
uA
uA
uA
V
IH
IN
-1
IL
I
IN
=Max., V =V (Max)
IN DD
20
V
=Min., I = -18mA
IN
-0.7
80
-1.2
-50
100
IK
I
=Max, V
OUT
= GND
mA
uA
mV
OK
O
= GND, V =<4.5V
OUT
OFF
H
V
D.C. Electrical Characteristics: @ 2.5V
D.C. Electrical Characteristics (Over the Operating Range , TA = 0°C to +85°C, VDD=2.5 +/-5%
Typ
Parameter
Description
Test Conditions
Min.
Max
Units
I
I
I
= -7mA
1.80
V
OH
V
Output High Voltage
V
=Min., V =V or V
IN IH
OH
DD
IL
= -15.2mA 1.60
V
V
OH
V
OL
V
IH
V
IL
Output Low Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Continuous Clamp Current
Power Down Disable
Input Hysteresis
V
DD
=Min., V =V or V
IN IH
= 15.2mA
OL
0.65
1.60
IL
Guaranteed Logic High Level
Guaranteed Logic Low Level
V
0.9
1
V
I
I
I
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
=Max
=Max
V
V
=2.4V
=0.5V
uA
uA
uA
V
IH
IN
-1
IL
I
IN
=Max, V =V (Max)
IN DD
20
V
IK
=Min. I = -18mA
IN
-0.7
80
-1.2
-50
100
I
=Max, V
OUT
= GND
mA
uA
mV
OK
O
= GND, V =<4.5V
OUT
OFF
H
V
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07055 Rev. **
5/8/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 3 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
Capacitance:
Parameter
Cin
Description
Test Conditions
Vin = 0V
Typ
2.5
6.5
Max
5
Units
pF
Input Capacitance
Output Capacitance
Cout
Vout = 0V
8
pF
Power Supply Characteristics:
Min
.
Symbol
Parameter
Test Conditions
Typ
Max Unit
Delta Quiescent Power Supply
Current
LVTTL/LVCMOS Inputs High
|value| = (V
= Max ) -
DD
= V -0.6V)
fL=0Hz
∆ICC
(V
DD
-
-
3
50
uA
DD
V
DD
= Max
fL=fMAX
OE# = VDD
mA /
MHz
Input toggling 50% Duty
Cycle, Outputs Open
Dynamic Power Supply Current
Total Power Supply Current
1
2.2
ICCD
IC
V
DD
= Max
fL=100MHz
OE# = GND
Input toggling 50% Duty
Cycle, Outputs Open
-
310
350
mA
High Frequency Parametrics :
Symbol
Parameter
Maximum frequency
VDD = 3.3V
Test Conditions
50% duty cycle tW(50-50)
Standard Load Circuit
Min
Typ
Max Unit
160
MHz
200
Fmax
-
-
50% duty cycle tW(50-50)
The “point to point load circuit”
20% duty cycle tW(20-80)
The “point to point load circuit”
Vin = 3.0V / 0.0V
Maximum frequency
VDD = 3.3 V
200
Vout = 2.3V / 0.4V
The “point to point load circuit”
Vin = 2.4 / 0.0V
Fmax(20)
-
-
-
MHz
Maximum frequency VDD =
2.5 V
100
Vout = 1.7V / 0.7V
The “point to point load circuit”
Vin = 3.0V / 0.0V F = 100MHz
Vout = 2.0V / 0.8V
The “point to point load circuit”
Vin = 2.4 / 0.0V F = 100MHz
Vout = 1.7V / 0.7V
Minimum pulse
VDD = 3.3 V
2
1
tW
-
nS
Minimum pulse
VDD = 2.5 V
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07055 Rev. **
5/8/2001
Page 4 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
AC Switching Characteristics @ 3.3
AC Switching Characteristics Over Operating Range VDD = 3.3V +/-5%, Temperature = 0°C to +85°C
Symbol
tPLH
Parameter
Propagation Delay – Low to High
Propagation Delay – High to Low
Propagation Delay –High to High Z
Propagation Delay – Low to High Z
Output Rise Time
Conditions
Min
Typ
3
Max Units
-
-
-
-
-
-
-
-
-
-
-
-
nS
nS
tPHL
tPHZ
tPLZ
tR
3
4
nS
3
nS
0.8
0.8
V/nS
V/nS
tF
Output Fall Time
Output Skew: Skew between outputs of the same
package (in phase)
Pulse Skew: Skew between opposite transitions
of the same output (TPHL – TPLH)
tSK(0)
tSK(p)
-
-
-
-
0.2
0.2
nS
nS
Package Skew: Skew between outputs of
different packages at the same power supply
voltage, temperature and package type.
tSK(t)
toff
-
-
0.3
nS
nS
nS
Delay from OE to driver off
4.00
4.00
ton
Delay from OE to Driver on
AC Switching Characteristics @ 2.5
AC Switching Characteristics Over Operating Range VDD = 2.5V +/-5%, Temperature = 0°C to +85°C
Symbol
tPLH
Parameter
Propagation Delay – Low to High
Propagation Delay – High to Low
Propagation Delay –High to High Z
Propagation Delay – Low to High Z
Output Rise Time
Conditions
Min
Typ
3.8
3.8
5
Max Units
-
-
-
-
-
-
-
-
-
-
-
-
nS
nS
tPHL
tPHZ
tPLZ
tR
nS
4
nS
0.4
0.6
V/nS
V/nS
tF
Output Fall Time
Output Skew: Skew between outputs of the same
package (in phase)
Pulse Skew: Skew between opposite transitions of
the same output (TPHL – TPLH)
tSK(0)
tSK(p)
-
-
-
-
0.2
0.2
nS
nS
Package Skew: Skew between outputs of
different packages at the same power supply
voltage, temperature and package type.
tSK(t)
toff
-
-
0.3
nS
nS
nS
Delay from OE to driver off
Delay from OE to Driver on
5.00
5.00
ton
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07055 Rev. **
5/8/2001
Page 5 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
Parameter Measurement Information
VDD @ 2.5
tw(50-50)
1.25 V
2.0 V
Input
Input
1.25 V
1.25 V
6 V
0 V
500 ohm
500 ohm
O pen
tw(20-80)
2.0 V
From O utput
Under Test
VSS
0 V
CL = 50 pF
(see Note A)
Voltage Waveforms - Pulse Duration
VOH
(min)
3.3 V
0 V
Output Control
(low-level enabling)
1.25 V
Load Circuit
VOL
(max)
tPZL
tPLZ
2.7 V
2.5V
VOL
1.5 V
th
Waveform 1
S1 at 2 x VDD
(see Note B)
Timing Input
Data Input
1.25 V
1.25V
VOL + 0.3V
tPHZ
0 V
tPZH
tsu
VOH
Waveform 2
S1 at GND
(see Note B)
V
OH- 0.3V
~0 V
2.7 V
0 V
1.5 V
1.5 V
Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Setup and Hold Times
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such
that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal
conditions such that the output is high except when
disabled by the output control.
C. All input pulses are supplied by generators having the
following characteristics: PRR < 10 MHz, ZO = 50 Ω, tr <
2.5 nS, tf < 2.5nS.
1.5 V
1.5 V
1.5 V
Input
0 V
tPLH
tPHL
VOH
VOL
1.5 V
Voltage Waveforms
1.5 V
Output
D. The outputs are measured one at a time with on
transition per measurement.
E.
F.
G.
t
t
t
and t
are the same as t
.
Propagation Delay Times
PLZ
PZL
PLH
PHZ
PZH
dis
and t
are the same as t
.
en
and t
are the same as t
.
PHL
pd
Test
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VDD
VSS
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07055 Rev. **
5/8/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 6 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
Parameter Measurement Information
VDD @ 3.3
6 V
Open
500 ohm
500 ohm
From Output
Under Test
VSS
VOH (min)
3.3 V
CL = 50 pF
(see Note A)
VOL
(max)
1.5 V
Output Control
(low-level enabling)
0 V
tPZL
tPLZ
Z
3 V
VOL
Waveform 1
S1 at 2 x VDD
(see Note I)
Load Circuit
1.5 V
1.5V
VOL + 0.3V
tPHZ
tPZH
VOH
2.7 V
Waveform 2
S1 at GND
(see Note I)
V
OH- 0.3V
1.5 V
th
Timing Input
Data Input
Z
~0 V
0 V
Voltage Waveforms
Enable and Disable Times
tsu
2.7 V
0 V
1.5 V
1.5 V
tw(50-50)
2.0 V
Voltage Waveforms
Setup and Hold Times
Input
Input
1.25 V
1.25 V
1.25 V
0 V
tw(20-80)
2.0 V
0 V
Voltage Waveforms - Pulse Duration
1.5 V
1.5 V
1.5 V
Notes:
H. CL includes probe and jig capacitance.
Input
0 V
tPLH
tPHL
I. Waveform 1 is for an output with internal conditions such
that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal
conditions such that the output is high except when
disabled by the output control.
J. All input pulses are supplied by generators having the
following characteristics: PRR < 100 MHz, ZO = 50 Ω, tr
< 2.5 nS, tf < 2.5nS.
VOH
VOL
1.5 V
Voltage Waveforms
1.5 V
Output
Propagation Delay Times
K. The outputs are measured one at a time with on
transition per measurement.
Test
S1
L.
t
t
t
and t
are the same as t
.
PLZ
PZL
PLH
PHZ
PZH
dis
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 x VDD
VSS
M.
N.
and t
are the same as t
.
en
and t
are the same as t
.
PHL
pd
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07055 Rev. **
5/8/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 7 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
Parameter Measurement Information
VDD @ 2.5
VDD @ 3.3
From Output
From Output
Under Test
CL = 3 pF
(see Notes
Under Test
CL = 3 pF
(see Notes
500 ohm
500 ohm
A,B,C)
A,B,C)
Point to Point Load Circuit
Point to Point Load Circuit
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07055 Rev. **
5/8/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 8 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
24 Pin SSOP Outline Dimensions
INCHES
MILLIMETERS
SYMBOL
MIN
-
NOM
MAX
MIN
-
NOM
MAX
A
A1
A2
B
-
.07874
-
-
2.0
.001969
.06496
.008661
.003543
.3110
.1969
-
0.05
1.65
0.22
0.09
7.90
5.00
-
-
.06890
.07283
.01496
.009843
.3346
.2205
1.75
1.85
0.38
0.25
8.50
5.60
-
-
-
C
D
E
-
.3228
Package Drawing and Dimensions
8.20
5.30
0.65 BSC
7.80
0.75
-
.2087
C
e
0.02559 BSC
.3071
L
H
L
.2913
.02165
0º
.3228
0.037
8º
7.40
0.55
0º
8.20
0.95
8º
H
.02953
-
E
a
D
a
A2
A
A1
e
24 Pin SOIC Outline Dimensions
B
INCHES
MILLIMETERS
SYMBOL
MIN
.09252
NOM
MAX
.1043
MIN
2.35
.10
NOM
MAX
A
A1
A2
B
-
-
2.65
.30
.003937
.08858
.01299
.009055
.5984
-
.01181
.09252
.02008
.01260
.6142
-
-
2.250
.33
-
2.350
.51
-
-
C
D
E
-
.23
-
.32
-
15.20
7.40
-
15.60
7.60
.2913
-
.2992
-
e
0.050 BSC
1.27 BSC
H
L
.3937
.01575
0º
-
-
-
.4193
.050
8º
10.00
.40
-
-
-
10.65
1.27
8º
a
0º
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07055 Rev. **
5/8/2001
Page 9 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
Ordering Information
Part Number
Package Type
CY2CC1810S
24 Pin SOIC
CY2CC1810O
24 Pin SSOP
Note: the ordering part number is formed by a combination of device number, package and screening as shown below.
Marking:
Example:
CY2CC1810 S
Date Code, A
Lot #
CY2CC1810S
Package
S = SOIC
O = SSOP
CYPRESS Device Number
INPUT OUTPUT Family
Communication Link Series
Notice
Cypress Semiconductor Corporation reserves the right to change or modify the information contained in this data
sheet, without notice. Cypress Semiconductor Corporation does not assume any liability arising out of the application
or use of any product or circuit described herein. Cypress Semiconductor Corporation does not convey any license
under its patent rights nor the rights of others. Cypress Semiconductor Corporation does not authorize its products for
use as critical components in life-support systems or critical medical instruments, where a malfunction or failure may
reasonably be expected to result in significant injury to the user.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07055 Rev. **
5/8/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 10 of 11
Preliminary
CY2CC1810
1:10 Signal Fanout Buffer w/ Output Enable
ComLTM SERIES
Document Title: CY2CC2920 1:10 Signal Fanout Buffer w/ Output Enable
Document Number: 38-07055
Rev. ECN
No.
Issue
Date
Orig. of
Change
Description of Change
**
107080 06/07/01 IKA
Convert from IMI to Cypress
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07055 Rev. **
5/8/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 11 of 11
相关型号：
CY2CC1810S
Low Skew Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO24, SOIC-24
CYPRESS
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