CY2CP1504ZXC [CYPRESS]
1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input; 1 ： 4 LVCMOS至LVPECL扇出缓冲器，具有可选时钟输入
| 型号： | CY2CP1504ZXC |
| 厂家： | 
CYPRESS |
| 描述： | 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input |
| 文件： | 总13页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2CP1504
1:4 LVCMOS to LVPECL Fanout Buffer
with Selectable Clock Input
Features
Functional Description
■ Select one of two low-voltage complementary metal oxide
semiconductor (LVCMOS) inputs to distribute to four
low-voltage positive emitter-coupled logic (LVPECL) output
pairs
The CY2CP1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The CY2CP1504 can select between
two separate LVCMOS input clocks using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The device has a
fully differential internal architecture that is optimized to achieve
low additive jitter and low skew at operating frequencies of up to
250 MHz.
■ 30-ps maximum output-to-output skew
■ 480-ps maximum propagation delay
■ 0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
■ Up to 250 MHz operation
■ Synchronous clock enable function
■ 20-Pin thin shrunk small outline package (TSSOP) package
■ 2.5-V or 3.3-V operating voltage[1]
■ Commercial and industrial operating temperature range
Logic Block Diagram
Q0
Q0#
VDD
VSS
Q1
Q1#
IN0
IN1
Q2
Q2#
Q3
Q3#
IN_SEL
100k
VDD
100k
Q
D
CLK_EN
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56313 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 25, 2011
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CY2CP1504
Contents
Pinouts .............................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions....................................................... 4
DC Electrical Specifications............................................ 5
AC Electrical Specifications............................................ 6
Ordering Information........................................................ 9
Ordering Code Definition............................................. 9
Package Dimension........................................................ 10
Acronyms........................................................................ 11
Document Conventions ................................................. 11
Document History Page................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support....................... 13
Products.................................................................... 13
PSoC Solutions......................................................... 13
Document Number: 001-56313 Rev. *F
Page 2 of 13
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CY2CP1504
Pinouts
Figure 1. Pin Diagram – 20-Pin TSSOP Package
VSS
1
20
Q0
CLK_EN
IN_SEL
2
3
4
5
19
18
17
16
Q0#
VDD
Q1
IN0
NC
IN1
NC
NC
Q1#
Q2
6
7
8
15
14
13
Q2#
VDD
Q3
9
12
11
NC
VDD
Q3#
10
Table 1. Pin Definitions
Pin No.
Pin Name
Pin Type
Power
Description
1
2
VSS
Ground
CLK_EN
Input
Synchronousclockenable. LVCMOS/low-voltagetransistor-transistorlogic
(LVTTL).
When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are
held high
3
4
IN_SEL
Input
Input
Input clock select pin. LVCMOS/LVTTL;
When IN_SEL = Low, input IN0 is active
When IN_SEL = High, input IN1 is active
IN0
LVCMOS input clock. Active when IN_SEL = Low
No connection
5,7,8,9
NC
6
IN1
Input
LVCMOS input clock. Active when IN_SEL = High
Power supply
10,13,18
11,14,16,19
12,15,17,20
VDD
Power
Output
Output
Q(0:3)#
Q(0:3)
LVPECL complementary output clocks
LVPECL output clocks
Document Number: 001-56313 Rev. *F
Page 3 of 13
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CY2CP1504
Absolute Maximum Ratings
Parameter
Description
Condition
Nonfunctional
Min
–0.5
–0.5
Max
Unit
V
VDD
Supply voltage
4.6
[2]
lesser of 4.0
VIN
Input voltage, relative to VSS
Nonfunctional
V
or V + 0.4
DD
[2]
lesser of 4.0
VOUT
DC output or I/O voltage, relative to VSS
Nonfunctional
–0.5
V
or V + 0.4
DD
TS
Storage temperature
Nonfunctional
–55
150
–
°C
V
ESDHBM
LU
Electrostatic discharge (ESD) protection
(Human body model)
JEDEC STD 22-A114-B
2000
Latch up
Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test
UL–94
MSL
Flammability rating
At 1/8 in
V-0
3
Moisture sensitivity level
Operating Conditions
Parameter
Description
Condition
2.5-V supply
3.3-V supply
Commercial
Min
2.375
3.135
0
Max
2.625
3.465
70
Unit
V
VDD
TA
Supply voltage
V
Ambient operating temperature
Power ramp time
°C
°C
ms
Industrial
–40
85
tPU
Power-up time for VDD to reach
minimum specified voltage (power
ramp must be monotonic)
0.05
500
Note
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required.
Document Number: 001-56313 Rev. *F
Page 4 of 13
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CY2CP1504
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
IDD
Description
Operating supply current
Condition
All LVPECL outputs floating (internal IDD
VDD = 3.3 V
Min
–
Max
61
Unit
mA
V
)
VIH1
VIL1
VIH2
VIL2
IIH
Input high voltage, All inputs
Input low voltage, All inputs
Input high voltage, All inputs
Input low voltage, All inputs
Input high current, All inputs
Input low current, All inputs
LVPECL output high voltage
LVPECL output low voltage
Internal pull-up/pull-down resistance
2.0
–0.3
1.7
–0.3
–
VDD + 0.3
0.8
VDD = 3.3 V
V
VDD = 2.5 V
VDD + 0.3
0.7
V
VDD = 2.5 V
V
[3]
Input = VDD
150
μA
μA
V
[3]
IIL
Input = VSS
–150
–
VOH
VOL
RP
Terminated with 50 Ω to VDD – 2.0[4]
Terminated with 50 Ω to VDD – 2.0[4]
VDD – 1.20 VDD – 0.70
VDD – 2.0 VDD – 1.63
V
CLK_EN has pull-up only
IN_SEL has pull-down only
60
140
kΩ
CIN
Input capacitance
Measured at 10 MHz; per pin
–
3
pF
Notes
3. Positive current flows into the input pin, negative current flows out of the input pin.
4. Refer to Figure 2 on page 7.
Document Number: 001-56313 Rev. *F
Page 5 of 13
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CY2CP1504
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85°C (Industrial))
Parameter
Description
Input frequency
Condition
Min
DC
Typ
–
Max
250
250
–
Unit
MHz
MHz
mV
FIN
FOUT
VPP
Output frequency
FOUT = FIN
DC
–
LVPECL differential output voltage
peak- to-peak, single-ended.
Fout = DC to 150 MHz
600
400
–
Fout = >150 MHz to 250 MHz
–
–
mV
Terminated with 50 Ω to VDD – 2.0[4]
[5]
tPD
Propagation delay input to output pair Input rise/fall time < 1.5 ns
(20% to 80%)
–
45
–
–
–
–
–
480
55
ps
%
[6]
tODC
Output duty cycle
Rail-to-rail input swing, 50%
input DTCY measured at Vdd/2
[7]
tSK1
Output-to-output skew
Device-to-device output skew
Any output to any output, with
same load conditions at DUT
30
ps
ps
[7]
tSK1 D
Any output to any output
between two or more devices.
Devices must have the same
input and have the same output
load.
–
150
PNADD
Additive RMS phase noise
156.25-MHz Input
Rise/fall time < 150 ps (20% to 80%)
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 1 MHz
Offset = 10 MHz
Offset = 20 MHz
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–120
–130
–135
–150
–150
–150
0.15
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
VID > 400 mV
[8]
tJIT
Additive RMS phase jitter (Random)
Output rise/fall time
156.25 MHz sinewave,
12 kHz to 20 MHz offset; input
swing = 2.2V, Vbias = VDD/2
[9]
tR, tF
50% duty cycle at input,
20% to 80% of full swing
–
–
300
ps
(VOL to VOH
)
Input rise/fall time < 1.5 ns
(20% to 80%)
tSOD
tSOE
Time from clock edge to outputs
disabled
Synchronous clock enable
(CLK_EN) switched Low
–
–
–
–
700
700
ps
ps
Time from clock edge to outputs
enabled
Synchronous clock enable
(CLK_EN) switched high
Notes
5. Refer to Figure 3 on page 7.
6. Refer to Figure 4 on page 7.
7. Refer to Figure 5 on page 7.
8. Refer to Figure 6 on page 8.
9. Refer to Figure 7 on page 8.
Document Number: 001-56313 Rev. *F
Page 6 of 13
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CY2CP1504
Figure 2. Output Differential Voltage
VOH
Q
VPP
Q#
VOL
Figure 3. Input to Any Output Pair Propagation Delay
IN
QX#
QX
tPD
Figure 4. Output Duty Cycle
QX
QX#
tPW
tPERIOD
tPW
tPERIOD
tODC
=
Figure 5. Output-to-Output and Device-to-Device Skew
QX
QX#
QY
Device 1
Device 2
QY#
QZ
tSK1
QZ#
tSK1 D
Document Number: 001-56313 Rev. *F
Page 7 of 13
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CY2CP1504
Figure 6. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
Area Under the Masked Phase Noise Plot
RMS Jitter ∝
Figure 7. Output Rise/Fall Time
QX
80%
80%
VPP
20%
20%
QX#
tR
tF
Figure 8. Synchronous Clock Enable Timing
CLK_EN
INX
tSOD
tPD
tSOE
QX
QX#
Document Number: 001-56313 Rev. *F
Page 8 of 13
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CY2CP1504
Ordering Information
Part Number
Pb-free
Type
Production Flow
Commercial, 0 °C to 70 °C
CY2CP1504ZXC
CY2CP1504ZXCT
CY2CP1504ZXI
CY2CP1504ZXIT
20-Pin TSSOP
20-Pin TSSOP tape and reel
20-Pin TSSOP
Commercial, 0 °C to 70 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
20-Pin TSSOP tape and reel
Ordering Code Definition
CY 2CP15 04 ZX C/I T
Tape and reel
Temperature range
C = Commercial
I = Industrial
Pb-free TSSOP package
Number of differential output pairs
Base part number
Company ID: CY = Cypress
Document Number: 001-56313 Rev. *F
Page 9 of 13
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CY2CP1504
Package Dimension
Figure 9. 20-Pin Thin Shrunk Small Outline Package (4.40-mm Body) ZZ20
51-85118 *C
Document Number: 001-56313 Rev. *F
Page 10 of 13
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CY2CP1504
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Table 3. Units of Measure
Acronym
ESD
Description
electrostatic discharge
Symbol
°C
Unit of Measure
degree Celsius
decibels relative to the carrier
giga hertz
HBM
human body model
dBc
GHz
Hz
kΩ
µA
µF
µs
JEDEC
LVDS
Joint electron devices engineering council
low-voltage differential signal
hertz
LVCMOS
low-voltage complementary metal oxide
semiconductor
kilo ohm
microamperes
micro Farad
microsecond
milliamperes
millisecond
millivolt
LVPECL
LVTTL
OE
low-voltage positive emitter-coupled logic
low-voltage transistor-transistor logic
Output enable
mA
ms
mV
MHz
ns
RMS
root mean square
TSSOP
thin shrunk small outline package
megahertz
nanosecond
ohm
Ω
pF
ps
pico Farad
pico second
volts
V
W
watts
Document Number: 001-56313 Rev. *F
Page 11 of 13
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CY2CP1504
Document History Page
Document Title: CY2CP1504 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Document Number: 001-56313
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
2782891
2838916
CXQ
CXQ
10/09/09
New Datasheet
*A
05/01/2010 Changed status from “ADVANCE” to “PRELIMINARY”.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 5.
Added tPU spec to the Operating Conditions table on page 3.
Changed max IDD spec in the DC Electrical Specs table on page 4 from 60
mA to 61 mA.
Changed VOH in the DC Electrical Specs table on page 4: minimum from VDD
- 1.15V to VDD - 1.20V; maximum from VDD - 0.75V to VDD - 0.70V.
Removed VOD spec from the DC Electrical Specs table on page 4.
Added RP spec in the DC Electrical Specs table on page 4. Min = 60 kΩ, Max
= 140 kΩ.
Added a measurement definition for CIN in the DC Electrical Specs table on
page 4.
Added VPP spec to the AC Electrical Specs table on page 5. VPP min = 600
mV for DC - 150 MHz and min = 400 mV for 150 MHz to 250 MHz.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to tR and tF specs in the AC Electrical specs table on page 5
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
2, 3, 4, 5 and 7, to be consistent with EROS.
*B
3011766
CXQ
08/20/2010 Changed from 0.25 ps to 0.15 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 6.
Added note 2 to describe IIH and IIL specs.
Removed reference to data distribution from “Functional Description”.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical
Specs table.
Updated package diagram.
Added Acronyms and Ordering Code Definition.
*C
*D
3017258
3100234
CXQ
CXQ
08/27/2010 Corrected Output Rise/Fall time diagram.
11/18/2010 Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Changed CIN condition to “Measured at 10 MHz”.
Removed tR and tF input specs from AC specs table.
Changed tODC from 48/52% to 45/55%, changed condition to “Rail-to-rail input
swing, 50% input duty cycle measured at Vdd/2”.
Changed phase jitter condition to “156.25 MHz sinewave, 12 kHz to 20 MHz
offset; input swing = 2.2V, Vbias = VDD/2 “
Removed tS and tH specs from AC specs table.
*E
*F
3137726
3182321
CXQ
CXQ
01/13/2011 Removed “Preliminary” status heading.
Removed resistors from IN0/IN1 in Logic Block Diagram.
Added Figure 8 to describe TSOE and TSOD
.
02/25/11
Post to external web.
Document Number: 001-56313 Rev. *F
Page 12 of 13
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CY2CP1504
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-56313 Rev. *F
Revised February 25, 2011
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