CY2DL818ZC [CYPRESS]
1:8 Clock Fanout Buffer; 1 ： 8时钟扇出缓冲器
| 型号： | CY2DL818ZC |
| 厂家： | 
CYPRESS |
| 描述： | 1:8 Clock Fanout Buffer |
| 文件： | 总8页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2DL818
1:8 Clock Fanout Buffer
Features
Description
• Low voltage operation
• VDD = 3.3V
• 1:8 fanout
This Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVDS
output pairs.
• Single-input-configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVDS Outputs
• Drives either a 50-ohm or 100-ohm load (selectable)
• Low input capacitance
• Low output skew
• Low propagation delay
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock. The Cypress CY2DL818 is ideal for both
level translations from single-ended to LVDS and/or for the
distribution of LVDS-based clock signals.
• Typical (tpd < 4 ns)
• Packages available include: TSSOP
• Does not exceed Bellcore 802.3 standards
• Operation at => 350 MHz – 700 Mbps
The Cypress CY2DL818 has configurable input and output
functions. The input can be selectable for LVCMOS/LVTTL,
LVPECL, or LVDS signals, while the output drivers support
standard and high-drive LVDS. Drive either a 50-ohm or
100-ohm line with a single part number/device.
Pin Configuration
Block Diagram
37
Q1A
36
Q1B
GND
VDD
VDD
VDD
VDD
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
1
2
3
4
5
6
7
8
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
35
Q2A
34
Q2B
InConfig
CNTRL
33
Q3A
32
INPUT
(LVPECL / LVDS / LVTTL)
Q3B
VDD
GND
9
10
11
31
30
VDD
Q5A
INPUT A
INPUT B
Q4A
10
INPUT A
INPUT B
11
Q4B
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
GND 12
VDD
VDD
28
27
Q5A
Q5B
13
14
15
16
17
18
19
6
InConfig
VDD
26
VDD
VDD
Q6A
Q6B
25
GND
GND
24
23
Q7A
Q7B
38 pin TSSOP
22
21
Q8A
Q8B
7
CNTRL
OUTPUT
(LVDS)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07058 Rev. *B
Revised December 15, 2002
CY2DL818
Pin Description
Pin Number
Pin Name
Pin Standard Interface
Pin Description
1, 9,12,
18,19,20,38
GND
VDD
POWER
Ground
2,3,4,5,8, 13
POWER
Power Supply
14,15,16,17,29
10,11
Input A, Input B(#)
Default: LVPECL / LDVS Differential input pair or single line.
Optional:LVTTL/LVCMOS LVPECL/LVDS default. See InConfig below.
single pin.
37, 36,35,34,
33,32,31, 30,
28,27,26,25,
24,23,22,21
Q1A, Q1B, Q2A, Q2B, LDVS
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B, Q6A, Q6B,
Q7A, Q7B, Q8A, Q8B
Differential Outputs
6
InConfig
LVTTL / LVCMOS
Converts inputs from the default
LVPECL/LVDS
(logic = 0)
To LVTTL/LVCMOS (logic = 1) “default pull-up”
See Figure 5 and Figure 6 for additional information
7
CNTRL
LVTTL / LVCMOS
Converts into a high-speed driver.
Logic = 0 = 100 ohm
Logic = 1 = 50-ohm “default pull-up”
See Figure 7 for additional Information
Output Drive Control for Standard and Bus/B/Hi-Drive
CNTRL
Pin 7 Binary Value
Drive STD
Impedance
100 Ohms
50 Ohms
Output Voltage Value
VO = Voutput
V = 1/2 * VO
V = 2 * VO
0
Standard
1
Hi-drive/Bus/B
100 Ohms
50 Ohms
V = VO
Input Receiver Configuration for Differential or LVTTL/LVCMOS
InCONFIG
Input Receiver Family
Pin 6 Binary Value
Input Receiver Type
1
LVTTL in LVCMOS
LVDS
Single-ended non-inverting, inverting, void of bias resistors.
Low-voltage differential signaling
0
LVPECL
Low-voltage pseudo (positive) emitter coupled logic
Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
LVTTL/LVCMOS INPUT LOGIC
Input Condition
Input B (–) Pin 11
Input Logic
Input
Output Logic Q Pins, Q1A or Q1
Ground
VCC
Input
Input – Bar
Input – Bar
Input
Input A (+) Pin 10
Input B (–) Pin 11
Input A (+) Pin 10
Input A (+) Pin 10
Input B (–) Pin 11
Input A (+) Pin 10
Input B (–) Pin 11
Input – Bar
Input
Input – Bar
Input
Ground
VCC
Input
Input – Bar
Input
Input – Bar
Input – Bar
Input
Input – Bar
Power Supply Characteristics
Parameter
Description
Dynamic Power Supply Current VDD = Max
Test Conditions
Min. Typ. Max.
Unit
ICCD
0.40 0.5 mA/MHz
Input toggling 50% Duty Cycle, Outputs Open
Total Power Supply Current
VDD = Max
IC
Input toggling 50% Duty Cycle, Outputs Open
fL = 100 MHz
40
80
mA
Document #: 38-07058 Rev. *B
Page 2 of 8
CY2DL818
Maximum Ratings[1][2]
Supply Voltage to Ground Potential
(Outputs only)........................................–0.3V to VDD + 0.3V
DC Input Voltage ................................... –0.3V to VDD + 0.3V
DC Output Voltage................................. –0.3V to VDD + 0.9V
Power Dissipation........................................................ 0.75W
Storage Temperature: ................................–65°C to + 150°C
Ambient Temperature:...................................–40°C to +85°C
Supply Voltage to Ground Potential
(Inputs and VCC only)....................................... –0.3V to 4.6V
DC Electrical Characteristics: 3.3V–LVDS Input
Parameter
Description
Conditions
Min.
Typ. Max. Unit
VID
VIC
VIH
VIL
IIH
IIL
Magnitude of Differential Input Voltage
100
600 mV
Common-mode of Differential Input VoltageIVIDI (min. and max.)
IVIDI/2 2.4 – (IVIDI/2)
V
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Guaranteed Logic High Level
Guaranteed Logic Low Level
VDD = Max
2
InConfig/Cntrl Pins
0.8
V
VIN = VDD
VIN = VSS
±10
±10
±20
±20
±20
µA
µA
µA
VDD = Max
II
VDD = Max, VIN = VDD(max.)
DC Electrical Characteristics: 3.3V–LVPECL Input
Parameter
Description
Differential input voltage p-p
Common-Mode Voltage
Input High Current
Conditions
Min.
Typ.
Max.
Unit
mV
V
I VID
VCM
IIH
I
Guaranteed Logic High Level
400
2400
2.25
±20
1.65
VDD = Max
VDD = Max
VIN = VDD
VIN = VSS
±10
±10
µA
µA
IIL
Input Low Current
±20
DC Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input
Parameter
Description
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Input Hysteresis
Conditions
Guaranteed Logic High Level
Guaranteed Logic Low Level
VDD = Max
Min.
Typ.
Max.
Unit
V
VIH
VIL
IIH
2
0.8
1
V
VIN = 2.7V
VIN = 0.5V
µA
µA
µA
V
IIL
VDD = Max
–1
II
VDD = Max., VIN = VDD(Max)
VDD = Min., IIN = -18mA
20
VIK
VH
–0.7
–1.2
80
mV
DC Electrical Characteristics: 3.3V–LVDS OUTPUT
Parame-
Description
ter
Conditions
VDD = 3.3V, VIN = VIH or VIL
Pin Control (pin 7) logic is “FALSE” CL – 10 pF RL and CL to GND
Min. Typ. Max. Unit
0.25 0.55
I VOD
I
Differential Output Voltage p-p
RL = 100
ohm
V
Risetime
Falltime
800 1500 ps
800 1500 ps
defaulting to 100-ohm output
DIfferential 20% to 80%
CL = Cintrinsic and Cexternal
See Figure 3
Risetime
Falltime
Pin Control (pin 7) logic is “TRUE”
setting 50-ohm output drivers
differential 20% to 80%
CL – 10 pF RL and CL to GND RL = 50 ohm
CL = Cintrinsic and Cexternal
See Figure 3
350 600
350 600
–10
ps
ps
IOS
Output Short Circuit
Output Voltage high
Output Voltage low
DOUT = 0V or DOUT- = 0V
mA
VOH
RL = 100
ohm
1550 mV
mV
VOL
925
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07058 Rev. *B
Page 3 of 8
CY2DL818
AC Switching Characteristics @ 3.3 V VDD = 3.3V ±5%, Temperature = –40°C to +85°C
Parameter
tPLH
Description
Propagation Delay – Low to High
Propagation Delay – High to Low
Conditions
Min. Typ
Max Unit
4.5
4.5
ns
ns
tPHL
tSK(0)
Output Skew: Skew between outputs of the same
package (in phase)
200
1.6
ps
ps
ns
tSK(p)
tSK(t)
Pulse Skew: Skew between opposite transitions of the
200
same output (tPHL – tPLH
)
Package Skew: Skew between outputs of different
packages at the same power supply voltage, temperature
and package type.
High Frequency Parametrics
Parameter
Fmax
Description
Conditions
50% duty cycle tW(50-50)
Standard Load Circuit.
LVDS VID = 100 mV
Min.
Typ
Max
400
Unit
Maximum frequency
VDD = 3.3V
MHz
Dj
Deterministic Jitter
50% duty cycle tW(50-50)
Standard Load Circuit.
LVDS VID = 100 mV
50
ps
Idd @ 25°C
Idd (mA) vs. Input Freq. (MHz)
200
180
160
140
120
100
80
High or B Drive Curves
60
Standard Drive Curves
40
20
0
40
140
240
340
440
540
Input Freq. (MHz)
LD 3.135
LD 3.3
LD 3.465
HD 3.135
HD 3.3
HD 3.465
Figure 1. IDD Current vs. Frequency in Low Drive and High Drive Full Load
Document #: 38-07058 Rev. *B
Page 4 of 8
CY2DL818
A
B
TPA
50
TPC
Pulse
10pF
Generator
50
TPB
Standard Termination
V1A
1.4 V
0V Differential
V1B
V0Y
1.0 V
1.4 V
0V Differential
1.0 V
V0Z
TPLH
TPHL
80%
0V Differential
V0Y - V0Z
20%
tR
tF
Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3,4,5,6]
A
T P A
5 0
P u ls e
T P C
5 0
G e n e ra to r
B
T P B
V O C
V O D
S ta n d a rd T e rm in a tio n
N e x t D e v ic e
V I(A )
V I(B )
1 .4 0 V
1 .0 V
V o c (p p )
V D D
V o c (s s )
Figure 3. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[3,4,5,6,7]
Notes:
3. All input pulses are supplied by a frequency generator with the following characteristics: TR and tF ≤ 1 ns; pulse rate = 50 Mpps; pulse width = 10 ± 0.2 ns.
4. RL = 50 ohm/100 ohm ± 1%.
5. CL includes instrumentation and fixture capacitance within 6 mm of the DUT.
6. TPA and B are used for prop delay and Rise/Fall Measurements. TPC is used for VOC measurements only.
7. All outputs should be loaded, used or not, in order to minimize noise and currents.
Document #: 38-07058 Rev. *B
Page 5 of 8
CY2DL818
A
B
TPA
50
TPC
Pulse
10pF
Generator
50
TPB
Standard Termination
100%
80%
VI(A)
VI(B)
1.4V
1.0V
0.0V
20%
0%
tF
tR
Figure 4. Test Circuit and Voltage Definitions for the Differential Output Signal [3,4,5,6]
INPUT A
LVCMOS / LVTTL
INPUT B
GND
InConfig
1
LVTTL/LVCMOS
Figure 5. InConfig Control for LVCMOS Input[8]
LV P E C L &
LV D S
InC o nfig
0
LV D S /L V P E C L
Figure 6. InConfig Control for Differential Input[9]
1 00 O h m s
’V o = V o
’V o = 1 /2 V o
’V o = 2 V o
’V o = V o
0
1
S tan d ard
H i D riv e B
5 0 O h m s
1 00 O h m s
5 0 O h m s
C N T R L
Figure 7. CNTRL Control for Standard or High-drive Drivers[10]
Notes:
8. See Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal on page 2.
9. LVPECL or LVDS differential input value.
10. Standard 100-ohm output impedance: high-drive 50-ohm output impedance.
Document #: 38-07058 Rev. *B
Page 6 of 8
CY2DL818
Ordering Information
Part Number
CY2DL818ZI
Package Type
38-pin TSSOP
Product Flow
Industrial, –40° to 85°C
CY2DL818ZIT
38-pin TSSOP–Tape and Reel
38-pin TSSOP
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
CY2DL818ZC
CY2DL818ZCT
38-pin TSSOP–Tape and Reel
Package Drawing and Dimensions
38-pin TSSOP (4.40 mm body) Z38
51-85151-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07058 Rev. *B
Page 7 of 8
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2DL818
Document Title: CY2DL818 1:8 Clock Fanout Buffer
Document Number: 38-07058
Orig. of
Rev.
**
ECN No. Issue Date Change
Description of Change
115151
117611
122745
05/30/02
09/16/02
12/15/02
EHX
RGL
RBI
New Data Sheet
*A
Changed the figure cross reference in page 2 and added a note 6 in page 5
Added power-up requirements to maximum ratings information.
*B
Document #: 38-07058 Rev. *B
Page 8 of 8
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