CY2XP24ZXI [CYPRESS]
Crystal to LVPECL Clock Generator; 水晶LVPECL时钟发生器
| 型号： | CY2XP24ZXI |
| 厂家： | 
CYPRESS |
| 描述： | Crystal to LVPECL Clock Generator |
| 文件： | 总8页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2XP24
Crystal to LVPECL Clock Generator
Features
Functional Description
■ One LVPECL Output Pair
The CY2XP24 is a PLL (Phase Locked Loop) based high
performance clock generator. It is optimized to generate 10 Gb
Ethernet, Fibre Channel, and other high performance clock
frequencies. It produces an output frequency that is either 6.25
times or 7.5 times the crystal frequency. It uses Cypress’s low
noise VCO technology to achieve less than 1 ps typical RMS
phase jitter, that meets both 10Gb Ethernet, Fibre Channel, and
SATA jitter requirements. The CY2XP24 has a crystal oscillator
interface input and one LVPECL output pair.
■ Selectable Output Frequency: 156.25 MHz or 187.5 MHz
■ External Crystal Frequency: 25 MHz
■ Low RMS Phase Jitter at 156.25 MHz, using 25 MHz crystal
(1.875 MHz to 20 MHz): 0.33 ps (typical)
■ Pb-Free 8-Pin TSSOP Package
■ Supply Voltage: 3.3V or 2.5V
■ Commercial and Industrial Temperature Ranges
Logic Block Diagram
XIN
CLK
External
Crystal
CRYSTAL
OSCILLATOR
PHASE
DETECTOR
VCO
/4
CLK#
XOUT
0 = /25
1 = /30
F_SEL
Pinouts
Figure 1. Pin Diagram - 8 Pin TSSOP
VDD
VSS
XOUT
XIN
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
F_SEL
Table 1. Pin Definitions - 8 Pin TSSOP
Pin Name Type
VDD
VSS
Description
1, 8
2
Power
Power
3.3V or 2.5V power supply. All supply current flows through pin 1
Ground
3, 4
5
XOUT, XIN XTAL Output and Input Parallel resonant crystal interface
F_SEL
CMOS Input
Frequency select. When HIGH, the output frequency is 7.5 times of the
crystal frequency. When LOW, the output frequency is 6.25 times of the
crystal frequency
6,7
CLK#, CLK LVPECL Output
Differential clock output
Cypress Semiconductor Corporation
Document #: 001-15705 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 12, 2009
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CY2XP24
Frequency Table
Inputs
PLL Multiplier Value
Output Frequency (MHz)
Crystal Frequency (MHz)
F_SEL
25
25
1
0
7.5
187.5
6.25
156.25
Absolute Maximum Conditions
Parameter
Description
Supply Voltage
Condition
Min
–0.5
–0.5
–65
Max
4.4
Unit
V
VDD
[1]
VIN
Input Voltage, DC
Relative to VSS
VDD + 0.5
150
V
TS
Temperature, Storage
Temperature, Junction
ESD Protection (Human Body Model)
Flammability Rating
Non operating
°C
°C
V
TJ
135
ESDHBM
UL–94
JEDEC STD 22-A114-B
At 1/8 in.
2000
V–0
100
91
[2]
ΘJA
Thermal Resistance, Junction to Ambient 0 m/s airflow
°C/W
1 m/s airflow
2.5 m/s airflow
87
Operating Conditions
Parameter
Description
Min
3.135
2.375
0
Max
3.465
2.625
70
Unit
V
VDD
TA
3.3V Supply Voltage
2.5V Supply Voltage
V
Ambient Temperature, Commercial
Ambient Temperature, Industrial
°C
°C
ms
-40
85
TPU
Power up time for all VDD to reach minimum specified voltage (ensure power
ramps are monotonic)
0.05
500
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
[3]
IDD
Power Supply Current with
output terminated
VDD = 3.465V, FOUT = 187.5 MHz,
output terminated
–
–
–
–
–
–
–
150
V
VDD = 2.625V, FOUT = 187.5 MHz,
output terminated
–
145
V
V
VOH
LVPECL Output High Voltage
LVPECL Output Low Voltage
VDD = 3.3V or 2.5V, RTERM = 50Ω to
VDD – 2.0V
V
DD –1.15
VDD –0.75
VOL
VDD = 3.3V or 2.5V, RTERM = 50Ω to
VDD – 2.0V
V
DD –2.0
VDD –1.625
1000
V
VOD1
VOD2
LVPECL Peak-to-Peak Output VDD = 3.3V or 2.5V, RTERM = 50Ω to
Voltage Swing VDD – 2.0V
600
mV
mV
LVPECL Output Voltage Swing VDD = 2.5V, RTERM = 50Ω to VDD
(VOH - VOL 1.5V
–
500
1000
)
Note
1. The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3.
I
includes approximately 24 mA of current that is dissipated externally in the output termination resistors.
DD
Document #: 001-15705 Rev. *D
Page 2 of 8
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CY2XP24
DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VOCM
LVPECL Output Common Mode VDD = 2.5V, RTERM = 50Ω to VDD
–
1.2
–
–
V
Voltage (VOH + VOL)/2
1.5V
VIH
VIL
IIH
Input High Voltage
0.7*VDD
–0.3
–
–
–
VDD + 0.3
0.3*VDD
115
V
Input Low Voltage
V
Input High Current
F_SEL = VDD
F_SEL = VSS
–
µA
µA
pF
pF
IIL
Input Low Current
–50
–
–
CIN
CINX
Input Capacitance
15
4.5
Pin Capacitance, XIN & XOUT
AC Electrical Characteristics
Parameter
Description
Output Frequency
Conditions
20% to 80% of full swing
Min
Typ
–
Max
187.5
–
Unit
MHz
ps
FOUT
156.25
[5]
TR, TF
Output Rise/Fall time
RMS Phase Jitter (Random)
Duty Cycle
–
–
500
0.33
–
[8]
TJitter(φ)
156.25 MHz, (1.875–20 MHz), 3.3V
Measured at zero crossing point
–
ps
[9]
TDC
45
–
55
%
TLOCK
Startup Time
Time for CLK to reach valid frequency
measured from the time
–
10
ms
VDD = VDD(min.) or from F_SEL
changing
Recommended Crystal Specifications[6]
Parameter
Description
Min
Max
Unit
Mode
F
Mode of Oscillation
Frequency
Fundamental
25
–
25
50
7
MHz
Ω
ESR
C0
Equivalent Series Resistance
Shunt Capacitance
–
pF
Notes
4. Outputs are terminated with 50Ω to V – 2V. Refer to Figure 2 on page 4 and Figure 3 on page 4.
DD
5. Refer to Figure 7 on page 5.
6. Characterized using an 18 pF parallel resonant crystal.
7. Not 100% tested, guaranteed by design and characterization.
8. Refer to Figure 4 on page 4.
9. Refer to Figure 7 on page 5.
Document #: 001-15705 Rev. *D
Page 3 of 8
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CY2XP24
Parameter Measurements
Figure 2. 3.3V Output Load AC Test Circuit
2V
SCOPE
Z = 50Ω
Z = 50Ω
VDD
LVPECL
CLK
50Ω
50Ω
CLK#
VSS
-1.3V +/- 0.165V
Figure 3. 2.5V Output Load AC Test Circuit
2V
SCOPE
Z = 50Ω
Z = 50Ω
VDD
LVPECL
CLK
50Ω
50Ω
CLK#
VSS
-0.5V +/- 0.125V
Figure 4. Output DC Parameters
VA
CLK
VOD
VOCM = (VA + VB)/2
CLK#
VB
Figure 5. Output Rise and Fall Time
CLK#
80% 80%
20%
20%
CLK
TR
TF
Figure 6. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
Area Under the Masked Phase Noise Plot
RMS Jitter =
Document #: 001-15705 Rev. *D
Page 4 of 8
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CY2XP24
Figure 7. Output Duty Cycle
CLK
TPW
TDC
=
TPERIOD
CLK#
TPW
TPERIOD
Figure 9. LVPECL Output Termination
Application Information
3.3V
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices. Figure 8 illus-
trates a typical filtering scheme. Because all current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
125Ω
125Ω
Z0 = 50Ω
Z0 = 50Ω
CLK
IN
CLK#
84Ω
84Ω
Figure 8. Power Supply Filtering
Crystal Input Interface
The CY2XP24 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are deter-
mined using a 25 MHz 18 pF parallel resonant crystal and are
chosen to minimize the ppm error. Note that the optimal values
for C1 and C2 depend on the parasitic trace capacitance and are
therefore layout dependent.
V
DD
(Pin 8)
3.3V
10µ
V
DD
(Pin 1)
0.1μF
0.01 µF
F
Figure 10. Crystal Input Interface
XIN
C1
30 pF
Termination for LVPECL Output
X1
Device
18 pF Parallel
The CY2XP24 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3V
operation, this data sheet specifies output levels for termination
Crystal
XOUT
C2
27 pF
to V –2.0V. This termination voltage can also be used for V
DD
DD
= 2.5V operation, or it can be terminated to V -1.5V. Note that
DD
it is also possible to terminate with 50 ohms to ground (V ), but
SS
the high and low signal levels differ from the data sheet values.
Termination resistors are best located close to the destination
device. To avoid reflections, trace characteristic impedance (Z )
0
should match the termination impedance. Figure 9 shows a
standard termination scheme.
Document #: 001-15705 Rev. *D
Page 5 of 8
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CY2XP24
Ordering Information
Part Number
CY2XP24ZXC
Package Type
Product Flow
8-Pin TSSOP
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, -40°C to 85°C
Industrial, -40°C to 85°C
CY2XP24ZXCT
CY2XP24ZXI
8-Pin TSSOP–Tape and Reel
8-Pin TSSOP
CY2XP24ZXIT
8-Pin TSSOP–Tape and Reel
Package Drawing and Dimensions
Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
2.90[0.114]
3.10[0.122]
51-85093-*A
Document #: 001-15705 Rev. *D
Page 6 of 8
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CY2XP24
Document History Page
Document Title: CY2XP24 Crystal to LVPECL Clock Generator
Document Number: 001-15705
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
1285703
See ECN
WWZ/KVM/ New data sheet
ARI
*A
*B
1451704
2669117
See ECN
WWZ/AESA Added I-temp devices
03/05/2009
KVM/AESA Changed crystal frequency and output frequencies
Updated phase jitter value
Rise & fall times changed from 350 ps to 500 ps (typ.)
Junction temperature changed from 125°C to 135°C
Changed IIL and IIH values
Entered value for IDD
Removed MSL spec
Changed Data Sheet Status to Final
*C
2700242
04/30/2009
KVM/PYRS Typos: changed VCC to VDD, changed ps to MHz
Changed footnote about external power dissipation
Reformatted AC and DC tables
Changed LVPECL parameters from VPP to VOD and VOCM
Added CINX spec
Added IDD for 2.5V
Added TLOCK timing
Revised text in Application Information section
Changed recommended crystal load capacitor values
*D
2718433
06/12/2009
WWZ/HMT No change. Submit to ECN for product launch.
Document #: 001-15705 Rev. *D
Page 7 of 8
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CY2XP24
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15705 Rev. *D
Revised June 12, 2009
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