CY3619 [CYPRESS]
Very Low Jitter Field and Factory Programmable Clock Generator; 非常低的抖动现场和工厂可编程时钟发生器
| 型号： | CY3619 |
| 厂家： | 
CYPRESS |
| 描述： | Very Low Jitter Field and Factory Programmable Clock Generator |
| 文件： | 总8页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY22180
PRELIMINARY
Very Low Jitter Field and Factory
Programmable Clock Generator
Benefits
Features
• Low period and cycle-to-cycle jitter
— Typical pk-pk period jitter: 60 ps
• InternalPLLgeneratesup to200 MHzoutput. Can generate
custom frequencies from an external crystal or a driven
source.
• Wide output frequency range
• In-house programming of samples and prototype quantities
can be done using the CY3672-USB programmer and
CY3619socketadapter. Productionquantitiesareavailable
through Cypress’s value added distribution partners or by
using third party programmers from BP Microsystems, HiLo
Systems, and others.
— Commercial temperature: 20–200 MHz
— Industrial temperature: 20–166 MHz
• Input frequency range
— External crystal: 10–30 MHz fundamental crystal
— External reference: 10–133 MHz clock
• Integrated phase-locked loop (PLL)
• Field programmable and factory programmed options
• Programmable crystal load capacitor tuning array
• 3.3V operation
• Eliminates the need for expensive and difficult to use
higher-order crystals.
• Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal. Eliminates the need for external CLoad
capacitors.
• Application compatibility in standard and low-power
systems
• Commercial and industrial temperature ranges
• Power down or output enable function
• Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
Pin Configuration
CY22180
8-pin SOIC
PLL
6
1
OUTPUT
DIVIDER
XIN/CLKIN
CXIN
CLKOUT
1
2
3
XIN/CLKIN
VDD
XOUT
NC
8
7
6
PROGRAMMABLE
CONFIGURATION
8
XOUT
CXOUT
5
PD#/OE
CLKOUT
REFOUT
3
4
VSS
REFOUT
5
PD# or OE
2
4
VDD
VSS
Cypress Semiconductor Corporation
Document #: 001-15577 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 10, 2007
CY22180
PRELIMINARY
Pin Description
Pin
Name
XIN/CLKIN
Description
1
2
3
Crystal input or reference clock input.
3.3V power supply.
VDD
PD#/OE
Power down pin, active LOW. If PD# = 0, the PLL and oscillator are powered down
and outputs are weakly pulled low.
Output enable pin, active HIGH. If OE = 1, CLKOUT and REFOUT are enabled.
User has the option of choosing either PD# or OE function.
4
5
6
7
8
VSS
Power supply ground.
REFOUT
CLKOUT
NC
Buffered reference output.
Low jitter clock output.
No connect. Leave this pin floating.
Crystal output. Leave this pin floating if external clock is used.
XOUT
programmed into the CY22180. CyberClocks Online outputs
an industry-standard JEDEC file used for programming the
General Description
The CY22180 is a low jitter clock generator for use in
networking, telecommunication, datacom, consumer
CY22180.
CyberClocks
Online
is
available
at
www.cyberclocksonline.com through user registration. For
more information on the registration process refer to the
CY3672 data sheet.
electronics, and other general purpose applications. The
CY22180 offers a single programmable output and an optional
copy of the input frequency. The on-chip reference oscillator is
designed to run off a 10–30 MHz crystal, or a 10–133 MHz
external clock signal. The output frequency range is 20–200
MHz. The CY22180 comes in an 8-pin SOIC, and requires a
3.3V power supply.
CY3672-USB Programming Kit and CY3619 Socket
Adapter
The Cypress CY3672 FTG programmer and CY3619 socket
adapter are needed to program the CY22180. The socket
adapter comes with small prototype quantities of CY22180.
The CY3619 can be ordered separately, so existing users of
the CY3672-USB programmer need order only the socket
adapters to program the CY22180.
Programming Description
Field Programmable (CY22180FSXC and CY22180FSXI)
The CY22180 is programmed at the package level, that is, in
a programmer socket. The CY22180 is flash technology
based, so the parts can be reprogrammed up to 100 times.
This enables fast and easy design changes and product
updates, and eliminates any issues with old and out-of-date
inventory.
Factory Programmed CY22180
Factory programming is available for volume manufacturing by
Cypress. All requests must be submitted to the local Cypress
Field Application Engineer (FAE) or sales representative.
Once the request has been processed, you will receive a new
part number (dash number) and samples with the
programmed values. This part number will be used for
additional sample requests and production orders.
Samples and small prototype quantities can be programmed
on the CY3672 programmer with the CY3619 socket adapter.
CyberClocks™ Online Software
Additional information on the CY22180 can be obtained from
the Cypress website at www.cypress.com.
CyberClocks Online Software is a web-based software appli-
cation that allows the user to custom-configure the CY22180.
All the parameters in Table 1 given as “Enter Data” can be
Table 1.
Total Xtal Load
Reference
Output
Power-down or Output
Enable
Pin Function
Input Frequency
OutputFrequency
Capacitance
XIN and XOUT
1 and 8
Pin Name
Pin#
XIN and XOUT
1 and 8
CLKOUT
REFOUT
5
PD#/OE
3
6
Unit
MHz
pF
MHz
On or Off
ENTER DATA
Select PD# or OE
ENTER DATA
Program Value
ENTER DATA
ENTER DATA
ENTER DATA
Document #: 001-15577 Rev. **
Page 2 of 8
CY22180
PRELIMINARY
Output Clock (CLKOUT, pin 6)
Product Functions
The output clock can be programmed to any frequency in the
range of 20–200 MHz.
Input Frequency (XIN, pin 1 and XOUT, pin 8)
The input to the CY22180 can be a crystal or a clock. The input
frequency range for crystals is 10 to 30 MHz, and for clock
signals is 10 to 133 MHz.
Reference Output (REFOUT, pin 5)
The reference clock output has the same frequency as the
input clock. This output can be programmed to be enabled
(clock on) or disabled (High-Z, clock off) through CyberClocks
Online software. If this output is not needed, Cypress recom-
mends that users request the disabled (High-Z, Clock Off)
option.
CXIN and CXOUT (pin 1 and pin 8)
The internal load capacitors at pin 1 (CXIN) and pin 8 (CXOUT
)
can be programmed from 12 pF to 60 pF in 0.5-pF increments.
Thus, these programmable capacitors support crystals with CL
values between 6 pF and 30 pF. The crystal CL value, minus
board parasitic capacitance, is the value entered into Cyber-
Clocks Online Software.
Power Down or Output Enable (PD# or OE, pin 3)
The CY22180 can be programmed to include either PD# or OE
function. PD# function can be used to power down the oscil-
lator and PLL. The OE function disables the outputs but does
not turn off the PLL. PD# achieves lower power consumption,
but PLL start up time means that turn-on time is slower than
for OE.
If using a driven reference, CyberClocks Online Software will
set CXIN and CXOUT to the minimum value 12 pF.
Absolute Maximum Ratings
Supply Voltage (VDD)........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-condensing).....–55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter
FNOM
Description
Comments
Min. Typ.
Max.
Unit
Nominal Crystal Frequency
Parallel resonance, fundamental mode,
AT cut
10
–
30
MHz
CLNOM
R1
Nominal Load Capacitance
6
–
–
–
–
30
25
2
pF
Ω
Equivalent Series Resistance (ESR) Fundamental mode
Crystal Drive Level No external series resistor assumed
DL
0.5
mW
Operating Conditions
Parameter
Description
Min. Typ.
Max.
3.45
70
Unit
V
VDD
TA
Supply Voltage
Ambient Commercial Temperature
3.13 3.30
0
–40
–
–
–
–
–
–
–
–
–
–
°C
Ambient Industrial Temperature
Max. Load Capacitance @ pin 5 and pin 6
External Reference Crystal
85
°C
CLOAD
FXIN
FCLKIN
FCLKOUT
10
pF
10
10
20
20
10
30
MHz
MHz
MHz
MHz
MHz
ms
External Reference Clock
133
200
166
133
500
CLKOUT frequency, Commercial Temperature
CLKOUT frequency, Industrial Temperature
REFOUT frequency
FREFOUT
TPU
Power-up time for all VDDs to reach minimum specified voltage (power ramp 0.05
must be monotonic)
Document #: 001-15577 Rev. **
Page 3 of 8
CY22180
PRELIMINARY
l
DC Electrical Characteristics
Parameter
Description
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Condition
Min
10
Typ
12
12
–
Max
Unit
mA
mA
V
I
I
V
V
= V – 0.5V, V = 3.3V (source)
DD DD
OH
OL
OH
OL
= 0.5V, V = 3.3V (sink)
10
DD
V
V
I
CMOS levels, 70% of V
CMOS levels, 30% of V
0.7V
V
+ 0.3
IH
DD
DD
DD
DD
–0.3
–
–
0.3V
V
IL
DD
Input High Current, PD#/OE V = V
DD
–
10
10
55
10
–
μA
μA
μA
μA
pF
pF
pF
IH
IN
I
Input Low Current, PD#/OE V = V , pull up disabled
–
–
IL
IN
IN
SS
V
= V , pull up enabled
–
–
SS
I
Output Leakage Current
Three-state output, PD#/OE = 0
–10
–
OZ
[1]
C
or C
Programmable Capacitance Capacitance at minimum setting
at pin 1 and pin 8
12
60
5
XIN
XOUT
Capacitance at maximum setting
–
–
[1]
C
Input Capacitance at
PD#/OE
–
7
IN
I
I
Supply Current
Standby current
f
= 10 MHz, f = 33 MHz, REFOUT off
OUT
–
–
11
10
15
40
mA
DD
IN
Device powered down with PD# = 0V (driven
reference pulled down)
μA
DDS
AC Electrical Characteristics[1]
Parameter
DC
Description
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
Condition
Min
45
Typ
50
Max
55
Unit
%
CLKOUT < 125 MHz, Measured at VDD/2
CLKOUT > 125 MHz, Measured at VDD/2
40
50
60
%
REFOUT, Measured at VDD/2
Duty Cycle of CLKIN = 50%
45
50
55
%
SR1
SR2
TPJ1
TPJ2
Rising Edge Slew Rate
Falling Edge Slew Rate
CLKOUT from 20 to 200 MHz;
REFOUT from 10 to 133 MHz. 20%–80% of VDD
2
2
–
–
–
–
–
–
–
–
3
3
–
–
–
–
–
–
–
–
–
–
V/ns
V/ns
ps
CLKOUT from 20 to 200 MHz;
REFOUT from 10 to 133 MHz. 80%–20% of VDD
[2, 3]
[2, 3]
CLKOUT pk-pk Period
Jitter, REFOUT off
CLKOUT = 20–200 MHz
75
(±38)
CLKOUT pk-pk Period
Jitter, REFOUT off, specific 106.25, 125, 133, or 200 MHz
frequencies
CLKIN = 10 MHz, CLKOUT = 20, 33, 66, 80,
60
(±30)
ps
CLKIN = 25 MHz, CLKOUT = 125 MHz
56
(±28)
ps
CLKIN = 30 MHz, CLKOUT = 33, 66, 80, 106.25,
125, or 133 MHz
62
(±31)
ps
CLKIN = 66 MHz, CLKOUT = 33 or 66 MHz
47
(±24)
ps
CLKIN = 66 MHz, CLKOUT = 80, 106.25, 125,
133, 166, or 200 MHz
68
(±34)
ps
CLKIN = 133 MHz, CLKOUT = 33, 66, or 80 MHz
68
(±34)
ps
CLKIN = 133 MHz,
52
ps
CLKOUT = 125, 133, or 166 MHz
(±26)
Notes
1. Guaranteed by characterization, not 100% tested.
2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, temperature, and output
load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions”.
3. Cycle-to-Cycle Jitter (peak) is always less than Period Jitter (peak-to-peak). Peak-to-Peak Period Jitter is the difference between the shortest and longest
measured periods.
Document #: 001-15577 Rev. **
Page 4 of 8
CY22180
PRELIMINARY
AC Electrical Characteristics[1]
Parameter
Description
Condition
Min
Typ
Max
Unit
[2, 3]
TPJ3
CLKOUT pk-pk Period
Jitter, REFOUT on
CLKOUT = 20–200 MHz
–
150
(±75)
–
ps
[2, 3]
TPJ4
tSTP
REFOUT pk-pk Period Jitter REFOUT = 10-133 MHz
–
–
–
–
–
–
–
265
(±133)
ps
ns
Power Down Time
(pin 3 = PD#)
Time from falling edge on PD# to stopped outputs
(Asynchronous)
150
150
150
3.5
2
350
350
350
5
TOE1
TOE2
tPU1
tPU2
Output Disable Time
(pin 3 = OE)
Time from falling edge on OE to stopped outputs
(Asynchronous)
ns
Output Enable Time
(pin 3 = OE)
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
ns
Power Up Time,
Crystal is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
ms
ms
Power Up Time,
Reference clock is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous), reference clock at
correct frequency
3
Application Circuits[4, 5]
Crystal
no
connect
CLKIN
Power
8
7
6
5
1
2
3
4
8
7
6
5
XIN/CLKIN
VDD
1
2
3
4
XOUT
NC
XIN/CLKIN
VDD
XOUT
Power
no
connect
no
connect
NC
CLKOUT
REFOUT
0.1uF
0.1uF
CY22180
CY22180
PD#/OE
VSS
PD#/OE
VSS
CLKOUT
REFOUT
VDD or
control
VDD or
control
Notes
4. Since the load capacitors (C
and C
) are provided by the CY22180, no external capacitors are needed on the XIN and XOUT pins to match the crystal
XOUT
XIN
load capacitor (C ). Only a single 0.1-μF bypass capacitor is required on the V pin.
L
DD
5. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected).
Document #: 001-15577 Rev. **
Page 5 of 8
CY22180
PRELIMINARY
Switching Waveforms
Figure 1. Duty Cycle Timing (DC = t1A/t1B
)
t
1B
t
1A
OUTPUT
Figure 2. Output Rise/Fall Time (CLKOUT and REFOUT)
OUTPUT
VDD
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x V )/SR1 (or SR3)
DD
Output Fall time (Tf) = (0.6 x V )/SR2 (or SR4)
DD
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 3. Power Down Timing and Power Up Timing
VDD
VIH
POWER
DOWN
VIL
tPU
0V
High Impedance
CLKOUT
(Asynchronous
)
tSTP
Figure 4. Output Enable/Disable Timing
VDD
VIH
OUTPUT
TOE2
ENABLE
VIL
0V
High Impedance
CLKOUT
(Asynchronous
)
TOE1
Document #: 001-15577 Rev. **
Page 6 of 8
CY22180
PRELIMINARY
Ordering Information
Part Number[6]
Description
Product Flow
CY22180FSXC
CY22180FSXI
CY22180SXC-xxx
CY22180SXC-xxxT
CY22180SXI-xxx
CY22180SXI-xxxT
CY3672-USB
Field Programmable, Pb-free
Field Programmable, Pb-free
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
n/a
Factory Programmed, Pb-free
Factory Programmed, Tape and Reel - Pb-free
Factory Programmed, Pb-free
Factory Programmed, Tape and Reel - Pb-free
FTG programmer
CY3619
CY22180FSXC and CY22180FSXI Socket adapter
n/a
Package Diagrams
Figure 5. 8-Lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Note
6. “xxx” denotes the assigned product dash number for devices that are factory-programmed.
Document #: 001-15577 Rev. **
Page 7 of 8
CY22180
PRELIMINARY
Document History Page
Document Title: CY22180 Very Low Jitter Field and Factory Programmable Clock Generator
Document Number: 001-15577
Orig. of
REV.
ECN NO. Issue Date
1058460 See ECN
Description of Change
Change
**
KVM/
New Data Sheet
KKVTMP
Document #: 001-15577 Rev. **
Page 8 of 8
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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