CY3686_技术文档

CY7C68033/CY7C68034

EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller

• Integrated, industry-standard enhanced 8051

CY7C68033/CY7C68034 Silicon Features

— 48-MHz, 24-MHz, or 12-MHz CPU operation

• Certified compliant for Bus- or Self-powered USB 2.0

operation (TID# 40490118)

— Four clocks per instruction cycle

— Three counter/timers

• Single-chip, integrated USB 2.0 transceiver and smart SIE

• Ultra low power – 43 mA typical current draw in any mode

• Enhanced 8051 core

— Expanded interrupt system

— Two data pointers

— Firmware runs from internal RAM, which is downloaded

from NAND flash at startup

• 3.3V operation with 5V tolerant inputs

• Vectored USB interrupts and GPIF/FIFO interrupts

— No external EEPROM required

• 15 KBytes of on-chip Code/Data RAM

— Default NAND firmware ~8 kB

— Default free space ~7 kB

• Separate data buffers for the Set-up and Data portions of a

CONTROL transfer

• Integrated I²C™ controller, runs at 100 or 400 kHz

• Four integrated FIFOs

— Integrated glue logic and FIFOs lower system cost

— Automatic conversion to and from 16-bit buses

— Master or slave operation

• Four programmable BULK/INTERRUPT/ISOCHRONOUS

endpoints

— Buffering options: double, triple, and quad

• Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

— Uses external clock or asynchronous strobes

— Easy interface to ASIC and DSP ICs

• Available in space saving, 56-pin QFN package

• SmartMedia Standard Hardware ECC generation with 1-bit

correction and 2-bit detection

CY7C68034 Only Silicon Features:

• Ideal for battery powered applications

— Suspend current: 100 μA (typ.)

• GPIF (General Programmable Interface)

— Allows direct connection to most parallel interfaces

— Programmable waveform descriptors and configuration

registers to define waveforms

CY7C68033 Only Silicon Features:

• Ideal for non-battery powered applications

— Suspend current: 300 μA (typ.)

— SupportsmultipleReady(RDY)inputsandControl(CTL)

outputs

• 12 fully-programmable GPIO pins

High-performance,

enhanced 8051 core

with low power options

24 MHz

Ext. Xtal

Block Diagram

NX2LP-Flex

/0.5

/1.0

/2.0

8051 Core

x20

2

12/24/48 MHz,

four clocks/cycle

PLL

I C

Master

V

CC

Connected for

full-speed USB

Additional I/Os

1.5k

NAND

Boot Logic

(ROM)

GeneralProgrammable

I/F to ASIC/DSP or bus

standards such as 8-bit

GPIF

NAND, EPP, etc.

RDY (2)

CTL (3)

USB

2.0

XCVR

D+

D–

15 kB

RAM

CY

Smart

USB

ECC

1.1/2.0

Engine

Up to 96 MB/s burst rate

Integrated full- and

high-speed XCVR

4 kB

8/16

FIFO

‘Soft Configuration’ enables

easy firmware changes

FIFO and USB endpoint memory

(master or slave modes)

Enhanced USB core

simplifies 8051 code

Cypress Semiconductor Corporation

Document #: 001-04247 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 21, 2006

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CY7C68033/CY7C68034

Default NAND Firmware Features

quick configuration of some features to decrease design effort

and increase time-to-market advantages.

Because the NX2LP-Flex™ is intended for NAND

Flash-based USB mass storage applications, a default

firmware image is included in the development kit with the

following features:

Overview

Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB

NX2LP-Flex (CY7C68033/CY7C68034) is a firmware-based,

• High (480-Mbps) or full (12-Mbps) speed USB support

• Both common NAND page sizes supported

— 512 bytes for up to 1 Gb capacity

programmable version

(CY7C68023/CY7C68024), which is

of the

EZ-USB NX2LP™

a

fixed-function,

low-power USB 2.0 NAND Flash controller. By integrating the

— 2K bytes for up to 8 Gb capacity

USB 2.0 transceiver, serial interface engine (SIE), enhanced

8051 microcontroller, and

a programmable peripheral

• 12 configurable general-purpose I/O (GPIO) pins

— 2 dedicated chip enable (CE#) pins

— 6 configurable CE#/GPIO pins

interface in a single chip, Cypress has created a very

cost-effective solution that enables feature-rich NAND

Flash-based applications.

The ingenious architecture of NX2LP-Flex results in USB data

transfer rates of over 53 Mbytes per second, the

maximum-allowable USB 2.0 bandwidth, while still using a

low-cost 8051 microcontroller in a small 56-pin QFN package.

Because it incorporates the USB 2.0 transceiver, the

NX2LP-Flex is more economical, providing a smaller footprint

solution than external USB 2.0 SIE or transceiver implemen-

tations. With EZ-USB NX2LP-Flex, the Cypress Smart SIE

handles most of the USB 1.1 and 2.0 protocol, freeing the

embedded microcontroller for application-specific functions

and decreasing development time while ensuring USB

compatibility.

• Up to 8 NAND Flash single-device (single-die) chips are

supported

• Up to 4 NAND Flash dual-device (dual-die) chips are

supported

• Compile option allows unused CE# pins to be config-

ured as GPIOs

— 4 dedicated GPIO pins

• Industry standard ECC NAND Flash correction

— 1-bit per 256-bit correction

— 2-bit error detection

The General Programmable Interface (GPIF) and

Master/Slave Endpoint FIFO (8- or 16-bit data bus) provide an

easy and glueless interface to popular interfaces such as

UTOPIA, EPP, I²C, PCMCIA, and most DSP processors.

• Industry standard (SmartMedia) page management for

wear leveling algorithm, bad block handling, and Physical

to Logical management.

• 8-bit NAND Flash interface support

• Support for 30-ns, 50-ns, and 100-ns NAND Flash timing

Applications

• Complies with the USB Mass Storage Class Specification

revision 1.0

The NX2LP-Flex allows designers to add extra functionality to

basic NAND Flash mass storage designs, or to interface them

with other peripheral devices. Applications may include:

The default firmware image implements a USB 2.0 NAND

Flash controller. This controller adheres to the Mass Storage

Class Bulk-Only Transport Specification. The USB port of the

NX2LP-Flex is connected to a host computer directly or via the

downstream port of a USB hub. Host software issues

commands and data to the NX2LP-Flex and receives status

and data from the NX2LP-Flex using standard USB protocol.

• NAND Flash-based GPS devices

• NAND Flash-based DVB video capture devices

• Wireless pointer/presenter tools with NAND Flash storage

• NAND Flash-based MPEG/TV conversion devices

• Legacy conversion devices with NAND Flash storage

• NAND Flash-based cameras

The default firmware image supports industry leading 8-bit

NAND Flash interfaces and both common NAND page sizes

of 512 and 2k bytes. Up to eight chip enable pins allow the

NX2LP-Flex to be connected to up to eight single- or four

dual-die NAND Flash chips.

• NAND Flash mass storage device with biometric (e.g.,

fingerprint) security

• Home PNA devices with NAND Flash storage

• Wireless LAN with NAND Flash storage

• NAND Flash-based MP3 players

Complete source code and documentation for the default

firmware image are included in the NX2LP-Flex development

kit to enable customization for meeting design requirements.

Additionally, compile options for the default firmware allow for

• LAN networking with NAND Flash storage

Document #: 001-04247 Rev. *D

Page 2 of 33

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CY7C68033/CY7C68034

Figure 1. Example DVB Block Diagram

8051 Microprocessor

The 8051 microprocessor embedded in the NX2LP-Flex has

256 bytes of register RAM, an expanded interrupt system and

three timer/counters.

Buttons

NAND-Based

DVB Unit

8051 Clock Frequency

NX2LP-Flex has an on-chip oscillator circuit that uses an

external 24-MHz (±100-ppm) crystal with the following charac-

teristics:

I/O

CTL

LCD

NX2LP-

Flex

NAND Bank(s)

CE[7:0]

D+/-

I/O

• Parallel resonant

• Fundamental mode

• 500-μW drive level

DVB

Decoder

• 12-pF (5% tolerance) load capacitors.

Audio / Video I/O

An on-chip PLL multiplies the 24-MHz oscillator up to

480 MHz, as required by the transceiver/PHY, and internal

counters divide it down for use as the 8051 clock. The default

8051 clock frequency is 12 MHz. The clock frequency of the

8051 can be changed by the 8051 through the CPUCS

register, dynamically

Figure 2. Example GPS Block Diagram

Buttons

NAND-Based

Figure 3. Crystal Configuration.

GPS Unit

24 MHz

C1

C2

I/O

CTL

LCD

12 pf

NX2LP-

Flex

NAND Bank(s)

CE[7:0]

D+/-

I/O

20 × PLL

GPS

12-pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

Special Function Registers

The “Reference Designs” section of the Cypress web site

provides additional tools for typical USB 2.0 applications. Each

reference design comes complete with firmware source and

object code, schematics, and documentation. Please visit

http://www.cypress.com for more information.

Certain 8051 SFR addresses are populated to provide fast

access to critical NX2LP-Flex functions. These SFR additions

are shown in Table 1. Bold type indicates non-standard,

enhanced 8051 registers. The two SFR rows that end with ‘0’

and ‘8’ contain bit-addressable registers. The four I/O ports

A–D use the SFR addresses used in the standard 8051 for

ports 0–3, which are not implemented in NX2LP-Flex.

Because of the faster and more efficient SFR addressing, the

NX2LP-Flex I/O ports are not addressable in external RAM

space (using the MOVX instruction).

Functional Overview

USB Signaling Speed

NX2LP-Flex operates at two of the three rates defined in the

USB Specification Revision 2.0, dated April 27, 2000:

I²C Bus

• Full speed, with a signaling bit rate of 12 Mbps

• High speed, with a signaling bit rate of 480 Mbps.

NX2LP supports the I²C bus as a master only at 100-/400-kHz.

SCL and SDA pins have open-drain outputs and hysteresis

inputs. These signals must be pulled up to 3.3V, even if no I²C

device is connected. The I²C bus is disabled at startup and

only available for use after the initial NAND access.

NX2LP-Flex does not support the low-speed signaling mode

of 1.5 Mbps.

Document #: 001-04247 Rev. *D

Page 3 of 33

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CY7C68033/CY7C68034

Table 1. Special Function Registers

x

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

8x

IOA

9x

IOB

Ax

Bx

Cx

Dx

Ex

Fx

IOC

IOD

SCON1

SBUF1

PSW

ACC

B

SP

EXIF

INT2CLR

INT4CLR

IOE

DPL0

DPH0

DPL1

DPH1

DPS

MPAGE

OEA

OEB

OEC

OED

OEE

PCON

TCON

TMOD

TL0

SCON0

IE

IP

T2CON

EICON

EIE

EIP

SBUF0

AUTOPTRH1

AUTOPTRL1

RESERVED

AUTOPTRH2

AUTOPTRL2

RESERVED

EP2468STAT

EP24FIFOFLGS

EP68FIFOFLGS

EP01STAT

GPIFTRIG

RCAP2L

RCAP2H

TL2

TL1

TH0

TH1

GPIFSGLDATH

GPIFSGLDATLX

TH2

CKCON

AUTOPTRSET-UP GPIFSGLDATLNOX

Buses

Enumeration

The NX2LP-Flex features an 8- or 16-bit ‘FIFO’ bidirectional

data bus, multiplexed on I/O ports B and D.

During the start-up sequence, internal logic checks for the

presence of NAND Flash with valid firmware. If valid firmware

is found, the NX2LP-Flex loads it and operates according to

the firmware. If no NAND Flash is detected, or if no valid

firmware is found, the NX2LP-Flex uses the default values

from internal ROM space for manufacturing mode operation.

The two modes of operation are described in the section

”Normal Operation Mode” on page 5 and ”Manufacturing

Mode” on page 5.

The default firmware image implements an 8-bit data bus in

GPIF Master mode. It is recommended that additional inter-

faces added to the default firmware image use this 8-bit data

bus.

Document #: 001-04247 Rev. *D

Page 4 of 33

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CY7C68033/CY7C68034

Figure 4. NX2LP-Flex Enumeration Sequence

values stored in ROM space. The default silicon ID values

should only be used for development purposes. Cypress

requires designers to use their own Vendor ID for final

products. A Vendor ID is obtained through registration with the

USB Implementor’s Forum (USB-IF). Also, if the NX2LP-Flex

is used as a mass storage class device, a unique USB serial

number is required for each device in order to comply with the

USB Mass Storage class specification.

Start-up

Cypress provides all the software tools and drivers necessary

for properly programming and testing the NX2LP-Flex. Please

refer to the documentation in the development kit for more

information on these topics.

NAND Flash

Present?

Yes

No

Table 2. Default Silicon ID Values

Default VID/PID/DID

Vendor ID

Product ID

0x04B4 Cypress Semiconductor

0x8613 EZ-USB^®Default

NAND Flash

Programmed?

No

Device release 0xAnnn Depends on chip revision

(nnn = chip revision, where first

silicon = 001)

Yes

ReNumeration™

Load Default

Descriptors and

Configuration Data

Load Firmware

From NAND

Cypress’s ReNumeration™ feature is used in conjunction with

the NX2LP-Flex manufacturing software tools to enable

first-time NAND programming. It is only available when used

in conjunction with the NX2LP-Flex Manufacturing tools, and

is not enabled during normal operation.

Bus-powered Applications

The NX2LP-Flex fully supports bus-powered designs by

enumerating with less than 100 mA, as required by the USB

2.0 specification.

Enumerate

According To

Firmware

Enumerate As

Unprogrammed

NX2LP-Flex

Interrupt System

INT2 Interrupt Request and Enable Registers

NX2LP-Flex implements an autovector feature for INT2 and

INT4. There are 27 INT2 (USB) vectors, and 14 INT4

(FIFO/GPIF) vectors. See the EZ-USB Technical Reference

Manual (TRM) for more details.

Normal Operation

Mode

Manufacturing

Mode

Normal Operation Mode

USB-Interrupt Autovectors

In Normal Operation Mode, the NX2LP-Flex behaves as a

USB 2.0 Mass Storage Class NAND Flash controller. This

includes all typical USB device states (powered, configured,

etc.). The USB descriptors are returned according to the data

stored in the configuration data memory area. Normal read

and write access to the NAND Flash is available in this mode.

The main USB interrupt is shared by 27 interrupt sources. To

save the code and processing time that normally would be

required to identify the individual USB interrupt source, the

NX2LP-Flex provides a second level of interrupt vectoring,

called Autovectoring. When a USB interrupt is asserted, the

NX2LP-Flex pushes the program counter onto its stack then

jumps to address 0x0500, where it expects to find a ‘jump’

instruction to the USB Interrupt service routine.

Manufacturing Mode

In Manufacturing Mode, the NX2LP-Flex enumerates using

the default descriptors and configuration data that are stored

in internal ROM space. This mode allows for first-time

programming of the configuration data memory area, as well

as board-level manufacturing tests.

Developers familiar with Cypress’s programmable USB

devices should note that these interrupt vector values differ

from those used in other EZ-USB microcontrollers. This is due

to the additional NAND boot logic that is present in the

NX2LP-Flex ROM space. Also, these values are fixed and

cannot be changed in the firmware.

Default Silicon ID Values

To facilitate proper USB enumeration when no programmed

NAND Flash is present, the NX2LP-Flex has default silicon ID

Document #: 001-04247 Rev. *D

Page 5 of 33

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Table 3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Source

Priority

1

INT2VEC Value

Notes

0x500

0x504

0x508

0x50C

0x510

0x514

0x518

0x51C

0x520

0x524

0x528

0x52C

0x530

0x534

0x538

0x53C

0x540

0x544

0x548

0x54C

0x550

0x554

0x558

0x55C

0x560

0x564

0x568

0x56C

0x570

0x574

0x578

0x57C

SUDAV

Setup Data Available

2

SOF

Start of Frame (or microframe)

Setup Token Received

3

SUTOK

4

SUSPEND

USB RESET

HISPEED

EP0ACK

USB Suspend request

5

Bus reset

6

Entered high speed operation

NX2LP ACK’d the CONTROL Handshake

Reserved

7

8

9

EP0-IN

EP0-OUT

EP1-IN

EP1-OUT

EP2

EP0-IN ready to be loaded with data

EP0-OUT has USB data

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

EP1-IN ready to be loaded with data

EP1-OUT has USB data

IN: buffer available. OUT: buffer has data

IN-Bulk-NAK (any IN endpoint)

Reserved

EP4

EP6

EP8

IBN

EP0PING

EP1PING

EP2PING

EP4PING

EP6PING

EP8PING

ERRLIMIT

EP0 OUT was Pinged and it NAK’d

EP1 OUT was Pinged and it NAK’d

EP2 OUT was Pinged and it NAK’d

EP4 OUT was Pinged and it NAK’d

EP6 OUT was Pinged and it NAK’d

EP8 OUT was Pinged and it NAK’d

Bus errors exceeded the programmed limit

Reserved

EP2ISOERR

EP4ISOERR

EP6ISOERR

EP8ISOERR

ISO EP2 OUT PID sequence error

ISO EP4 OUT PID sequence error

ISO EP6 OUT PID sequence error

ISO EP8 OUT PID sequence error

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP

register), the NX2LP-Flex substitutes its INT2VEC byte.

Therefore, if the high byte (‘page’) of a jump-table address is

preloaded at location 0x544, the automatically-inserted

INT2VEC byte at 0x545 will direct the jump to the correct

address out of the 27 addresses within the page.

FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual

USB-interrupt sources, the FIFO/GPIF interrupt is shared

among 14 individual FIFO/GPIF sources. The FIFO/GPIF

Interrupt, like the USB Interrupt, can employ autovectoring.

Table 4 shows the priority and INT4VEC values for the 14

FIFO/GPIF interrupt sources.

Document #: 001-04247 Rev. *D

Page 6 of 33

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CY7C68033/CY7C68034

Table 4. Individual FIFO/GPIF Interrupt Sources

Priority

INT4VEC Value

0x580

Source

EP2PF

EP4PF

EP6PF

EP8PF

EP2EF

EP4EF

EP6EF

EP8EF

EP2FF

EP4FF

EP6FF

EP8FF

GPIFDONE

GPIFWF

Notes

1

2

Endpoint 2 Programmable Flag

0x584

Endpoint 4 Programmable Flag

Endpoint 6 Programmable Flag

Endpoint 8 Programmable Flag

Endpoint 2 Empty Flag

Endpoint 4 Empty Flag

Endpoint 6 Empty Flag

Endpoint 8 Empty Flag

Endpoint 2 Full Flag

3

0x588

4

0x58C

0x590

5

6

0x594

7

0x598

8

0x59C

0x5A0

0x5A4

0x5A8

0x5AC

0x5B0

0x5B4

9

10

11

12

13

14

Endpoint 4 Full Flag

Endpoint 6 Full Flag

Endpoint 8 Full Flag

GPIF Operation Complete

GPIF Waveform

If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP

register), the NX2LP-Flex substitutes its INT4VEC byte.

Therefore, if the high byte (‘page’) of a jump-table address is

preloaded at location 0x554, the automatically-inserted

INT4VEC byte at 0x555 will direct the jump to the correct

address out of the 14 addresses within the page. When the

ISR occurs, the NX2LP-Flex pushes the program counter onto

its stack then jumps to address 0x553, where it expects to find

a ‘jump’ instruction to the ISR Interrupt service routine.

reset period must allow for the stabilization of the crystal and

the PLL. This reset period should be approximately 5 ms after

V_CChas reached 3.0V. If the crystal input pin is driven by a

clock signal, the internal PLL stabilizes in 200 μs after V_CChas

reached 3.0V^[1]. Figure 5 shows a power-on reset condition

and a reset applied during operation. A power-on reset is

defined as the time reset is asserted while power is being

applied to the circuit. A powered reset is defined to be when

the NX2LP-Flex has previously been powered on and

operating and the RESET# pin is asserted.

Reset and Wakeup

Cypress provides an application note which describes and

recommends power on reset implementation and can be found

on the Cypress web site. For more information on reset imple-

mentation for the EZ-USB family of products visit the

http://www.cypress.com website.

Reset Pin

The input pin RESET#, will reset the NX2LP-Flex when

asserted. This pin has hysteresis and is active LOW. When a

crystal is used as the clock source for the NX2LP-Flex, the

Figure 5. Reset Timing Plots

RESET#

V_IL

3.3V

3.0V

3.3V

V_CC

0V

T_RESET

Power-on Reset

Powered Reset

Note

1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 μs.

Document #: 001-04247 Rev. *D

Page 7 of 33

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CY7C68033/CY7C68034

Table 5. Reset Timing Values

Figure 6. Internal Code Memory

Condition

T_RESET

FFFF

7.5 kBytes

Power-on Reset with crystal

5 ms

USB registers

and 4 kBytes

FIFO buffers

Power-on Reset with external 200 μs + Clock stability time

clock source

(RD#, WR#)

E200

E1FF

Powered Reset

200 μs

512 Bytes RAM Data

(RD#, WR#)*

E000

Wakeup Pins

The 8051 puts itself and the rest of the chip into a power-down

mode by setting PCON.0 = 1. This stops the oscillator and

PLL. When WAKEUP is asserted by external logic, the oscil-

lator restarts, after the PLL stabilizes, and then the 8051

receives a wakeup interrupt. This applies whether or not

NX2LP-Flex is connected to the USB.

3FFF

15 kBytes RAM

Code and Data

(PSEN#, RD#,

WR#)*

The NX2LP-Flex exits the power-down (USB suspend) state

using one of the following methods:

0500

• USB bus activity (if D+/D– lines are left floating, noise on

these lines may indicate activity to the NX2LP-Flex and

initiate a wakeup).

1 kbyte ROM

0000

*SUDPTR, USB download, NAND boot access

• External logic asserts the WAKEUP pin

• External logic asserts the PA3/WU2 pin.

The second wakeup pin, WU2, can also be configured as a

general purpose I/O pin. This allows a simple external R-C

network to be used as a periodic wakeup source. Note that

WAKEUP is, by default, active LOW.

Register Addresses

Figure 7. Internal Register Addresses

Program/Data RAM

FFFF

4 KBytes EP2-EP8

Internal ROM/RAM Size

buffers

(8 x 512)

The NX2LP-Flex has 1 kBytes ROM and 15 kBytes of internal

program/data RAM, where PSEN#/RD# signals are internally

ORed to allow the 8051 to access it as both program and data

memory. No USB control registers appear in this space.

F000

EFFF

2 KBytes RESERVED

Internal Code Memory

E800

E7FF

E7C0

This mode implements the internal block of RAM (starting at

0x0500) as combined code and data memory, as shown in

Figure 6, below.

64 Bytes EP1IN

E7BF

E780

E77F

E740

64 Bytes EP1OUT

Only the internal and scratch pad RAM spaces have the

following access:

64 Bytes EP0 IN/OUT

E73F

• USB download (only supported by the Cypress Manufac-

turing Tool)

64 Bytes RESERVED

E700

E6FF

8051 Addressable Registers

• Setup data pointer

• NAND boot access.

(512)

E500

E4FF

Reserved (128)

E480

E47F

128 bytes GPIF Waveforms

E400

E3FF

E200

Reserved (512)

E1FF

512 bytes

8051 xdata RAM

E000

Document #: 001-04247 Rev. *D

Page 8 of 33

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CY7C68033/CY7C68034

Endpoint RAM

Setup Data Buffer

A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup

data from a CONTROL transfer.

Size

• 3 × 64 bytes (Endpoints 0 and 1)

• 8 × 512 bytes (Endpoints 2, 4, 6, 8)

Endpoint Configurations (High-speed Mode)

Endpoints 0 and 1 are the same for every configuration.

Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can

be either BULK or INTERRUPT. The endpoint buffers can be

configured in any 1 of the 12 configurations shown in the

vertical columns. When operating in full-speed BULK mode,

only the first 64 bytes of each buffer are used. For example, in

high-speed the max packet size is 512 bytes, but in full-speed

it is 64 bytes. Even though a buffer is configured to be a 512

byte buffer, in full-speed only the first 64 bytes are used. The

unused endpoint buffer space is not available for other opera-

tions. An example endpoint configuration would be:

Organization

• EP0

— Bidirectional endpoint zero, 64-byte buffer

• EP1IN, EP1OUT

— 64-byte buffers, bulk or interrupt

• EP2,4,6,8

— Eight 512-byte buffers, bulk, interrupt, or isochronous.

— EP4 and EP8 can be double buffered, while EP2 and 6

can be either double, triple, or quad buffered.

EP2–1024 double buffered; EP6–512 quad buffered

(column 8 in Figure 8).

For high-speed endpoint configuration options, see Figure 8.

Figure 8. Endpoint Configuration

64

EP0 IN&OUT

EP1 IN

EP1 OUT

EP2

512

EP2

EP2 EP2

EP2

512

EP2

512

EP2

512

1024

512

1024

EP4

512

EP4 EP4

512

EP6

1024

512

EP6

512

EP6

512

EP6

EP6 EP6

EP6

EP6 EP6

512

1024

1024 1024

512

1024

512

EP8

512

EP8

512

EP8

512

EP8

512

EP8

512

1024

512

1024

512

10

11

12

9

4

5

8

1

2

3

6

7

Default Full-Speed Alternate Settings

Table 6. Default Full-Speed Alternate Settings^{[2, 3]}

Alternate Setting

0

64

0

1

2

3

ep0

64

ep1out

ep1in

ep2

64 bulk

64 int

0

64 bulk out (2×)

64 int out (2×)

64 iso out (2×)

Notes

2. ‘0’ means ‘not implemented.’

3. ‘2×’ means ‘double buffered.’

Document #: 001-04247 Rev. *D

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Table 6. Default Full-Speed Alternate Settings^{[2, 3]}(continued)

ep4

ep6

ep8

0

64 bulk out (2×)

64 bulk in (2×)

64 bulk out (2×)

64 int in (2×)

64 bulk out (2×)

64 iso in (2×)

64 bulk in (2×)

Default High-Speed Alternate Settings

Table 7. Default High-Speed Alternate Settings^{[2, 3]}

Alternate Setting

0

1

2

3

ep0

64

0

64

ep1out

ep1in

ep2

512 bulk^[4]

64 int

0

64 int

0

512 bulk out (2×)

512 bulk in (2×)

512 int out (2×)

512 bulk out (2×)

512 int in (2×)

512 bulk in (2×)

512 iso out (2×)

512 bulk out (2×)

512 iso in (2×)

512 bulk in (2×)

ep4

0

ep6

0

ep8

0

External FIFO Interface

(IFCLK), at a rate that transfers data up to 96 Megabytes/s

(48-MHz IFCLK with 16-bit interface).

Architecture

In Slave (S) mode, the NX2LP-Flex accepts an internally

derived clock (IFCLK, max. frequency 48 MHz) and SLCS#,

SLRD, SLWR, SLOE, PKTEND signals from external logic.

Each endpoint can individually be selected for byte or word

operation by an internal configuration bit, and a Slave FIFO

Output Enable signal SLOE enables data of the selected

width. External logic must ensure that the output enable signal

is inactive when writing data to a slave FIFO. The slave

interface must operate asynchronously, where the SLRD and

SLWR signals act directly as strobes, rather than a clock

qualifier as in a synchronous mode. The signals SLRD, SLWR,

SLOE and PKTEND are gated by the signal SLCS#.

The NX2LP-Flex slave FIFO architecture has eight 512-byte

blocks in the endpoint RAM that directly serve as FIFO

memories, and are controlled by FIFO control signals (such as

SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).

In operation, some of the eight RAM blocks fill or empty from

the SIE, while the others are connected to the I/O transfer

logic. The transfer logic takes two forms, the GPIF for internally

generated control signals, or the slave FIFO interface for

externally controlled transfers.

Master/Slave Control Signals

The NX2LP-Flex endpoint FIFOS are implemented as eight

physically distinct 256x16 RAM blocks. The 8051/SIE can

switch any of the RAM blocks between two domains, the USB

(SIE) domain and the 8051-I/O Unit domain. This switching is

done virtually instantaneously, giving essentially zero transfer

time between ‘USB FIFOS’ and ‘Slave FIFOS.’ Since they are

physically the same memory, no bytes are actually transferred

between buffers.

GPIF and FIFO Clock Rates

An 8051 register bit selects one of two frequencies for the

internally supplied interface clock: 30 MHz and 48 MHz. A bit

within the IFCONFIG register will invert the IFCLK signal.

The default NAND firmware image implements a 48-MHz

internally supplied interface clock. The NAND boot logic uses

the same configuration to implement 100-ns timing on the

NAND bus to support proper detection of all NAND Flash

types.

At any given time, some RAM blocks are filling/emptying with

USB data under SIE control, while other RAM blocks are

available to the 8051 and/or the I/O control unit. The RAM

blocks operate as single-port in the USB domain, and

dual-port in the 8051-I/O domain. The blocks can be

configured as single, double, triple, or quad buffered as previ-

ously shown.

GPIF

The GPIF is a flexible 8- or 16-bit parallel interface driven by a

user-programmable finite state machine. It allows the

NX2LP-Flex to perform local bus mastering, and can

implement a wide variety of protocols such as 8-bit NAND

interface, printer parallel port, and Utopia. The default NAND

firmware and boot logic utilizes GPIF functionality to interface

with NAND Flash.

The I/O control unit implements either an internal-master (M

for master) or external-master (S for Slave) interface.

In Master (M) mode, the GPIF internally controls

FIFOADR[1:0] to select a FIFO. The two RDY pins can be

used as flag inputs from an external FIFO or other logic if

desired. The GPIF can be run from an internally derived clock

The GPIF on the NX2LP-Flex features three programmable

control outputs (CTL) and two general-purpose ready inputs

(RDY). The GPIF data bus width can be 8 or 16 bits. Because

Note

4. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.

Document #: 001-04247 Rev. *D

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CY7C68033/CY7C68034

the default NAND firmware image implements an 8-bit data

bus and up to 8 chip enable pins on the GPIF ports, it is recom-

mended that designs based upon the default firmware image

use an 8-bit data bus as well.

ECCM = 0

Two 3-byte ECCs, each calculated over a 256-byte block of

data. This configuration conforms to the SmartMedia Standard

and is used by both the NAND boot logic and default NAND

firmware image.

Each GPIF vector defines the state of the control outputs, and

determines what state a ready input (or multiple inputs) must

be before proceeding. The GPIF vector can be programmed

to advance a FIFO to the next data value, advance an address,

etc. A sequence of the GPIF vectors make up a single

waveform that will be executed to perform the desired data

move between the NX2LP-Flex and the external device.

When any value is written to ECCRESET and data is then

passed across the GPIF or Slave FIFO interface, the ECC for

the first 256 bytes of data will be calculated and stored in

ECC1. The ECC for the next 256 bytes of data will be stored

in ECC2. After the second ECC is calculated, the values in the

ECCx registers will not change until ECCRESET is written

again, even if more data is subsequently passed across the

interface.

Three Control OUT Signals

The NX2LP-Flex exposes three control signals, CTL[2:0].

CTLx waveform edges can be programmed to make transi-

tions as fast as once per clock (20.8 ns using a 48-MHz clock).

ECCM = 1

One 3-byte ECC calculated over a 512-byte block of data.

Two Ready IN Signals

When any value is written to ECCRESET and data is then

passed across the GPIF or Slave FIFO interface, the ECC for

the first 512 bytes of data will be calculated and stored in

ECC1; ECC2 is unused. After the ECC is calculated, the value

in ECC1 will not change until ECCRESET is written again,

even if more data is subsequently passed across the interface

The 8051 programs the GPIF unit to test the RDY pins for

GPIF branching. The 56-pin package brings out two signals,

RDY[1:0].

Long Transfer Mode

In GPIF Master mode, the 8051 appropriately sets GPIF trans-

action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or

GPIFTCB0) for unattended transfers of up to 2³²transactions.

The GPIF automatically throttles data flow to prevent under- or

over-flow until the full number of requested transactions

complete. The GPIF decrements the value in these registers

to represent the current status of the transaction.

Autopointer Access

NX2LP-Flex provides two identical autopointers. They are

similar to the internal 8051 data pointers, but with an additional

feature: they can optionally increment after every memory

access. Also, the autopointers can point to any NX2LP-Flex

register or endpoint buffer space.

I²C Controller

ECC Generation^[5]

NX2LP has one I²C port that the 8051, once running uses to

control external I²C devices. The I²C port operates in master

mode only. The I²C post is disabled at startup and only

available for use after the initial NAND access.

The NX2LP-Flex can calculate ECCs (Error-Correcting

Codes) on data that passes across its GPIF or Slave FIFO

interfaces. There are two ECC configurations:

• Two ECCs, each calculated over 256 bytes (SmartMedia

Standard)

I²C Port Pins

The I²C pins SCL and SDA must have external 2.2-kΩ pull-up

• One ECC calculated over 512 bytes.

resistors even if no EEPROM is connected to the NX2LP.

The two ECC configurations described below are selected by

the ECCM bit. The ECC can correct any one-bit error or detect

any two-bit error.

I²C Interface General-Purpose Access

The 8051 can control peripherals connected to the I²C bus

using the I²CTL and I²DATA registers. NX2LP provides I²C

master control only and is never an I²C slave.

Note

5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.

Document #: 001-04247 Rev. *D

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CY7C68033/CY7C68034

from the default NAND firmware image, which actually utilizes

GPIF Master mode. The signals on the left edge of the ‘Port’

column are common to all modes of the NX2LP-Flex. The

8051 selects the interface mode using the IFCONFIG[1:0]

register bits. Port mode is the power-on default configuration.

Pin Assignments

Figure 9 and Figure 10 identify all signals for the 56-pin

NX2LP-Flex package.

Three modes of operation are available for the NX2LP-Flex:

Port mode, GPIF Master mode, and Slave FIFO mode. These

modes define the signals on the right edge of each column in

Figure 9. The right-most column details the signal functionality

Figure 10 details the pinout of the 56-pin package and lists pin

names for all modes of operation. Pin names with an asterisk

(*) feature programmable polarity.

Figure 9. Port and Signal Mapping

Default NAND

Firmware Use

Port

GPIF Master

Slave FIFO

↔

CE7#/GPIO7

CE6#/GPIO6

CE5#/GPIO5

CE4#/GPIO4

CE3#/GPIO3

CE2#/GPIO2

CE1#

CE0#

DD7

DD6

DD5

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

↔

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

↔

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

XTALIN

DD4

DD3

DD2

DD1

XTALOUT

RESET#

WAKEUP#

SCL

DD0

SDATA

→

R_B1#

R_B2#

→

SLRD

SLWR

→

RDY0

RDY1

→

←

WE#

RE0#

RE1#

←

FLAGA

FLAGB

FLAGC

←

CTL0

CTL1

CTL2

←

→

↔

GPIO1

GPIO0

WP_SW#

WP_NF#

LED2#

LED1#

ALE

PA7

PA6

PA5

↔

←

↔

←

↔

FLAGD/SLCS#/PA7

PKTEND

FIFOADR1

FIFOADR0

PA3/WU2

SLOE

PA1/INT1#

PA0/INT0#

↔

PA7

PA6

PA5

PA4

PA3/WU2

PA2

PA1/INT1#

PA0/INT0#

PA4

WU2/PA3

PA2

INT1#/PA1

INTO#/PA0

DPLUS

DMINUS

CLE

↔

GPIO8

GPIO9

GPIO8

GPIO9

↔

GPIO8

GPIO9

↔

GPIO8

GPIO9

←

Document #: 001-04247 Rev. *D

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CY7C68033/CY7C68034

Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin Assignment

RESET#

RDY0/*SLRD

RDY1/*SLWR

AVCC

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

3

XTALOUT

XTALIN

AGND

4

5

6

CY7C68033/CY7C68034

56-pin QFN

AVCC

7

PA2/*SLOE

PA1/INT1#

DPLUS

8

DMINUS

AGND

9

PA0/INT0#

10

11

12

13

14

VCC

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

GND

GPIO8

RESERVED#

Document #: 001-04247 Rev. *D

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Table 8. NX2LP-Flex Pin Descriptions ^[6]

56 QFN

Number

NAND

Firmware

Usage

DefaultPin

Name

Type

Default

State

Description

9

8

DMINUS

DPLUS

N/A

I/O/Z

Input

Z

USB D– Signal. Connect to the USB D– signal.

USB D+ Signal. Connect to the USB D+ signal.

42

RESET#

N/A

Active LOW Reset. Resets the entire chip. See section ”Reset and

Wakeup” on page 7 for more details.

5

XTALIN

N/A

Input

N/A

Crystal Input. Connect this signal to a 24-MHz parallel-resonant,

fundamental mode crystal and load capacitor to GND.

It is also correct to drive XTALIN with an external 24-MHz square

wave derived from another clock source. When driving from an

external source, the driving signal should be a 3.3V square wave.

4

XTALOUT

GPIO9

N/A

Output

N/A

Crystal Output. Connect this signal to a 24-MHz parallel-resonant,

fundamental mode crystal and load capacitor to GND.

If an external clock is used to drive XTALIN, leave this pin open.

54

1

GPIO9

R_B1#

O/Z

12 MHz GPIO9 is a bidirectional IO port pin.

RDY0 or

SLRD

Input

N/A

H

Multiplexed pin whose function is selected by IFCONFIG[1:0].

RDY0 is a GPIF input signal.

SLRD is the input-only read strobe with programmable polarity

(FIFOPINPOLAR[3]) for the slave FIFOs connected to FD[7:0] or

FD[15:0].

R_B1# is a NAND Ready/Busy input signal.

2

RDY1 or

SLWR

R_B2#

WE#

Input

O/Z

Multiplexed pin whose function is selected by IFCONFIG[1:0].

RDY1 is a GPIF input signal.

SLWR is the input-only write strobe with programmable polarity

(FIFOPINPOLAR[2]) for the slave FIFOs connected to FD[7:0] or

FD[15:0].

R_B2# is a NAND Ready/Busy input signal.

29

CTL0 or

FLAGA

Multiplexed pin whose function is selected by IFCONFIG[1:0].

CTL0 is a GPIF control output.

FLAGA is a programmable slave-FIFO output status flag signal.

Defaults to programmable for the FIFO selected by the

FIFOADR[1:0] pins.

WE# is the NAND write enable output signal.

30

31

CTL1 or

FLAGB

RE0#

RE1#

O/Z

H

Multiplexed pin whose function is selected by IFCONFIG[1:0].

CTL1 is a GPIF control output.

FLAGB is a programmable slave-FIFO output status flag signal.

Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.

RE0# is a NAND read enable output signal.

CTL2 or

FLAGC

Multiplexed pin whose function is selected by IFCONFIG[1:0].

CTL2 is a GPIF control output.

FLAGC is a programmable slave-FIFO output status flag signal.

Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.

RE1# is a NAND read enable output signal.

Note

6. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and in

standby. Note also that no pins should be driven while the device is powered down.

Document #: 001-04247 Rev. *D

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CY7C68033/CY7C68034

Table 8. NX2LP-Flex Pin Descriptions (continued)^[6]

56 QFN

Number

NAND

Firmware

Usage

DefaultPin

Name

Type

Default

State

Description

13

14

15

GPIO8

Reserved#

SCL

GPIO8

N/A

I/O/Z

Input

OD

I

GPIO8: is a bidirectional IO port pin.

N/A

Z

Reserved. Connect to ground.

N/A

Clock for the I²C interface. Connect to VCC with a 2.2K resistor,

even if no I²C peripheral is attached.

16

44

SDATA

N/A

OD

Z

Data for the I²C interface. Connect to VCC with a 2.2K resistor, even

if no I²C peripheral is attached.

WAKEUP

Unused

Input

N/A

USB Wakeup. If the 8051 is in suspend, asserting this pin starts up

the oscillator and interrupts the 8051 to allow it to exit the suspend

mode. Holding WAKEUP asserted inhibits the EZ-USB chip from

suspending. This pin has programmable polarity, controlled by

WAKEUP[4].

Port A

33

PA0 or

INT0#

CLE

ALE

I/O/Z

I

Multiplexed pin whose function is selected by PORTACFG[0]

(PA0) PA0 is a bidirectional IO port pin.

INT0# is the active-LOW 8051 INT0 interrupt input signal, which is

either edge triggered (IT0 = 1) or level triggered (IT0 = 0).

CLE is the NAND Command Latch Enable signal.

34

35

PA1 or

INT1#

I

Multiplexed pin whose function is selected by PORTACFG[1]

(PA1) PA1 is a bidirectional IO port pin.

INT1# is the active-LOW 8051 INT1 interrupt input signal, which is

either edge triggered (IT1 = 1) or level triggered (IT1 = 0).

ALE is the NAND Address Latch Enable signal.

PA2 or

SLOE

LED1#

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PA2) PA2 is a bidirectional IO port pin.

SLOE is an input-only output enable with programmable polarity

(FIFOPINPOLAR[4]) for the slave FIFOs connected to FD[7:0] or

FD[15:0].

LED1# is the data activity indicator LED sink pin.

36

PA3 or

WU2

LED2#

I/O/Z

I

Multiplexed pin whose function is selected by WAKEUP[7] and

(PA3) OEA[3]

PA3 is a bidirectional I/O port pin.

WU2 is an alternate source for USB Wakeup, enabled by WU2EN

bit (WAKEUP[1]) and polarity set by WU2POL (WAKEUP[4]). If the

8051 is in suspend and WU2EN = 1, a transition on this pin starts

up the oscillator and interrupts the 8051 to allow it to exit the suspend

mode. Asserting this pin inhibits the chip from suspending, if

WU2EN = 1.

LED2# is the chip activity indicator LED sink pin.

37

38

PA4 or

FIFOADR0

WP_NF#

WP_SW#

I/O/Z

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PA4) PA4 is a bidirectional I/O port pin.

FIFOADR0 is an input-only address select for the slave FIFOs

connected to FD[7:0] or FD[15:0].

WP_NF# is the NAND write-protect control output signal.

PA5 or

FIFOADR1

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PA5) PA5 is a bidirectional I/O port pin.

FIFOADR1 is an input-only address select for the slave FIFOs

connected to FD[7:0] or FD[15:0].

WP_SW# is the NAND write-protect switch input signal.

Document #: 001-04247 Rev. *D

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Table 8. NX2LP-Flex Pin Descriptions (continued)^[6]

56 QFN

Number

NAND

Firmware

Usage

DefaultPin

Name

Type

Default

State

Description

39

PA6 or

PKTEND

GPIO0

(Input)

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PA6) bits.

PA6 is a bidirectional I/O port pin.

PKTEND is an input used to commit the FIFO packet data to the

endpoint and whose polarity is programmable via FIFOPIN-

POLAR[5].

GPIO1 is a general purpose I/O signal.

40

PA7 or

FLAGD or

SLCS#

GPIO1

(Input)

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PA7) and PORTACFG[7] bits.

PA7 is a bidirectional I/O port pin.

FLAGD is a programmable slave-FIFO output status flag signal.

SLCS# gates all other slave FIFO enable/strobes

GPIO0 is a general purpose I/O signal.

Port B

18

PB0 or

FD[0]

DD0

DD1

DD2

DD3

DD4

DD5

DD6

DD7

I/O/Z

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PB0) PB0 is a bidirectional I/O port pin.

FD[0] is the bidirectional FIFO/GPIF data bus.

DD0 is a bidirectional NAND data bus signal.

19

20

21

22

23

24

25

PB1 or

FD[1]

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PB1) PB1 is a bidirectional I/O port pin.

FD[1] is the bidirectional FIFO/GPIF data bus.

DD1 is a bidirectional NAND data bus signal.

PB2 or

FD[2]

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PB2) PB2 is a bidirectional I/O port pin.

FD[2] is the bidirectional FIFO/GPIF data bus.

DD2 is a bidirectional NAND data bus signal.

PB3 or

FD[3]

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PB3) PB3 is a bidirectional I/O port pin.

FD[3] is the bidirectional FIFO/GPIF data bus.

DD3 is a bidirectional NAND data bus signal.

PB4 or

FD[4]

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PB4) PB4 is a bidirectional I/O port pin.

FD[4] is the bidirectional FIFO/GPIF data bus.

DD4 is a bidirectional NAND data bus signal.

PB5 or

FD[5]

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PB5) PB5 is a bidirectional I/O port pin.

FD[5] is the bidirectional FIFO/GPIF data bus.

DD5 is a bidirectional NAND data bus signal.

PB6 or

FD[6]

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PB6) PB6 is a bidirectional I/O port pin.

FD[6] is the bidirectional FIFO/GPIF data bus.

DD6 is a bidirectional NAND data bus signal.

PB7 or

FD[7]

I

Multiplexed pin whose function is selected by IFCONFIG[1:0].

(PB7) PB7 is a bidirectional I/O port pin.

FD[7] is the bidirectional FIFO/GPIF data bus.

DD7 is a bidirectional NAND data bus signal.

PORT D

45

PD0 or

FD[8]

CE0#

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PD0) and EPxFIFOCFG.0 (wordwide) bits.

FD[8] is the bidirectional FIFO/GPIF data bus.

CE0# is a NAND chip enable output signal.

Document #: 001-04247 Rev. *D

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Table 8. NX2LP-Flex Pin Descriptions (continued)^[6]

56 QFN

Number

NAND

Firmware

Usage

DefaultPin

Name

Type

Default

State

Description

46

PD1 or

FD[9]

CE1#

I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PD1) and EPxFIFOCFG.0 (wordwide) bits.

FD[9] is the bidirectional FIFO/GPIF data bus.

CE1# is a NAND chip enable output signal.

47

PD2 or

FD[10]

CE2# or GPIO2 I/O/Z

CE3# or GPIO3 I/O/Z

CE4# or GPIO4 I/O/Z

CE5# or GPIO5 I/O/Z

CE6# or GPIO6 I/O/Z

CE7# or GPIO7 I/O/Z

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PD2) and EPxFIFOCFG.0 (wordwide) bits.

FD[10] is the bidirectional FIFO/GPIF data bus.

CE2# is a NAND chip enable output signal.

GPIO2 is a general purpose I/O signal.

48

49

50

51

52

PD3 or

FD[11]

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PD3) and EPxFIFOCFG.0 (wordwide) bits.

FD[11] is the bidirectional FIFO/GPIF data bus.

CE3# is a NAND chip enable output signal.

GPIO3 is a general purpose I/O signal.

PD4 or

FD[12]

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PD4) and EPxFIFOCFG.0 (wordwide) bits.

FD[12] is the bidirectional FIFO/GPIF data bus.

CE4# is a NAND chip enable output signal.

GPIO4 is a general purpose I/O signal.

PD5 or

FD[13]

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PD5) and EPxFIFOCFG.0 (wordwide) bits.

FD[13] is the bidirectional FIFO/GPIF data bus.

CE5# is a NAND chip enable output signal.

GPIO5 is a general purpose I/O signal.

PD6 or

FD[14]

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PD6) and EPxFIFOCFG.0 (wordwide) bits.

FD[14] is the bidirectional FIFO/GPIF data bus.

CE6# is a NAND chip enable output signal.

GPIO6 is a general purpose I/O signal.

PD7 or

FD[15]

I

Multiplexed pin whose function is selected by the IFCONFIG[1:0]

(PD7) and EPxFIFOCFG.0 (wordwide) bits.

FD[15] is the bidirectional FIFO/GPIF data bus.

CE7# is a NAND chip enable output signal.

GPIO7 is a general purpose I/O signal.

Power and Ground

3

7

AVCC

AGND

VCC

N/A

Power

Ground

Power

N/A

Analog V_CC. Connect this pin to 3.3V power source. This signal

provides power to the analog section of the chip.

6

10

Analog Ground. Connect to ground with as short a path as

possible.

11

17

27

32

43

55

V_CC. Connect to 3.3V power source.

12

26

28

41

53

56

GND

N/A

Ground

N/A

Ground.

Document #: 001-04247 Rev. *D

Page 17 of 33

[+] Feedback

CY7C68033/CY7C68034

Register Summary

NX2LP-Flex register bit definitions are described in the EZ-USB TRM in greater detail. Some registers that are listed here and in

the TRM do not apply to the NX2LP-Flex. They are kept here for consistency reasons only. Registers that do not apply to the

NX2LP-Flex should be left at their default power-up values.

Table 9. NX2LP-Flex Register Summary

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

GPIF Waveform Memories

E400 128 WAVEDATA

GPIF Waveform

Descriptor 0, 1, 2, 3 data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

E480 128 reserved

GENERAL CONFIGURATION

E50D

GPCR2

General Purpose Configu- reserved

ration Register 2

reserved

FULL_SPEE reserved

D_ONLY

reserved

00000000 R

E600

E601

1

CPUCS

CPU Control & Status

0

1

0

PORTCSTB CLKSPD1 CLKSPD0 CLKINV

CLKOE

IFCFG1

8051RES

IFCFG0

00000010 rrbbbbbr

10000000 RW

IFCONFIG

Interface Configuration

(Ports, GPIF, slave FIFOs)

3048MHZ

0

IFCLKPOL ASYNC

GSTATE

FLAGA2

FLAGC2

EP2

[7]

E602

E603

E604

1

PINFLAGSAB

Slave FIFO FLAGA and FLAGB3

FLAGB Pin Configuration

FLAGB2

FLAGD2

0

FLAGB1

FLAGD1

0

FLAGB0

FLAGD0

0

FLAGA3

FLAGC3

EP3

FLAGA1

FLAGC1

EP1

FLAGA0

FLAGC0

EP0

00000000 RW

PINFLAGSCD

Slave FIFO FLAGC and FLAGD3

FLAGD Pin Configuration

[7]

FIFORESET

Restore FIFOS to default NAKALL

state

xxxxxxxx

W

E605

E606

E607

E608

1

BREAKPT

BPADDRH

BPADDRL

UART230

Breakpoint Control

0

BREAK

A11

A3

BPPULSE BPEN

0

00000000 rrrrbbbr

xxxxxxxx RW

Breakpoint Address H

Breakpoint Address L

A15

A7

0

A14

A6

0

A13

A5

0

A12

A4

0

A10

A2

0

A9

A1

A8

A0

230 Kbaud internally

generated ref. clock

0

230UART1 230UART0 00000000 rrrrrrbb

[7]

E609

1

FIFOPINPOLAR

REVID

Slave FIFO Interface pins 0

polarity

0

PKTEND

SLOE

rv4

SLRD

rv3

SLWR

rv2

EF

FF

00000000 rrbbbbbb

E60A 1

E60B 1

Chip Revision

rv7

rv6

0

rv5

0

rv1

rv0

RevA

00000001

R

[7]

REVCTL

Chip Revision Control

0

dyn_out

enh_pkt

00000000 rrrrrrbb

UDMA

E60C 1

3

GPIFHOLDAMOUNT MSTB Hold Time

(for UDMA)

0

HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb

reserved

ENDPOINT CONFIGURATION

E610

E611

1

EP1OUTCFG

Endpoint 1-OUT

Configuration

VALID

0

TYPE1

TYPE0

0

10100000 brbbrrrr

EP1INCFG

Endpoint 1-IN

Configuration

E612

E613

E614

E615

1

2

1

EP2CFG

EP4CFG

EP6CFG

EP8CFG

reserved

Endpoint 2 Configuration VALID

Endpoint 4 Configuration VALID

Endpoint 6 Configuration VALID

Endpoint 8 Configuration VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

0

BUF0

0

10100010 bbbbbrbb

10100000 bbbbrrrr

11100010 bbbbbrbb

11100000 bbbbrrrr

SIZE

0

BUF1

0

BUF0

0

[7]

E618

E619

EP2FIFOCFG

Endpoint 2/slave FIFO

configuration

0

INFM1

OEP1

AUTOOUT AUTOIN

ZEROLENIN 0

WORDWIDE 00000101 rbbbbbrb

1

EP4FIFOCFG

EP6FIFOCFG

EP8FIFOCFG

reserved

Endpoint 4/slave FIFO

configuration

E61A 1

E61B 1

E61C 4

Endpoint 6/slave FIFO

configuration

Endpoint 8/slave FIFO

configuration

[7

E620

E621

E622

E623

E624

E625

E626

E627

E628

1

EP2AUTOINLENH Endpoint 2 AUTOIN

0

PL10

PL2

0

PL9

PL8

PL0

PL8

PL0

PL8

PL0

PL8

PL0

ECCM

00000010 rrrrrbbb

00000000 RW

Packet Length H

[7]

EP2AUTOINLENL

Endpoint 2 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL1

PL9

PL1

PL9

PL1

PL9

PL1

0

[7]

EP4AUTOINLENH Endpoint 4 AUTOIN

00000010 rrrrrrbb

00000000 RW

Packet Length H

[7]

EP4AUTOINLENL

Endpoint 4 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL2

PL10

PL2

0

[7]

EP6AUTOINLENH Endpoint 6 AUTOIN

00000010 rrrrrbbb

00000000 RW

Packet Length H

[7]

EP6AUTOINLENL

Endpoint 6 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

[7]

EP8AUTOINLENH Endpoint 8 AUTOIN

00000010 rrrrrrbb

00000000 RW

Packet Length H

[7]

EP8AUTOINLENL

ECCCFG

Endpoint 8 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL2

0

ECC Configuration

00000000 rrrrrrrb

Note

7. Read and writes to these registers may require synchronization delay, see the Technical Reference Manual for “Synchronization Delay.”

Document #: 001-04247 Rev. *D

Page 18 of 33

[+] Feedback

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E629

1

ECCRESET

ECC1B0

ECC Reset

x

00000000

W

R

E62A 1

E62B 1

E62C 1

E62D 1

E62E 1

E62F 1

ECC1 Byte 0 Address

ECC1 Byte 1 Address

ECC1 Byte 2 Address

ECC2 Byte 0 Address

ECC2 Byte 1 Address

ECC2 Byte 2 Address

LINE15

LINE7

COL5

LINE15

LINE7

COL5

DECIS

LINE14

LINE6

COL4

LINE14

LINE6

COL4

PKTSTAT

LINE13

LINE5

COL3

LINE13

LINE5

COL3

LINE12

LINE4

COL2

LINE12

LINE4

COL2

LINE11

LINE3

COL1

LINE11

LINE3

COL1

LINE10

LINE2

COL0

LINE10

LINE2

COL0

0

LINE9

LINE1

LINE17

LINE9

LINE1

0

LINE8

LINE0

LINE16

LINE8

LINE0

0

ECC1B1

ECC1B2

ECC2B0

ECC2B1

ECC2B2

[7]

E630

H.S.

1

EP2FIFOPFH

Endpoint 2/slave FIFO

Programmable Flag H

IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

PFC9

PFC8

10001000 bbbbbrbb

E630

F.S.

EP2FIFOPFH

Endpoint 2/slave FIFO

Programmable Flag H

DECIS

PFC7

PKTSTAT

PFC6

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

PFC9

PFC1

0

IN:PKTS[2] 10001000 bbbbbrbb

OUT:PFC8

[7]

E631

H.S.

EP2FIFOPFL

Endpoint 2/slave FIFO

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC0

PFC8

PFC0

PFC8

00000000 RW

E631

F.S

Endpoint 2/slave FIFO

Programmable Flag L

IN:PKTS[1] IN:PKTS[0] PFC5

OUT:PFC7 OUT:PFC6

00000000 RW

E632

H.S.

EP4FIFOPFH

Endpoint 4/slave FIFO

Programmable Flag H

DECIS

PFC7

PKTSTAT

PFC6

0

IN: PKTS[1] IN: PKTS[0] 0

OUT:PFC10 OUT:PFC9

10001000 bbrbbrrb

00000000 RW

[7]

E632

F.S

EP4FIFOPFH

Endpoint 4/slave FIFO

Programmable Flag H

0

OUT:PFC10 OUT:PFC9

0

[7]

E633

H.S.

EP4FIFOPFL

Endpoint 4/slave FIFO

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

0

PFC1

PFC9

PFC1

0

E633

F.S

EP4FIFOPFL

Endpoint 4/slave FIFO

Programmable Flag L

IN: PKTS[1] IN: PKTS[0] PFC5

OUT:PFC7 OUT:PFC6

00000000 RW

E634

H.S.

EP6FIFOPFH

Endpoint 6/slave FIFO

Programmable Flag H

DECIS

PFC7

PKTSTAT

PFC6

IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

00001000 bbbbbrbb

[7]

E634

F.S

EP6FIFOPFH

Endpoint 6/slave FIFO

Programmable Flag H

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

IN:PKTS[2] 00001000 bbbbbrbb

OUT:PFC8

[7]

E635

H.S.

EP6FIFOPFL

Endpoint 6/slave FIFO

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC0

PFC8

PFC0

00000000 RW

E635

F.S

EP6FIFOPFL

Endpoint 6/slave FIFO

Programmable Flag L

IN:PKTS[1] IN:PKTS[0] PFC5

OUT:PFC7 OUT:PFC6

00000000 RW

E636

H.S.

EP8FIFOPFH

Endpoint 8/slave FIFO

Programmable Flag H

DECIS

PFC7

PKTSTAT

PFC6

0

IN: PKTS[1] IN: PKTS[0] 0

OUT:PFC10 OUT:PFC9

00001000 bbrbbrrb

00000000 RW

[7]

E636

F.S

EP8FIFOPFH

Endpoint 8/slave FIFO

Programmable Flag H

0

OUT:PFC10 OUT:PFC9

0

[7]

E637

H.S.

EP8FIFOPFL

reserved

Endpoint 8/slave FIFO

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC1

[7]

E637

F.S

Endpoint 8/slave FIFO

Programmable Flag L

IN: PKTS[1] IN: PKTS[0] PFC5

OUT:PFC7 OUT:PFC6

00000000 RW

8

1

E640

E641

E642

E643

EP2ISOINPKTS

EP4ISOINPKTS

EP6ISOINPKTS

EP8ISOINPKTS

reserved

EP2 (if ISO) IN Packets AADJ

per frame (1-3)

0

INPPF1

INPPF0

00000001 brrrrrbb

00000001 brrrrrrr

00000001 brrrrrbb

00000001 brrrrrrr

1

EP4 (if ISO) IN Packets AADJ

per frame (1-3)

EP6 (if ISO) IN Packets AADJ

per frame (1-3)

EP8 (if ISO) IN Packets AADJ

per frame (1-3)

E644

E648

E649

4

1

7

[7]

INPKTEND

Force IN Packet End

Skip

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

[7]

OUTPKTEND

Force OUT Packet End Skip

INTERRUPTS

[7]

E650

E651

E652

E653

E654

E655

E656

E657

E658

E659

1

EP2FIFOIE

Endpoint 2 slave FIFO

Flag Interrupt Enable

0

EDGEPF

PF

EF

EP1

0

FF

00000000 RW

[7,8]

EP2FIFOIRQ

Endpoint 2 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[7]

EP4FIFOIE

Endpoint 4 slave FIFO

Flag Interrupt Enable

0

EDGEPF

PF

FF

[7,8]

EP4FIFOIRQ

Endpoint 4 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[7]

EP6FIFOIE

Endpoint 6 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

FF

[7,8]

EP6FIFOIRQ

Endpoint 6 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[7]

EP8FIFOIE

Endpoint 8 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

FF

[7,8]

EP8FIFOIRQ

Endpoint 8 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

IBNIE

IN-BULK-NAK Interrupt

Enable

0

EP8

EP4

EP6

EP2

EP4

EP2

EP0

IBN

[8]

IBNIRQ

IN-BULK-NAK interrupt

Request

0

EP4

00xxxxxx rrbbbbbb

00000000 RW

E65A 1

NAKIE

Endpoint Ping-NAK/IBN EP8

Interrupt Enable

EP6

EP1

Note

8. The register can only be reset, it cannot be set.

Document #: 001-04247 Rev. *D

Page 19 of 33

[+] Feedback

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

0

b0

Default

Access

[8]

E65B 1

NAKIRQ

Endpoint Ping-NAK/IBN EP8

Interrupt Request

EP6

EP4

EP2

EP1

EP0

IBN

xxxxxx0x bbbbbbrb

E65C 1

E65D 1

E65E 1

USBIE

USBIRQ

EPIE

USB Int Enables

0

EP0ACK

EP6

HSGRANT URES

SUSP

SUTOK

EP1IN

SOF

SUDAV

EP0IN

00000000 RW

[8]

USB Interrupt Requests

0

SUSP

SOF

0xxxxxxx rbbbbbbb

00000000 RW

Endpoint Interrupt

Enables

EP8

EP4

EP2

EP1OUT

EP0OUT

[8]

E65F 1

EPIRQ

Endpoint Interrupt

Requests

EP8

EP6

EP4

EP2

EP1OUT

EP1IN

EP0OUT

EP0IN

0

RW

[7]

E660

E661

E662

1

GPIFIE

GPIF Interrupt Enable

GPIF Interrupt Request

0

GPIFWF

0

GPIFDONE 00000000 RW

GPIFDONE 000000xx RW

ERRLIMIT 00000000 RW

[7]

GPIFIRQ

0

USBERRIE

USB Error Interrupt

Enables

ISOEP8

ISOEP6

ISOEP4

ISOEP2

[8]

E663

E664

1

USBERRIRQ

ERRCNTLIM

USB Error Interrupt

Requests

ISOEP8

EC3

ISOEP6

EC2

ISOEP4

EC1

ISOEP2

EC0

0

ERRLIMIT 0000000x bbbbrrrb

USB Error counter and

limit

LIMIT3

LIMIT2

LIMIT1

LIMIT0

xxxx0100 rrrrbbbb

E665

E666

1

CLRERRCNT

INT2IVEC

Clear Error Counter EC3:0 x

x

xxxxxxxx

W

R

Interrupt 2 (USB)

Autovector

0

1

0

I2V4

I2V3

I2V2

I2V1

I2V0

0

00000000

E667

1

INT4IVEC

Interrupt 4 (slave FIFO &

GPIF) Autovector

0

I4V3

0

I4V2

0

I4V1

I4V0

0

10000000

R

E668

E669

1

7

INTSET-UP

reserved

Interrupt 2&4 setup

AV2EN

INT4SRC

AV4EN

00000000 RW

INPUT/OUTPUT

PORTACFG

E670

E671

E672

1

I/O PORTA Alternate

Configuration

FLAGD

GPIFA7

GPIFA8

0

SLCS

GPIFA6

T2EX

0

INT1

GPIFA1

T1OUT

0

INT0

00000000 RW

00000000 rrrrrrrb

PORTCCFG

PORTECFG

I/O PORTC Alternate

Configuration

GPIFA5

INT6

0

GPIFA4

GPIFA3

GPIFA2

GPIFA0

T0OUT

EXTCLK

I/O PORTE Alternate

Configuration

RXD1OUT RXD0OUT T2OUT

E673

E677

E678

E679

4

1

XTALINSRC

reserved

I2CS

XTALIN Clock Source

0

2

I C Bus Control & Status START

2

STOP

d6

LASTRD

ID1

d4

0

ID0

d3

0

BERR

d2

ACK

d1

DONE

d0

000xx000 bbbrrrrr

xxxxxxxx RW

00000000 RW

xxxxxxxx RW

I2DAT

I C Bus Data

d7

0

d5

0

2

E67A 1

E67B 1

I2CTL

I C Bus Control

0

STOPIE

D1

400kHz

D0

XAUTODAT1

Autoptr1 MOVX access, D7

when APTREN=1

D6

D5

D4

D3

D2

E67C 1

XAUTODAT2

UDMA CRC

Autoptr2 MOVX access, D7

when APTREN=1

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

[7]

E67D 1

E67E 1

E67F 1

UDMACRCH

UDMA CRC MSB

UDMA CRC LSB

UDMA CRC Qualifier

CRC15

CRC14

CRC6

0

CRC13

CRC5

0

CRC12

CRC4

0

CRC11

CRC3

CRC10

CRC2

CRC9

CRC1

CRC8

CRC0

01001010 RW

10111010 RW

[7]

UDMACRCL

CRC7

UDMACRC-

QUALIFIER

QENABLE

QSTATE

QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb

USB CONTROL

USBCS

E680

E681

E682

E683

E684

E685

E686

E687

E688

1

2

USB Control & Status

Put chip into suspend

HSM

x

0

DISCON

NOSYNSOF RENUM

SIGRSUME x0000000 rrrrbbbb

SUSPEND

WAKEUPCS

TOGCTL

x

xxxxxxxx

W

Wakeup Control & Status WU2

WU

S

WU2POL

WUPOL

0

DPEN

EP2

FC10

FC2

MF2

FA2

WU2EN

EP1

FC9

FC1

MF1

FA1

WUEN

EP0

FC8

FC0

MF0

FA0

xx000101 bbbbrbbb

x0000000 rrrbbbbb

Toggle Control

Q

R

IO

EP3

0

USBFRAMEH

USBFRAMEL

MICROFRAME

FNADDR

USB Frame count H

USB Frame count L

Microframe count, 0-7

USB Function address

0

00000xxx

xxxxxxxx

00000xxx

0xxxxxxx

R

FC7

0

FC6

0

FC5

0

FC4

0

FC3

0

FA6

FA5

FA4

FA3

reserved

ENDPOINTS

[7]

E68A 1

E68B 1

E68C 1

E68D 1

EP0BCH

Endpoint 0 Byte Count H (BC15)

Endpoint 0 Byte Count L (BC7)

(BC14)

BC6

(BC13)

BC5

(BC12)

BC4

(BC11)

BC3

(BC10)

BC2

(BC9)

BC1

(BC8)

BC0

xxxxxxxx RW

[7]

EP0BCL

reserved

EP1OUTBC

Endpoint 1 OUT Byte

Count

0

BC6

BC5

BC4

BC3

BC2

BC1

BC0

0xxxxxxx RW

E68E 1

E68F 1

reserved

EP1INBC

Endpoint 1 IN Byte Count 0

Endpoint 2 Byte Count H

Endpoint 2 Byte Count L BC7/SKIP

BC6

0

BC5

0

BC4

0

BC3

0

BC2

BC10

BC2

BC1

BC9

BC1

BC0

BC8

BC0

0xxxxxxx RW

00000xxx RW

xxxxxxxx RW

[7]

E690

E691

E692

E694

E695

E696

E698

E699

1

2

1

2

1

EP2BCH

0

[7]

EP2BCL

BC6

BC5

BC4

BC3

reserved

[7]

EP4BCH

Endpoint 4 Byte Count H

0

BC9

BC1

BC8

BC0

000000xx RW

xxxxxxxx RW

[7]

EP4BCL

Endpoint 4 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

BC2

reserved

[7]

EP6BCH

Endpoint 6 Byte Count H

0

BC10

BC2

BC9

BC1

BC8

BC0

00000xxx RW

xxxxxxxx RW

[7]

EP6BCL

Endpoint 6 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

E69A 2

E69C 1

E69D 1

reserved

[7]

EP8BCH

Endpoint 8 Byte Count H

0

BC9

BC1

BC8

BC0

000000xx RW

xxxxxxxx RW

[7]

EP8BCL

Endpoint 8 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

BC2

Document #: 001-04247 Rev. *D

Page 20 of 33

[+] Feedback

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E69E 2

E6A0 1

reserved

EP0CS

Endpoint 0 Control and HSNAK

Status

0

BUSY

0

STALL

FF

10000000 bbbbbbrb

00000000 bbbbbbrb

00101000 rrrrrrrb

00000100 rrrrrrrb

E6A1 1

E6A2 1

E6A3 1

E6A4 1

E6A5 1

E6A6 1

E6A7 1

E6A8 1

E6A9 1

E6AA 1

E6AB 1

E6AC 1

E6AD 1

E6AE 1

E6AF 1

E6B0 1

E6B1 1

E6B2 1

E6B3 1

E6B4 1

E6B5 1

EP1OUTCS

EP1INCS

Endpoint 1 OUT Control

and Status

0

Endpoint 1 IN Control and 0

Status

0

EP2CS

Endpoint 2 Control and

Status

0

NPAK2

NPAK1

NPAK0

0

FULL

0

EMPTY

PF

EP4CS

Endpoint 4 Control and

Status

0

NPAK1

0

EP6CS

Endpoint 6 Control and

Status

0

NPAK2

NPAK1

0

EP8CS

Endpoint 8 Control and

Status

0

NPAK1

0

EP2FIFOFLGS

EP4FIFOFLGS

EP6FIFOFLGS

EP8FIFOFLGS

EP2FIFOBCH

EP2FIFOBCL

EP4FIFOBCH

EP4FIFOBCL

EP6FIFOBCH

EP6FIFOBCL

EP8FIFOBCH

EP8FIFOBCL

SUDPTRH

Endpoint 2 slave FIFO

Flags

0

EF

00000010

00000110

00000000

R

Endpoint 4 slave FIFO

Flags

0

PF

EF

FF

Endpoint 6 slave FIFO

Flags

0

PF

EF

FF

Endpoint 8 slave FIFO

Flags

0

PF

EF

FF

Endpoint 2 slave FIFO

total byte count H

0

BC12

BC4

0

BC11

BC3

0

BC10

BC2

BC10

BC2

BC10

BC2

BC10

BC2

A10

A2

BC9

BC1

BC9

BC1

BC9

BC1

BC9

BC1

A9

BC8

BC0

BC8

BC0

BC8

BC0

BC8

BC0

A8

Endpoint 2 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

Endpoint 4 slave FIFO

total byte count H

Endpoint 4 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC4

0

BC3

BC11

BC3

0

Endpoint 6 slave FIFO

total byte count H

Endpoint 6 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC4

0

Endpoint 8 slave FIFO

total byte count H

Endpoint 8 slave FIFO

total byte count L

BC7

BC6

A14

A6

0

BC5

A13

A5

0

BC4

A12

A4

BC3

A11

A3

Setup Data Pointer high A15

address byte

xxxxxxxx RW

SUDPTRL

Setup Data Pointer low ad- A7

dress byte

A1

0

xxxxxxx0 bbbbbbbr

SUDPTRCTL

Setup Data Pointer Auto

Mode

0

SDPAUTO 00000001 RW

2

reserved

E6B8 8

SET-UPDAT

8 bytes of setup data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

R

SET-UPDAT[0] =

bmRequestType

SET-UPDAT[1] =

bmRequest

SET-UPDAT[2:3] = wVal-

ue

SET-UPDAT[4:5] = wInd-

ex

SET-UPDAT[6:7] =

wLength

GPIF

E6C0 1

E6C1 1

GPIFWFSELECT

GPIFIDLECS

Waveform Selector

SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0

FIFORD1

0

FIFORD0

IDLEDRV

11100100 RW

10000000 RW

GPIF Done, GPIF IDLE DONE

drive mode

0

E6C2 1

E6C3 1

E6C4 1

E6C5 1

GPIFIDLECTL

GPIFCTLCFG

Inactive Bus, CTL states

CTL Drive Type

0

CTL5

0

CTL4

0

CTL3

0

CTL2

0

CTL1

0

CTL0

11111111 RW

00000000 RW

TRICTL

0

CTL0

[7]

GPIFADRH

GPIF Address H

0

GPIFA8

GPIFA0

[7]

GPIFADRL

GPIF Address L

GPIFA7

GPIFA6

GPIFA5

GPIFA4

GPIFA3

GPIFA2

GPIFA1

FLOWSTATE

E6C6 1

Flowstate Enable and

Selector

FSE

0

FS2

FS1

FS0

00000000 brrrrbbb

E6C7 1

E6C8 1

FLOWLOGIC

Flowstate Logic

LFUNC1

CTL0E3

LFUNC0

CTL0E2

TERMA2

TERMA1

TERMA0

CTL3

TERMB2

CTL2

TERMB1

CTL1

TERMB0

CTL0

00000000 RW

FLOWEQ0CTL

CTL-Pin States in

Flowstate

(when Logic = 0)

CTL0E1/

CTL5

CTL0E0/

CTL4

E6C9 1

E6CA 1

E6CB 1

E6CC 1

FLOWEQ1CTL

FLOWHOLDOFF

FLOWSTB

CTL-Pin States in Flow- CTL0E3

state (when Logic = 1)

CTL0E2

CTL0E1/

CTL5

CTL0E0/

CTL4

CTL3

CTL2

CTL1

CTL0

00000000 RW

00010010 RW

00100000 RW

00000001 rrrrrrbb

Holdoff Configuration

HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE HOCTL2

0

HOCTL1

MSTB1

FALLING

HOCTL0

MSTB0

RISING

Flowstate Strobe

Configuration

SLAVE

RDYASYNC CTLTOGL

SUSTAIN

0

MSTB2

FLOWSTBEDGE

Flowstate Rising/Falling

Edge Configuration

0

Document #: 001-04247 Rev. *D

Page 21 of 33

[+] Feedback

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E6CD 1

E6CE 1

FLOWSTBPERIOD Master-Strobe Half-PeriodD7

[7]

D6

D5

D4

D3

D2

D1

D0

00000010 RW

00000000 RW

GPIFTCB3

GPIFTCB2

GPIFTCB1

GPIFTCB0

GPIF Transaction Count TC31

Byte 3

TC30

TC29

TC28

TC27

TC26

TC25

TC24

[7]

E6CF 1

E6D0 1

E6D1 1

2

GPIF Transaction Count TC23

Byte 2

TC22

TC14

TC6

TC21

TC13

TC5

TC20

TC12

TC4

TC19

TC11

TC3

TC18

TC10

TC2

TC17

TC9

TC1

TC16

TC8

TC0

00000000 RW

00000001 RW

00000000 RW

GPIF Transaction Count TC15

Byte 1

GPIF Transaction Count TC7

Byte 0

reserved

1

0

x

[7]

E6D2 1

E6D3 1

EP2GPIFFLGSEL

Endpoint 2 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP2GPIFPFSTOP Endpoint 2 GPIF stop

FIFO2FLAG 00000000 RW

transaction on prog. flag

[7]

E6D4 1

3

EP2GPIFTRIG

reserved

Endpoint 2 GPIF Trigger

x

xxxxxxxx

W

reserved

[7]

E6DA 1

E6DB 1

EP4GPIFFLGSEL

Endpoint 4 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP4GPIFPFSTOP Endpoint 4 GPIF stop

FIFO4FLAG 00000000 RW

transaction on GPIF Flag

[7]

E6DC 1

3

EP4GPIFTRIG

reserved

Endpoint 4 GPIF Trigger

x

xxxxxxxx

W

reserved

[7]

E6E2 1

E6E3 1

EP6GPIFFLGSEL

Endpoint 6 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP6GPIFPFSTOP Endpoint 6 GPIF stop

FIFO6FLAG 00000000 RW

transaction on prog. flag

[7]

E6E4 1

3

EP6GPIFTRIG

reserved

Endpoint 6 GPIF Trigger

x

xxxxxxxx

W

reserved

[7]

E6EA 1

E6EB 1

EP8GPIFFLGSEL

Endpoint 8 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP8GPIFPFSTOP Endpoint 8 GPIF stop

FIFO8FLAG 00000000 RW

transaction on prog. flag

[7]

E6EC 1

3

EP8GPIFTRIG

reserved

Endpoint 8 GPIF Trigger

x

xxxxxxxx

W

E6F0 1

XGPIFSGLDATH

GPIF Data H

D15

D14

D6

D13

D12

D4

0

D11

D3

0

D10

D2

0

D9

D1

0

D8

D0

0

xxxxxxxx RW

(16-bit mode only)

E6F1 1

E6F2 1

E6F3 1

XGPIFSGLDATLX

Read/Write GPIF Data L & D7

trigger transaction

D5

XGPIFSGLDATL-

NOX

Read GPIF Data L, no

transaction trigger

D7

D6

D5

xxxxxxxx

R

GPIFREADYCFG

InternalRDY,Sync/Async, INTRDY

RDY pin states

SAS

TCXRDY5

00000000 bbbrrrrr

E6F4 1

E6F5 1

E6F6 2

GPIFREADYSTAT

GPIFABORT

GPIF Ready Status

0

x

0

x

RDY5

x

RDY4

x

RDY3

x

RDY2

x

RDY1

x

RDY0

x

00xxxxxx

xxxxxxxx

R

Abort GPIF Waveforms

W

reserved

ENDPOINT BUFFERS

E740 64 EP0BUF

E780 64 EP10UTBUF

E7C0 64 EP1INBUF

2048 reserved

EP0-IN/-OUT buffer

EP1-OUT buffer

EP1-IN buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

RW

F000 1024 EP2FIFOBUF

512/1024-byte EP 2/slave D7

FIFO buffer (IN or OUT)

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

F400 512 EP4FIFOBUF

512 byte EP 4/slave FIFO D7

buffer (IN or OUT)

xxxxxxxx RW

F600 512 reserved

F800 1024 EP6FIFOBUF

512/1024-byte EP 6/slave D7

FIFO buffer (IN or OUT)

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

FC00 512 EP8FIFOBUF

512 byte EP 8/slave FIFO D7

buffer (IN or OUT)

FE00 512 reserved

xxxx

I²C Configuration Byte

Special Function Registers (SFRs)

0

DISCON

0

400KHZ

xxxxxxxx n/a

[10]

[9]

80

81

82

1

IOA

SP

Port A (bit addressable) D7

D6

A6

D5

A5

D4

A4

D3

A3

D2

A2

D1

A1

D0

A0

xxxxxxxx RW

00000111 RW

00000000 RW

Stack Pointer

D7

A7

DPL0

Data Pointer 0 L

Document #: 001-04247 Rev. *D

Page 22 of 33

[+] Feedback

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

A11

A3

A11

0

b2

A10

A2

A10

0

b1

A9

A1

A9

0

b0

Default

Access

83

84

85

86

87

88

1

DPH0

Data Pointer 0 H

Data Pointer 1 L

Data Pointer 1 H

Data Pointer 0/1 select

Power Control

A15

A7

A14

A6

A14

0

A13

A5

A13

0

A12

A4

A12

0

A8

00000000 RW

00110000 RW

00000000 RW

[9]

DPL1

DPH1

A0

[9]

A15

0

A8

[9]

DPS

SEL

IDLE

IT0

PCON

TCON

SMOD0

TF1

x

1

x

Timer/Counter Control

(bit addressable)

TR1

TF0

TR0

IE1

IT1

IE0

89

1

TMOD

Timer/Counter Mode

Control

GATE

CT

M1

M0

GATE

CT

M1

M0

00000000 RW

8A

8B

8C

8D

8E

8F

90

91

92

1

TL0

Timer 0 reload L

Timer 1 reload L

Timer 0 reload H

Timer 1 reload H

Clock Control

D7

D15

x

D6

D14

x

D5

D4

D3

D2

D1

D0

00000000 RW

00000001 RW

TL1

D5

D4

D3

D2

D1

D0

TH0

D13

T2M

D12

T1M

D11

T0M

D10

MD2

D9

D8

TH1

D9

D8

[9]

CKCON

MD1

MD0

reserved

[9]

IOB

Port B (bit addressable) D7

External Interrupt Flag(s) IE5

D6

D5

D4

D3

1

D2

0

D1

0

D0

0

xxxxxxxx RW

00001000 RW

00000000 RW

[9]

EXIF

IE4

A14

I²CINT

A13

USBNT

A12

[9]

MPAGE

Upper Addr Byte of MOVX A15

using @R0/@R1

A11

A10

A9

A8

93

98

5

1

reserved

SCON0

Serial Port 0 Control

(bit addressable)

SM0_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00000000 RW

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A8

1

5

1

SBUF0

Serial Port 0 Data Buffer D7

Autopointer 1 Address H A15

Autopointer 1 Address L A7

D6

D5

D4

D3

A11

A3

D2

D1

A9

A1

D0

A8

A0

00000000 RW

[9]

AUTOPTRH1

A14

A6

A13

A5

A12

A4

A10

A2

[9]

AUTOPTRL1

reserved

[9]

AUTOPTRH2

Autopointer 2 Address H A15

Autopointer 2 Address L A7

A14

A6

A13

A5

A12

A4

A11

A3

A10

A2

A9

A1

A8

A0

00000000 RW

[9]

AUTOPTRL2

reserved

[9]

IOC

Port C (bit addressable) D7

D6

x

D5

x

D4

x

D3

x

D2

x

D1

x

D0

x

xxxxxxxx RW

[9]

INT2CLR

Interrupt 2 clear

Interrupt 4 clear

x

xxxxxxxx

W

[9]

INT4CLR

x

reserved

IE

Interrupt Enable

(bit addressable)

EA

ES1

ET2

ES0

ET1

EX1

ET0

EX0

00000000 RW

A9

AA

1

reserved

[9]

EP2468STAT

Endpoint 2,4,6,8 status EP8F

flags

EP8E

EP6F

EP6E

EP4F

EP4E

EP2F

EP2E

01011010

00100010

01100110

R

AB

AC

1

EP24FIFOFLGS

[9]

Endpoint 2,4 slave FIFO

status flags

0

EP4PF

EP8PF

EP4EF

EP8EF

EP4FF

EP8FF

0

EP2PF

EP6PF

EP2EF

EP6EF

EP2FF

EP6FF

EP68FIFOFLGS

[9]

Endpoint 6,8 slave FIFO

status flags

0

AD

AF

B0

B1

2

1

reserved

[9]

AUTOPTRSET-UP Autopointer 1&2 setup

[9]

0

APTR2INC APTR1INC APTREN

00000110 RW

xxxxxxxx RW

IOD

Port D (bit addressable) D7

D6

D5

D4

D3

D2

D1

D0

[9]

IOE

Port E

D7

(NOT bit addressable)

[9]

B2

B3

B4

B5

B6

B7

B8

1

OEA

OEB

Port A Output Enable

Port B Output Enable

Port C Output Enable

Port D Output Enable

Port E Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

OEC

OED

[9]

OEE

reserved

IP

Interrupt Priority (bit ad-

dressable)

1

PS1

PT2

PS0

PT1

PX1

PT0

PX0

10000000 RW

B9

BA

1

reserved

[9]

EP01STAT

Endpoint 0&1 Status

0

EP1INBSY EP1OUTBS EP0BSY

Y

00000000 R

[9, 7]

BB

1

GPIFTRIG

Endpoint 2,4,6,8 GPIF

slave FIFO Trigger

DONE

RW

EP1

EP0

10000xxx brrrrbbb

BC

BD

1

reserved

[9]

GPIFSGLDATH

GPIF Data H (16-bit mode D15

only)

D14

D6

D13

D5

D12

D4

D11

D3

D10

D2

D9

D1

D8

D0

xxxxxxxx RW

[9]

BE

1

GPIFSGLDATLX

GPIF Data L w/Trigger

D7

Notes

9. SFRs not part of the standard 8051 architecture.

10. If no NAND is detected by the SIE then the default is 00000000.

Document #: 001-04247 Rev. *D

Page 23 of 33

[+] Feedback

CY7C68033/CY7C68034

Table 9. NX2LP-Flex Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

R

BF

1

GPIFSGLDAT

LNOX

GPIF Data L w/No Trigger D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

[9]

C0

1

SCON1

Serial Port 1 Control (bit SM0_1

addressable)

SM1_1

D6

SM2_1

D5

REN_1

D4

TB8_1

D3

RB8_1

D2

TI_1

D1

RI_1

D0

00000000 RW

[9]

C1

C2

C8

1

6

1

SBUF1

Serial Port 1 Data Buffer D7

reserved

T2CON

Timer/Counter 2 Control TF2

(bit addressable)

EXF2

RCLK

TCLK

EXEN2

TR2

CT2

CPRL2

00000000 RW

C9

CA

1

reserved

RCAP2L

Capture for Timer 2, au- D7

to-reload, up-counter

D6

D5

D4

D3

D2

D1

D0

00000000 RW

CB

1

RCAP2H

Capture for Timer 2, au- D7

to-reload, up-counter

CC

CD

CE

D0

1

2

1

TL2

Timer 2 reload L

Timer 2 reload H

D7

D6

D5

D4

D3

D2

D1

D9

D0

D8

00000000 RW

TH2

D15

D14

D13

D12

D11

D10

reserved

PSW

Program Status Word (bit CY

addressable)

AC

F0

RS1

RS0

OV

F1

P

00000000 RW

D1

D8

D9

E0

7

1

7

1

reserved

[9]

EICON

External Interrupt Control SMOD1

1

ERESI

D5

RESI

D4

INT6

D3

0

01000000 RW

00000000 RW

reserved

ACC

Accumulator (bit address- D7

able)

D6

D2

D1

D0

E1

E8

7

1

reserved

[9]

EIE

External Interrupt En-

able(s)

1

EX6

EX5

EX4

EI²C

EUSB

11100000 RW

E9

F0

F1

F8

7

1

7

1

reserved

B

B (bit addressable)

D7

1

D6

1

D5

1

D4

D3

D2

D1

D0

00000000 RW

11100000 RW

reserved

[9]

EIP

External Interrupt Priority

Control

PX6

PX5

PX4

PI²C

PUSB

F9

7

reserved

R = all bits read-only

W = all bits write-only

r = read-only bit

w = write-only bit

b = both read/write bit

Static Discharge Voltage...........................................>2000V

Max Output Current, per I/O port................................. 10 mA

Absolute Maximum Ratings

Storage Temperature ..................................–65°C to +150°C

Ambient Temperature with Power Supplied......0°C to +70°C

Supply Voltage to Ground Potential............... –0.5V to +4.0V

DC Input Voltage to Any Input Pin ........................ +5.25V^[11]

Operating Conditions

T_A(Ambient Temperature Under Bias)............. 0°C to +70°C

Supply Voltage............................................+3.00V to +3.60V

Ground Voltage.................................................................. 0V

DC Voltage Applied to

Outputs in High Z State......................... –0.5V to V_CC+ 0.5V

F_OSC(Oscillator or Crystal Frequency).... 24 MHz ± 100 ppm

Power Dissipation .....................................................300 mW

(Parallel Resonant)

Note

11. Applying power to I/O pins when the chip is not powered is not recommended.

Document #: 001-04247 Rev. *D

Page 24 of 33

[+] Feedback

CY7C68033/CY7C68034

DC Characteristics

Table 10.DC Characteristics

Parameter

V_CC

V_CCRamp Up 0 to 3.3V

Description

Conditions

Min.

3.00

200

2

Typ.

Max.

Unit

V

Supply Voltage

3.3

3.60

μs

V

V_IH

V_IL

Input HIGH Voltage

5.25

0.8

Input LOW Voltage

–0.5

2

V

V_{IH_X}

V_{IL_X}

I_I

Crystal Input HIGH Voltage

Crystal Input LOW Voltage

Input Leakage Current

Output Voltage HIGH

Output LOW Voltage

Output Current HIGH

Output Current LOW

Input Pin Capacitance

5.25

0.8

V

–0.5

V

0< V_IN< V_CC

I_OUT= 4 mA

±10

μA

V

V_OH

V_OL

I_OH

I_OL

2.4

I_OUT= –4 mA

0.4

4

V

mA

pF

μA

mA

ms

μs

4

C_IN

Except D+/D–

10

D+/D–

15

I_SUSP

Suspend Current

CY7C68034

Connected

300

100

0.5

0.3

43

380^[12]

150^[12]

1.2^[12]

1.0^[12]

Disconnected

Suspend Current

CY7C68033

Connected

Disconnected

I_CC

Supply Current

8051 running, connected to USB HS

8051 running, connected to USB FS

Before bMaxPower granted by host

V_CCmin = 3.0V

35

I_UNCONFIG

T_RESET

Unconfigured Current

43

Reset Time After Valid Power

Pin Reset After powered on

5.0

200

USB Transceiver

USB 2.0-compliant in full- and high-speed modes.

AC Electrical Characteristics

USB Transceiver

USB 2.0-compliant in full- and high-speed modes.

Note

12. Measured at Max V , 25°C.

CC

Document #: 001-04247 Rev. *D

Page 25 of 33

[+] Feedback

CY7C68033/CY7C68034

Slave FIFO Asynchronous Read

Figure 11. Slave FIFO Asynchronous Read Timing Diagram^[13]

t

RDpwh

SLRD

t

RDpwl

t

XFLG

t

FLAGS

XFD

DATA

SLOE

N+1

N

t

OEoff

OEon

Table 11.Slave FIFO Asynchronous Read Parameters^[15]

Parameter Description

t_RDpwlSLRD Pulse Width LOW

Min.

50

Max.

Unit

ns

t_RDpwh

t_XFLG

t_XFD

SLRD Pulse Width HIGH

50

ns

SLRD to FLAGS Output Propagation Delay

70

15

ns

SLRD to FIFO Data Output Propagation Delay

SLOE Turn-on to FIFO Data Valid

ns

t_OEon

t_OEoff

10.5

ns

SLOE Turn-off to FIFO Data Hold

ns

Slave FIFO Asynchronous Write

Figure 12. Slave FIFO Asynchronous Write Timing Diagram^[13]

t

WRpwh

SLWR/SLCS#

t

WRpwl

t

FDH

SFD

DATA

t

XFD

FLAGS

Table 12.Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK ^[15]

Parameter

t_WRpwl

t_WRpwh

t_SFD

Description

Min.

50

Max.

Unit

ns

SLWR Pulse LOW

SLWR Pulse HIGH

70

ns

SLWR to FIFO DATA Setup Time

FIFO DATA to SLWR Hold Time

10

ns

t_FDH

10

ns

t_XFD

SLWR to FLAGS Output Propagation Delay

70

ns

Notes

13. Dashed lines denote signals with programmable polarity.

14. GPIF asynchronous RDY signals have a minimum setup time of 50 ns when using internal 48-MHz IFCLK.

x

15. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.

Document #: 001-04247 Rev. *D

Page 26 of 33

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CY7C68033/CY7C68034

Slave FIFO Asynchronous Packet End Strobe

Figure 13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram^[9]

t

PEpwh

PKTEND

FLAGS

t

PEpwl

t

XFLG

Table 13.Slave FIFO Asynchronous Packet End Strobe Parameters^[15]

Parameter Description

t_PEpwlPKTEND Pulse Width LOW

t_PWpwh

t_XFLG

Min.

50

Max.

Unit

ns

PKTEND Pulse Width HIGH

50

ns

PKTEND to FLAGS Output Propagation Delay

115

ns

Slave FIFO Output Enable

Figure 14. Slave FIFO Output Enable Timing Diagram^[13]

SLOE

t

OEoff

t

OEon

DATA

Table 14.Slave FIFO Output Enable Parameters

Parameter Description

t_OEon

t_OEoff

Min.

Max.

10.5

Unit

ns

SLOE Assert to FIFO DATA Output

SLOE Deassert to FIFO DATA Hold

ns

Slave FIFO Address to Flags/Data

Figure 15. Slave FIFO Address to Flags/Data Timing Diagram^[13]

FIFOADR [1.0]

t

XFLG

FLAGS

DATA

t

XFD

N

N+1

Table 15.Slave FIFO Address to Flags/Data Parameters

Parameter

t_XFLG

t_XFD

Description

FIFOADR[1:0] to FLAGS Output Propagation Delay

FIFOADR[1:0] to FIFODATA Output Propagation Delay

Min.

Max.

10.7

14.3

Unit

ns

Document #: 001-04247 Rev. *D

Page 27 of 33

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CY7C68033/CY7C68034

Slave FIFO Asynchronous Address

Figure 16. Slave FIFO Asynchronous Address Timing Diagram^[13]

SLCS/FIFOADR [1:0]

SLRD/SLWR/PKTEND

t

FAH

t

SFA

Table 16.Slave FIFO Asynchronous Address Parameters^[15]

Parameter

Description

Min.

Max.

Unit

ns

t_SFA

t_FAH

FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time

RD/WR/PKTEND to FIFOADR[1:0] Hold Time

10

ns

Sequence Diagram

Sequence Diagram of a Single and Burst Asynchronous Read

Figure 17. Slave FIFO Asynchronous Read Sequence and Timing Diagram^[13]

t

FAH

SFA

FAH

FIFOADR

t=0

t

RDpwh

t

RDpwh

t

T=0

RDpwl

RDpwh

RDpwl

RDpwh

SLRD

SLCS

t=3

t=2

T=2

T=3

T=5

T=4

T=6

t

XFLG

t

XFLG

FLAGS

DATA

SLOE

t

XFD

t

XFD

t

XFD

Data (X)

Driven

N+3

N

N+1

N+2

N

t

OEon

t

OEoff

OEon

t=4

T=1

T=7

t=1

Figure 18. Slave FIFO Asynchronous Read Sequence of Events Diagram

SLOE

SLRD

SLOE

SLRD

N+1

SLRD

N+1

SLRD

N+2

SLRD

N+2

SLOE

FIFO POINTER

N

N+1

N

N+1

N+3

N+2

N+3

FIFO DATA BUS Not Driven

Driven: X

Not Driven

N

N+1

N+2

Not Driven

Document #: 001-04247 Rev. *D

Page 28 of 33

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CY7C68033/CY7C68034

Figure 17 diagrams the timing relationship of the SLAVE FIFO

signals during an asynchronous FIFO read. It shows a single

read followed by a burst read.

• The data that will be driven, after asserting SLRD, is the

updated data from the FIFO. This data is valid after a propa-

gation delay of t_XFDfrom the activating edge of SLRD. In

Figure 17, data N is the first valid data read from the FIFO.

For data to appear on the data bus during the read cycle

(that is SLRD is asserted), SLOE MUST be in an asserted

state. SLRD and SLOE can also be tied together.

• At t = 0 the FIFO address is stable and the SLCS signal is

asserted.

• At t = 1, SLOE is asserted. This results in the data bus being

driven. The data that is driven on to the bus is previous data,

it data that was in the FIFO from a prior read cycle.

The same sequence of events is also shown for a burst read

marked with T = 0 through 5. Note: In burst read mode, during

SLOE is assertion, the data bus is in a driven state and outputs

the previous data. Once SLRD is asserted, the data from the

FIFO is driven on the data bus (SLOE must also be asserted)

and then the FIFO pointer is incremented.

• At t = 2, SLRD is asserted. The SLRD must meet the

minimum active pulse of t_RDpwland minimum de-active

pulse width of t_RDpwh. If SLCS is used then, SLCS must be

in asserted with SLRD or before SLRD is asserted (that is

the SLCS and SLRD signals must both be asserted to start

a valid read condition).

Sequence Diagram of a Single and Burst Asynchronous Write

Figure 19. Slave FIFO Asynchronous Write Sequence and Timing Diagram^[13]

t

FAH

t

SFA

FAH

FIFOADR

t=0

T=0

t

WRpwh

WRpwl

WRpwh

WRpwl

WRpwh

WRpwl

SLWR

SLCS

t =1

t=3

T=1

T=4

T=3

T=7

T=6

T=9

t

XFLG

t

XFLG

FLAGS

DATA

t

SFD

t

SFD FDH

FDH

N

N+1

N+2

N+3

t=2

T=8

T=2

T=5

t

PEpwl

PEpwh

PKTEND

Figure 19 diagrams the timing relationship of the SLAVE FIFO

write in an asynchronous mode. The diagram shows a single

write followed by a burst write of 3 bytes and committing the

4-byte-short packet using PKTEND.

pointer. The FIFO flag is also updated after t_XFLGfrom the

deasserting edge of SLWR.

The same sequence of events are shown for a burst write and

is indicated by the timing marks of T = 0 through 5. Note: In

the burst write mode, once SLWR is deasserted, the data is

written to the FIFO and then the FIFO pointer is incremented

to the next byte in the FIFO. The FIFO pointer is post incre-

mented.

• At t = 0 the FIFO address is applied, insuring that it meets

the setup time of t_SFA. If SLCS is used, it must also be

asserted (SLCS may be tied low in some applications).

• At t = 1 SLWR is asserted. SLWR must meet the minimum

active pulse of t_WRpwland minimum de-active pulse width

of t_WRpwh. If the SLCS is used, it must be in asserted with

SLWR or before SLWR is asserted.

In Figure 19 once the four bytes are written to the FIFO and

SLWR is deasserted, the short 4-byte packet can be

committed to the host using the PKTEND. The external device

should be designed to not assert SLWR and the PKTEND

signal at the same time. It should be designed to assert the

PKTEND after SLWR is deasserted and met the minimum

de-asserted pulse width. The FIFOADDR lines are to be held

constant during the PKTEND assertion.

• At t = 2, data must be present on the bus t_SFDbefore the

deasserting edge of SLWR.

• At t = 3, deasserting SLWR will cause the data to be written

from the data bus to the FIFO and then increments the FIFO

Document #: 001-04247 Rev. *D

Page 29 of 33

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CY7C68033/CY7C68034

Ordering Information

Table 17.Ordering Information

Ordering Code

Description

Silicon for battery-powered applications

CY7C68034-56LFXC

8x8 mm, 56 QFN – Lead-free

Silicon for non-battery-powered applications

CY7C68033-56LFXC

8x8 mm, 56 QFN – Lead-free

Development Kit

CY3686

EZ-USB NX2LP-Flex Development Kit

Package Diagram

Figure 20. 56-Lead QFN 8 x 8 mm LF56A

DIMENSIONS IN MM[INCHES] MIN.

MAX.

REFERENCE JEDEC MO-220

TOP VIEW

SIDE VIEW

1.00[0.039] MAX.

BOTTOM VIEW

0.08[0.003]

C

7.90[0.311]

A

8.10[0.319]

0.05[0.002] MAX.

0.18[0.007]

0.28[0.011]

7.70[0.303]

7.80[0.307]

0.80[0.031] MAX.

0.20[0.008] REF.

PIN1 ID

N

0.20[0.008] R.

1

2

1

2

0.45[0.018]

0.80[0.031]

DIA.

E-PAD

(PAD SIZE VARY

BY DEVICE TYPE)

0.30[0.012]

0.50[0.020]

0.24[0.009]

0.60[0.024]

(4X)

0°-12°

.240TYP

0.50[0.020]

C

SEATING PLANE

6.45[0.254]

6.55[0.258]

OPTION FOR CML - BOTTOM VIEW

N

2.375

1

2

1.925

R.250

(3X)

R.100

R.600

R.500

R.400

R.300

R.200

PIN #1 ID

E-PAD

.000

.680

(PAD SIZE VARY

BY DEVICE TYPE)

R.100

R.200

R.400

R.300

1.975

2.075

2.175

2.275

U-GROOVE DIMENSION

51-85144*E

NOTE:

DIMENSIONS ARE SAME WITH STD DWG ON UPPER RIGHT EXCEPT

FOR THE U-GROOVE ON THE PADDLE

Document #: 001-04247 Rev. *D

Page 30 of 33

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CY7C68033/CY7C68034

PCB Layout Recommendations^[16]

The following recommendations should be followed to ensure

reliable high-performance operation:

heat transfer area below the package to provide a good

thermal bond to the circuit board. A Copper (Cu) fill is to be

designed into the PCB as a thermal pad under the package.

Heat is transferred from the NX2LP-Flex to the PCB through

the device’s metal paddle on the bottom side of the package.

It is then conducted from the PCB’s thermal pad to the inner

ground plane by a 5 x 5 array of vias. A via is a plated through

hole in the PCB with a finished diameter of 13 mil. The QFN’s

metal die paddle must be soldered to the PCB’s thermal pad.

Solder mask is placed on the board top side over each via to

resist solder flow into the via. The mask on the top side also

minimizes outgassing during the solder reflow process.

• At least a four-layer impedance controlled boards is recom-

mended to maintain signal quality.

• Specify impedance targets (ask your board vendor what

they can achieve) to meet USB specifications.

• To control impedance, maintain trace widths and trace

spacing.

• Minimize any stubs to avoid reflected signals.

• Connections between the USB connector shell and signal

ground must be done near the USB connector.

For further information on this package design please refer to

the application note Surface Mount Assembly of AMKOR’s

MicroLeadFrame (MLF) Technology. This application note can

be downloaded from AMKOR’s website from the following

URL:

• Bypass/flyback caps on VBUS, near connector, are recom-

mended.

• DPLUS and DMINUS trace lengths should be kept to within

2 mm of each other in length, with preferred length of

20–30 mm.

http://www.amkor.com/products/notes_papers/

MLF_AppNote_0902.pdf.

• Maintain a solid ground plane under the DPLUS and

DMINUS traces. Do not allow the plane to be split under

these traces.

The application note provides detailed information on board

mounting guidelines, soldering flow, rework process, etc.

• No vias should be placed on the DPLUS or DMINUS trace

routing unless absolutely necessary.

Figure 21 below displays a cross-sectional area underneath

the package. The cross section is of only one via. The solder

paste template needs to be designed to allow at least 50%

solder coverage. The thickness of the solder paste template

should be 5 mil. It is recommended that ‘No Clean’ type 3

solder paste is used for mounting the part. Nitrogen purge is

recommended during reflow.

• Isolate the DPLUS and DMINUS traces from all other signal

traces as much as possible.

Quad Flat Package No Leads (QFN) Package

Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB)

is made by soldering the leads on the bottom surface of the

package to the PCB. Hence, special attention is required to the

Figure 22 is a plot of the solder mask pattern and Figure 23

displays an X-Ray image of the assembly (darker areas

indicate solder)

Figure 21. Cross-section of the Area Underneath the QFN Package.

0.017” dia

Solder Mask

Cu Fill

0.013” dia

PCB Material

Via hole for thermally connecting the

This figure only shows the top three layers of the

QFN to the circuit board ground plane.

circuit board: Top Solder, PCB Dielectric, and the Ground Plane.

Note

16. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High

Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.

Document #: 001-04247 Rev. *D

Page 31 of 33

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CY7C68033/CY7C68034

Figure 22. Plot of the Solder Mask (White Area)

Figure 23. X-ray Image of the Assembly

Purchase of I²C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips

I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification

as defined by Philips. EZ-USB FX2LP, EZ-USB FX2 and ReNumeration are trademarks, and EZ-USB is a registered trademark,

of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their

respective holders.

Document #: 001-04247 Rev. *D

Page 32 of 33

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C68033/CY7C68034

Document History Page

Document Title: CY7C68033/CY7C68034 EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller

Document #: 001-04247 Rev. *D

Orig. of

Change

REV.

ECN NO. Issue Date

Description of Change

**

388499

394699

See ECN

GIR

Preliminary draft

*A

XUT

Minor Change: Upload data sheet to external website. Publicly announcing the

parts. No physical changes to document were made

*B

400518

See ECN

GIR

Took ‘Preliminary’ off the top of all pages. Corrected the first bulleted item.

Corrected Figure 3-2 caption. Added new logo

*C

*D

433952

498295

See ECN

RGL

KKU

Added I²C functionality

Updated Data sheet format

Changed In/Output reference from I/O to IO

Changed set-up to setup

Changed IFCLK and CLKOUT pins to GPIO8 and GPIO9. Removed external

IFCLK

Document #: 001-04247 Rev. *D

Page 33 of 33

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型号：	CY3686
厂家：	CYPRESS
描述：	EZ-USB NX2LP-Flex⑩ Flexible USB NAND Flash Controller EZ- USB NX2LP -FLEX ™灵活的USB NAND闪存控制器闪存控制器
文件：	总33页 (文件大小：1526K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY3686 [CYPRESS]

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