CY37032VP48-100BAI_技术文档

Ultra37000 CPLD Family

5V, 3.3V, ISR™ High-Performance CPLDs

Features

General Description

• In-System Reprogrammable™ (ISR™) CMOS CPLDs

— JTAG interface for reconfigurability

— Design changes do not cause pinout changes

— Design changes do not cause timing changes

• High density

The Ultra37000™ family of CMOS CPLDs provides a range of

high-density programmable logic solutions with unparalleled

system performance. The Ultra37000 family is designed to

bring the flexibility, ease of use, and performance of the 22V10

to high-density CPLDs. The architecture is based on a number

of logic blocks that are connected by a Programmable Inter-

connect Matrix (PIM). Each logic block features its own

product term array, product term allocator, and 16 macrocells.

The PIM distributes signals from the logic block outputs and all

input pins to the logic block inputs.

— 32 to 512 macrocells

— 32 to 264 I/O pins

— Five dedicated inputs including four clock pins

• Simple timing model

All of the Ultra37000 devices are electrically erasable and In-

System Reprogrammable (ISR), which simplifies both design

and manufacturing flows, thereby reducing costs. The ISR

feature provides the ability to reconfigure the devices without

having design changes cause pinout or timing changes. The

Cypress ISR function is implemented through a JTAG-

compliant serial interface. Data is shifted in and out through

the TDI and TDO pins, respectively. Because of the superior

routability and simple timing model of the Ultra37000 devices,

ISR allows users to change existing logic designs while simul-

taneously fixing pinout assignments and maintaining system

performance.

— No fanout delays

— No expander delays

— No dedicated vs. I/O pin delays

— No additional delay through PIM

— No penalty for using full 16 product terms

— No delay for steering or sharing product terms

• 3.3V and 5V versions

• PCI-compatible^[1]

• Programmable bus-hold capabilities on all I/Os

• Intelligent product term allocator provides:

— 0 to 16 product terms to any macrocell

The entire family features JTAG for ISR and boundary scan,

and is compatible with the PCI Local Bus specification,

meeting the electrical and timing requirements. The

Ultra37000 family features user programmable bus-hold

capabilities on all I/Os.

— Product term steering on an individual basis

— Product term sharing among local macrocells

• Flexible clocking

Ultra37000 5.0V Devices

The Ultra37000 devices operate with a 5V supply and can

support 5V or 3.3V I/O levels. V_CCOconnections provide the

capability of interfacing to either a 5V or 3.3V bus. By

connecting the V_CCOpins to 5V the user insures 5V TTL levels

on the outputs. If V_CCOis connected to 3.3V the output levels

meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.

These devices require 5V ISR programming.

— Four synchronous clocks per device

— Product term clocking

— Clock polarity control per logic block

• Consistent package/pinout offeringacrossall densities

— Simplifies design migration

— Same pinout for 3.3V and 5.0V devices

• Packages

Ultra37000V 3.3V Devices

Devices operating with a 3.3V supply require 3.3V on all V_CCO

pins, reducing the device’s power consumption. These

devices support 3.3V JEDEC standard CMOS output levels,

and are 5V-tolerant. These devices allow 3.3V ISR

programming.

— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,

BGA, and Fine-Pitch BGA packages

Note:

1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V_CC, PCI V_IH= 2V.

Cypress Semiconductor Corporation

Document #: 38-03007 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 7, 2003

Ultra37000 CPLD Family

Selection Guide

5.0V Selection Guide

General Information

Dedicated

Inputs

Device

Macrocells

32

I/O Pins

32

Speed (t_PD

)

Speed (f_MAX

)

CY37032

CY37064

CY37128

CY37192

CY37256

CY37384

CY37512

5

6

200

64

32/64

6

200

128

64/128

6.5

7.5

10

167

192

120

154

256

128/160/192

160/192

160/192/264

154

384

118

512

118

Speed Bins

Device

200

167

154

X

143

125

X

100

83

66

CY37032

CY37064

CY37128

CY37192

CY37256

CY37384

CY37512

X

Device-Package Offering and I/O Count

44-

84-

100-

160-

208-

Lead

256-

Lead

BGA

352-

Lead

BGA

Device

Lead

TQFP PLCC CLCC PLCC CLCC TQFP TQFP CQFP PQFP CQFP

CY37032

CY37064

CY37128

CY37192

CY37256

CY37384

CY37512

37

69

133

125

133

165

197

165

269

3.3V Selection Guide

General Information

Dedicated

Inputs

Device

Macrocells

32

I/O Pins

32

Speed (t_PD

)

Speed (f_MAX)

CY37032V

CY37064V

CY37128V

CY37192V

CY37256V

CY37384V

CY37512V

5

8.5

10

12

15

143

125

100

83

64

32/64

128

64/80/128

120

192

256

128/160/192

160/192

160/192/264

384

512

83

Document #: 38-03007 Rev. *C

Page 2 of 62

Ultra37000 CPLD Family

Speed Bins

Device

200

167

154

143

X

125

100

X

83

66

CY37032V

CY37064V

CY37128V

CY37192V

CY37256V

CY37384V

CY37512V

X

Device-Package Offering & I/O Count

Device

CY37032V

CY37064V

CY37128V

CY37192V

CY37256V

CY37384V

CY37512V

37

69

85

69

133

125

133

165

197

165

269

Logic Block

Architecture Overview of Ultra37000 Family

The logic block is the basic building block of the Ultra37000

architecture. It consists of a product term array, an intelligent

product-term allocator, 16 macrocells, and a number of I/O

cells. The number of I/O cells varies depending on the device

used. Refer to Figure 1 for the block diagram.

Programmable Interconnect Matrix

The PIM consists of a completely global routing matrix for

signals from I/O pins and feedbacks from the logic blocks. The

PIM provides extremely robust interconnection to avoid fitting

and density limitations.

Product Term Array

The inputs to the PIM consist of all I/O and dedicated input pins

and all macrocell feedbacks from within the logic blocks. The

number of PIM inputs increases with pin count and the number

of logic blocks. The outputs from the PIM are signals routed to

the appropriate logic blocks. Each logic block receives 36

inputs from the PIM and their complements, allowing for 32-bit

operations to be implemented in a single pass through the

device. The wide number of inputs to the logic block also

improves the routing capacity of the Ultra37000 family.

Each logic block features a 72 x 87 programmable product

term array. This array accepts 36 inputs from the PIM, which

originate from macrocell feedbacks and device pins. Active

LOW and active HIGH versions of each of these inputs are

generated to create the full 72-input field. The 87 product

terms in the array can be created from any of the 72 inputs.

Of the 87 product terms, 80 are for general-purpose use for

the 16 macrocells in the logic block. Four of the remaining

seven product terms in the logic block are output enable (OE)

product terms. Each of the OE product terms controls up to

eight of the 16 macrocells and is selectable on an individual

macrocell basis. In other words, each I/O cell can select

between one of two OE product terms to control the output

buffer. The first two of these four OE product terms are

available to the upper half of the I/O macrocells in a logic block.

The other two OE product terms are available to the lower half

of the I/O macrocells in a logic block.

An important feature of the PIM is its simple timing. The propa-

gation delay through the PIM is accounted for in the timing

specifications for each device. There is no additional delay for

traveling through the PIM. In fact, all inputs travel through the

PIM. As a result, there are no route-dependent timing param-

eters on the Ultra37000 devices. The worst-case PIM delays

are incorporated in all appropriate Ultra37000 specifications.

Routing signals through the PIM is completely invisible to the

user. All routing is accomplished by software—no hand routing

is necessary. Warp and third-party development packages

automatically route designs for the Ultra37000 family in a

matter of minutes. Finally, the rich routing resources of the

Ultra37000 family accommodate last minute logic changes

while maintaining fixed pin assignments.

The next two product terms in each logic block are dedicated

asynchronous set and asynchronous reset product terms. The

final product term is the product term clock. The set, reset, OE

and product term clock have polarity control to realize OR

functions in a single pass through the array.

Document #: 38-03007 Rev. *C

Page 3 of 62

Ultra37000 CPLD Family

3

2

0−16

I/O

CELL

0

MACRO-

CELL

0

PRODUCT

TERMS

7

MACRO-

CELL

1

0−16

to cells

2, 4, 6 8, 10, 12

PRODUCT

TERMS

FROM

PIM

36

80

72 x 87

PRODUCT TERM

ARRAY

PRODUCT

TERM

ALLOCATOR

MACRO-

CELL

14

I/O

CELL

14

0−16

PRODUCT

TERMS

MACRO-

CELL

15

0−16

TO

PIM

PRODUCT

TERMS

16

8

Figure 1. Logic Block with 50% Buried Macrocells

Low-Power Option

variable fashion. The software automatically takes advantage

of this capability—the user does not have to intervene.

Each logic block can operate in high-speed mode for critical

path performance, or in low-power mode for power conser-

vation. The logic block mode is set by the user on a logic block

by logic block basis.

Note that neither product term sharing nor product term

steering have any effect on the speed of the product. All worst-

case steering and sharing configurations have been incorpo-

rated in the timing specifications for the Ultra37000 devices.

Product Term Allocator

Ultra37000 Macrocell

Through the product term allocator, software automatically

distributes product terms among the 16 macrocells in the logic

block as needed. A total of 80 product terms are available from

the local product term array. The product term allocator

provides two important capabilities without affecting perfor-

mance: product term steering and product term sharing.

Within each logic block there are 16 macrocells. Macrocells

can either be I/O Macrocells, which include an I/O Cell which

is associated with an I/O pin, or buried Macrocells, which do

not connect to an I/O. The combination of I/O Macrocells and

buried Macrocells varies from device to device.

Product Term Steering

Buried Macrocell

Product term steering is the process of assigning product

terms to macrocells as needed. For example, if one macrocell

requires ten product terms while another needs just three, the

product term allocator will “steer” ten product terms to one

macrocell and three to the other. On Ultra37000 devices,

product terms are steered on an individual basis. Any number

between 0 and 16 product terms can be steered to any

macrocell. Note that 0 product terms is useful in cases where

a particular macrocell is unused or used as an input register.

Figure 2 displays the architecture of buried macrocells. The

buried macrocell features a register that can be configured as

combinatorial, a D flip-flop, a T flip-flop, or a level-triggered

latch.

The register can be asynchronously set or asynchronously

reset at the logic block level with the separate set and reset

product terms. Each of these product terms features program-

mable polarity. This allows the registers to be set or reset

based on an AND expression or an OR expression.

Product Term Sharing

Clocking of the register is very flexible. Four global

synchronous clocks and a product term clock are available to

clock the register. Furthermore, each clock features program-

mable polarity so that registers can be triggered on falling as

well as rising edges (see the Clocking section). Clock polarity

is chosen at the logic block level.

Product term sharing is the process of using the same product

term among multiple macrocells. For example, if more than

one output has one or more product terms in its equation that

are common to other outputs, those product terms are only

programmed once. The Ultra37000 product term allocator

allows sharing across groups of four output macrocells in a

Document #: 38-03007 Rev. *C

Page 4 of 62

Ultra37000 CPLD Family

The buried macrocell also supports input register capability.

The buried macrocell can be configured to act as an input

register (D-type or latch) whose input comes from the I/O pin

associated with the neighboring macrocell. The output of all

buried macrocells is sent directly to the PIM regardless of its

configuration.

Bus Hold Capabilities on all I/Os

Bus-hold, which is an improved version of the popular internal

pull-up resistor, is a weak latch connected to the pin that does

not degrade the device’s performance. As a latch, bus-hold

maintains the last state of a pin when the pin is placed in a

high-impedance state, thus reducing system noise in bus-

interface applications. Bus-hold additionally allows unused

device pins to remain unconnected on the board, which is

particularly useful during prototyping as designers can route

new signals to the device without cutting trace connections to

V_CCor GND. For more information, see the application note

“Understanding Bus-Hold — A Feature of Cypress CPLDs.”

I/O Macrocell

Figure 2 illustrates the architecture of the I/O macrocell. The

I/O macrocell supports the same functions as the buried

macrocell with the addition of I/O capability. At the output of the

macrocell, a polarity control mux is available to select active

LOW or active HIGH signals. This has the added advantage

of allowing significant logic reduction to occur in many appli-

cations.

Programmable Slew Rate Control

Each output has a programmable configuration bit, which sets

the output slew rate to fast or slow. For designs concerned with

meeting FCC emissions standards the slow edge provides for

lower system noise. For designs requiring very high perfor-

mance the fast edge rate provides maximum system perfor-

mance.

The Ultra37000 macrocell features a feedback path to the PIM

separate from the I/O pin input path. This means that if the

macrocell is buried (fed back internally only), the associated

I/O pin can still be used as an input.

Document #: 38-03007 Rev. *C

Page 5 of 62

Ultra37000 CPLD Family

f

I/O MACROCELL

FAST

FROM PTM

0

1

SLEW

SLOW

0−16

PRODUCT

TERMS

C25

C26

I/O CELL

0

1

O

0

1

P

D/T/L

Q

0

1

2

3

4

“0”

“1”

0

1

2

3

O

R

C4

O

DECODE

C2 C3

C0 C1C24

C6 C5

1

0

BURIED MACROCELL

FROM PTM

0

1

0−16

PRODUCT

TERMS

C25

0

1

0

O

P

D/T/L

1

Q

0

1

Q

2

3

C7

R

4

DECODE

C2 C3

C0 C1C24

1

0

FEEDBACK TO PIM

ASYNCHRONOUS

BLOCK RESET

ASYNCHRONOUS

BLOCK PRESET

4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)

1 ASYNCHRONOUS CLOCK(PTCLK)

OE0

OE1

Figure 2. I/O and Buried Macrocells

INPUT PIN

0

1

O

TO PIM

2

3

D

0

1

2

3

Q

FROM CLOCK

POLARITY MUXES

O

C12 C13

C10 C11

D

LE

Figure 3. Input Macrocell

Document #: 38-03007 Rev. *C

Page 6 of 62

Ultra37000 CPLD Family

0

1

TO CLOCK MUX ON

ALL INPUT MACROCELLS

O

INPUT/CLOCK PIN

C12

0

O

1

TO CLOCK MUX

IN EACH

LOGIC BLOCK

C13, C14, C15

OR C16

0

1

2

3

O

TO PIM

CLOCK POLARITY MUX

ONE PER LOGIC BLOCK

FOR EACH CLOCK INPUT

D

0

Q

FROM CLOCK

POLARITY INPUT

CLOCK PINS

1

O

2

3

C10C11

C8

C9

D

LE

Figure 4. Input/Clock Macrocell

Clocking

The Ultra37000 features:

• No fanout delays

• No expander delays

• No dedicated vs. I/O pin delays

• No additional delay through PIM

Each I/O and buried macrocell has access to four synchronous

clocks (CLK0, CLK1, CLK2 and CLK3) as well as an

asynchronous product term clock PTCLK. Each input

macrocell has access to all four synchronous clocks.

• No penalty for using 0–16 product terms

• No added delay for steering product terms

• No added delay for sharing product terms

• No routing delays

Dedicated Inputs/Clocks

Five pins on each member of the Ultra37000 family are desig-

nated as input-only. There are two types of dedicated inputs

on Ultra37000 devices: input pins and input/clock pins.

Figure 3 illustrates the architecture for input pins. Four input

options are available for the user: combinatorial, registered,

double-registered, or latched. If a registered or latched option

is selected, any one of the input clocks can be selected for

control.

• No output bypass delays

The simple timing model of the Ultra37000 family eliminates

unexpected performance penalties.

COMBINATORIAL SIGNAL

Figure 4 illustrates the architecture for the input/clock pins.

Like the input pins, input/clock pins can be combinatorial,

registered, double-registered, or latched. In addition, these

pins feed the clocking structures throughout the device. The

clock path at the input has user-configurable polarity.

t

= 6.5 ns

PD

INPUT

OUTPUT

REGISTERED SIGNAL

= 3.5 ns

t

= 4.5 ns

S

CO

Product Term Clocking

D,T,L

O

INPUT

In addition to the four synchronous clocks, the Ultra37000

family also has a product term clock for asynchronous

clocking. Each logic block has an independent product term

clock which is available to all 16 macrocells. Each product term

clock also supports user configurable polarity selection.

CLOCK

Figure 5. Timing Model for CY37128

Timing Model

One of the most important features of the Ultra37000 family is

the simplicity of its timing. All delays are worst case and

system performance is unaffected by the features used. Figure

5 illustrates the true timing model for the 167-MHz devices in

high speed mode. For combinatorial paths, any input to any

output incurs a 6.5-ns worst-case delay regardless of the

amount of logic used. For synchronous systems, the input set-

up time to the output macrocells for any input is 3.5 ns and the

clock to output time is also 4.0 ns. These measurements are

for any output and synchronous clock, regardless of the logic

used.

JTAG and PCI Standards

PCI Compliance

5V operation of the Ultra37000 is fully compliant with the PCI

Local Bus Specification published by the PCI Special Interest

Group. The 3.3V products meet all PCI requirements except

for the output 3.3V clamp, which is in direct conflict with 5V

tolerance. The Ultra37000 family’s simple and predictable

timing model ensures compliance with the PCI AC specifica-

tions independent of the design.

Document #: 38-03007 Rev. *C

Page 7 of 62

Ultra37000 CPLD Family

IEEE 1149.1-compliant JTAG

Warp Enterprise™

The Ultra37000 family has an IEEE 1149.1 JTAG interface for

both Boundary Scan and ISR.

Warp Enterprise provides even more features. It provides

unlimited timing simulation and source-level behavioral

simulation as well as a debugger. It has the ability to generate

graphical HDL blocks from HDL text. It can even generate

testbenches.

Boundary Scan

The Ultra37000 family supports Bypass, Sample/Preload,

Extest, Idcode, and Usercode boundary scan instructions. The

JTAG interface is shown in Figure 6.

Warp is available for PC and UNIX platforms. Some features

are not available in the UNIX version. For further information

see the Warp for PC, Warp for UNIX, Warp Professional and

Warp Enterprise data sheets on Cypress’s web site

(www.cypress.com).

Instruction Register

TDI

TDO

Third-Party Software

Although Warp is a complete CPLD development tool on its

own, it interfaces with nearly every third party EDA tool. All

major third-party software vendors provide support for the

Ultra37000 family of devices. Refer to the third-party software

data sheet or contact your local sales office for a list of

currently supported third-party vendors.

Bypass Reg.

JTAG

TMS

TAP

CONTROLLER

Boundary Scan

idcode

TCK

Programming

Usercode

ISR Prog.

There are four programming options available for Ultra37000

devices. The first method is to use a PC with the 37000

UltraISR programming cable and software. With this method,

the ISR pins of the Ultra37000 devices are routed to a

connector at the edge of the printed circuit board. The 37000

UltraISR programming cable is then connected between the

parallel port of the PC and this connector. A simple configu-

ration file instructs the ISR software of the programming

operations to be performed on each of the Ultra37000 devices

in the system. The ISR software then automatically completes

all of the necessary data manipulations required to accomplish

the programming, reading, verifying, and other ISR functions.

For more information on the Cypress ISR Interface, see the

ISR Programming Kit data sheet (CY3700i).

Data Registers

Figure 6. JTAG Interface

In-System Reprogramming (ISR)

In-System Reprogramming is the combination of the capability

to program or reprogram a device on-board, and the ability to

support design changes without changing the system timing

or device pinout. This combination means design changes

during debug or field upgrades do not cause board respins.

The Ultra37000 family implements ISR by providing a JTAG

compliant interface for on-board programming, robust routing

resources for pinout flexibility, and a simple timing model for

consistent system performance.

The second method for programming Ultra37000 devices is on

automatic test equipment (ATE). This is accomplished through

a file created by the ISR software. Check the Cypress website

for the latest ISR software download information.

Development Software Support

The third programming option for Ultra37000 devices is to

utilize the embedded controller or processor that already

exists in the system. The Ultra37000 ISR software assists in

this method by converting the device JEDEC maps into the

ISR serial stream that contains the ISR instruction information

and the addresses and data of locations to be programmed.

The embedded controller then simply directs this ISR stream

to the chain of Ultra37000 devices to complete the desired

reconfiguring or diagnostic operations. Contact your local

sales office for information on availability of this option.

Warp

Warp is a state-of-the-art compiler and complete CPLD design

tool. For design entry, Warp provides an IEEE-STD-1076/1164

VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a

graphical finite state machine editor. It provides optimized

synthesis and fitting by replacing basic circuits with ones pre-

optimized for the target device, by implementing logic in

unused memory and by perfect communication between fitting

and synthesis. To facilitate design and debugging, Warp

provides graphical timing simulation and analysis.

The fourth method for programming Ultra37000 devices is to

use the same programmer that is currently being used to

program FLASH370i devices.

Warp Professional™

Warp Professional contains several additional features. It

provides an extra method of design entry with its graphical

block diagram editor. It allows up to 5 ms timing simulation

instead of only 2 ms. It allows comparison of waveforms before

and after design changes.

For all pinout, electrical, and timing requirements, refer to

device data sheets. For ISR cable and software specifications,

refer to the UltraISR kit data sheet (CY3700i).

Third-Party Programmers

As with development software, Cypress support is available

on a wide variety of third-party programmers. All major third-

party programmers (including BP Micro, Data I/O, and SMS)

support the Ultra37000 family.

Document #: 38-03007 Rev. *C

Page 8 of 62

Ultra37000 CPLD Family

Logic Block Diagrams

CY37032/CY37032V

Clock/

Input

1

TDI

TCK

TMS

JTAG Tap

Controller

TDO

4

JTAG_EN

4

36

16

36

16

LOGIC

BLOCK

A

LOGIC

BLOCK

B

16 I/Os

I/O₀−I/O₁₅

16 I/Os

I/O₁₆−I/O₃₁

PIM

16

Clock/

Input

CY37064/CY37064V (100-Lead TQFP)

Input

4

1

4

36

LOGIC

BLOCK

LOGIC

BLOCK

D

16 I/Os

I/O -I/O

0

I/O -I/O

48

15

31

16

36

16

36

63

47

A

PIM

16 I/Os

LOGIC

BLOCK

B

LOGIC

BLOCK

C

I/O -I/O

32

I/O -I/O

16

32

TDI

JTAG Tap

Controller

TCK

TMS

TDO

Document #: 38-03007 Rev. *C

Page 9 of 62

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

TDI

JTAG Tap

CY37128/CY37128V (160-lead TQFP)

CLOCK

INPUTS

TCK

TMS

TDO

INPUTS

1

Controller

4

INPUT/CLOCK

MACROCELLS

INPUT

MACROCELL

JTAG_EN

4

16 I/Os

LOGIC

BLOCK

A

LOGIC

BLOCK

H

16 I/Os

I/O –I/O

36

16

36

16

0

15

I/O –I/O

112

127

PIM

LOGIC

BLOCK

B

LOGIC

BLOCK

G

16 I/Os

36

16

36

16

I/O –I/O

96 111

16

31

47

LOGIC

BLOCK

C

LOGIC

BLOCK

F

36

16

36

16

I/O –I/O

80

32

95

79

16 I/Os

LOGIC

BLOCK

D

LOGIC

BLOCK

E

16 I/Os

36

16

36

16

I/O –I/O

64

28

63

64

Clock/

Input

CY37192/CY37192V (160-lead TQFP)

Input

4

1

4

36

LOGIC

BLOCK

L

10 I/Os

9

10 I/Os

I/O –I/O

BLOCK

A

16

36

16

36

16

36

16

36

16

36

I/O –I/O

110

119

0

10 I/Os

I/O –I/O

10 I/Os

LOGIC

BLOCK

B

LOGIC

BLOCK

K

16

36

16

36

16

I/O –I/O

10

100

109

19

10 I/Os

I/O –I/O

99

10 I/Os

LOGIC

BLOCK

C

LOGIC

BLOCK

J

I/O –I/O

20

29

90

PIM

10 I/Os

I/O –I/O

10 I/Os

39

LOGIC

BLOCK

D

LOGIC

BLOCK

I

I/O –I/O

30

80

89

36

16

36

10 I/Os

I/O –I/O

10 I/Os

49

LOGIC

BLOCK

E

LOGIC

BLOCK

H

I/O –I/O

40

70

79

69

36

16

10 I/Os

I/O –I/O

10 I/Os

LOGIC

BLOCK

F

LOGIC

BLOCK

G

I/O –I/O

50

16

60

59

TDI

TCK

TMS

60

JTAG Tap

Controller

TDO

Document #: 38-03007 Rev. *C

Page 10 of 62

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

Clock/

Input

1

CY37256/CY37256V (256-lead BGA)

4

36

LOGIC

BLOCK

A

LOGIC

BLOCK

P

12 I/Os

I/O₀−I/O₁₁

12 I/Os

16

36

16

36

16

36

16

36

16

36

I/O₁₈₀−I/O₁₉₁

12 I/Os

LOGIC

BLOCK

B

LOGIC

BLOCK

O

16

36

16

36

16

I/O₁₆₈−I/O₁₇₉

I/O₁₂−I/O₂₃

12 I/Os

LOGIC

BLOCK

C

LOGIC

BLOCK

N

I/O₁₅₆−I/O₁₆₇

I/O₂₄−I/O₃₅

12 I/Os

LOGIC

BLOCK

D

LOGIC

BLOCK

M

I/O₃₆−I/O₄₇

I/O₁₄₄−I/O₁₅₅

PIM

36

16

36

16

12 I/Os

LOGIC

BLOCK

E

LOGIC

BLOCK

L

I/O₄₈−I/O₅₉

I/O₁₃₂−I/O₁₄₃

36

16

12 I/Os

LOGIC

BLOCK

F

LOGIC

BLOCK

K

I/O₁₂₀−I/O₁₃₁

I/O₆₀−I/O₇₁

36

16

36

16

36

12 I/Os

LOGIC

BLOCK

G

LOGIC

BLOCK

J

I/O₇₂−I/O₈₃

I/O₁₀₈−I/O₁₁₉

36

16

12 I/Os

I/O₈₄−I/O₉₅

LOGIC

BLOCK

H

LOGIC

BLOCK

I

16

I/O₉₆−I/O₁₀₇

TDI

TCK

TMS

96

JTAG Tap

Controller

TDO

Document #: 38-03007 Rev. *C

Page 11 of 62

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

Clock/

Input

CY37384/CY37384V (256-Lead BGA)

Input

1

4

36

16

36

16

36

16

36

16

36

LOGIC

BLOCK

AA

LOGIC

BLOCK

BL

12 I/Os

I/O₀−I/O₁₁

16

36

12 I/Os

I/O₁₂−I/O₂₃

LOGIC

BLOCK

AB

LOGIC

BLOCK

BK

16

36

16

36

16

36

I/O₁₆₈−I/O₁₉₁

12 I/Os

I/O₂₄−I/O₃₅

LOGIC

BLOCK

AC

LOGIC

BLOCK

BJ

I/O₁₅₆−I/O₁₇₉

12 I/Os

LOGIC

BLOCK

AD

LOGIC

BLOCK

BI

I/O₁₄₄−I/O₁₆₇

36

16

PIM

12 I/Os

I/O₃₆−I/O₄₇

LOGIC

BLOCK

AE

LOGIC

BLOCK

BH

16

36

16

36

16

12 I/Os

LOGIC

BLOCK

AF

LOGIC

BLOCK

BG

I/O₁₃₂−I/O₁₅₅

36

16

36

16

36

16

36

16

12 I/Os

I/O₄₈−I/O₅₉

LOGIC

BLOCK

AG

LOGIC

BLOCK

BF

36

16

12 I/Os

I/O₆₀−I/O₇₁

LOGIC

BLOCK

AH

LOGIC

BLOCK

BE

I/O₁₂₀−I/O₁₄₃

36

16

12 I/Os

I/O₇₂−I/O₈₃

LOGIC

BLOCK

AI

LOGIC

BLOCK

BD

I/O₁₀₈−I/O₁₃₁

36

16

36

16

12 I/Os

LOGIC

BLOCK

AJ

LOGIC

BLOCK

BC

I/O₉₆−I/O₁₁₉

36

16

36

16

12 I/Os

I/O₈₄−I/O₉₅

LOGIC

BLOCK

AK

LOGIC

BLOCK

BB

36

16

36

16

12 I/Os

LOGIC

BLOCK

AL

LOGIC

BLOCK

BA

I/O₉₆−I/O₁₀₇

TDI

TCK

TMS

JTAG Tap

Controller

96

TDO

Document #: 38-03007 Rev. *C

Page 12 of 62

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

CY37512/CY37512V (352-Lead BGA)

Input

Clock/ Input

4

1

4

36

LOGIC

BLOCK

AA

LOGIC

BLOCK

BP

12 I/Os

11

16

36

16

36

16

36

16

36

16

36

I/O

−I/O

0

12 I/Os

LOGIC

BLOCK

AB

LOGIC

BLOCK

BO

16

36

I/O

−

I/O

−

I/O

252

263

12

23

12 I/Os

I/O

12 I/Os

LOGIC

BLOCK

AC

LOGIC

BLOCK

BN

16

36

16

I/O

−

I/O

24

35

240

228

251

239

12 I/Os

I/O

LOGIC

BLOCK

AD

LOGIC

BLOCK

BM

36

16

36

LOGIC

BLOCK

AE

LOGIC

BLOCK

BL

12 I/Os

47

−

36

48

60

36

16

12 I/Os

I/O

LOGIC

BLOCK

AF

LOGIC

BLOCK

BK

−I/O

16

36

16

216

227

36

16

36

LOGIC

BLOCK

AG

LOGIC

BLOCK

BJ

12 I/Os

59

36

12 I/Os

I/O

LOGIC

BLOCK

AH

LOGIC

BLOCK

BI

−

I/O

16

36

16

36

204

215

203

191

PIM

12 I/Os

LOGIC

BLOCK

AI

LOGIC

BLOCK

BH

16

36

16

36

71

12 I/Os

I/O

LOGIC

BLOCK

AJ

LOGIC

BLOCK

BG

−

I/O

16

36

16

36

192

180

12 I/Os

83

LOGIC

BLOCK

AK

LOGIC

BLOCK

BF

I/O

−

I/O

16

36

16

36

72

12 I/Os

I/O

12 I/Os

LOGIC

BLOCK

AL

LOGIC

BLOCK

BE

−

16

36

16

36

I/O

−I/O

84 95

12 I/Os

I/O

LOGIC

BLOCK

AM

LOGIC

BLOCK

BD

12 I/Os

−

I/O

16

36

16

36

168

179

I/O

−I/O

96 107

12 I/Os

I/O

12 I/Os

LOGIC

BLOCK

AN

LOGIC

BLOCK

BC

−I/O

16

36

16

36

I/O

−I/O

156

167

108

119

12 I/Os

I/O

12 I/Os

LOGIC

BLOCK

AO

LOGIC

BLOCK

BB

−

I/O

16

36

I/O

−

I/O

16

36

144

155

120

131

12 I/Os

I/O

LOGIC

BLOCK

AP

LOGIC

BLOCK

BA

I/O

16

132

143

132

TDI

TCK

TMS

JTAG Tap

Controller

TDO

Document #: 38-03007 Rev. *C

Page 13 of 62

Ultra37000 CPLD Family

DC Voltage Applied to Outputs

5.0V Device Characteristics

Maximum Ratings

in High-Z State................................................–0.5V to +7.0V

DC Input Voltage ............................................–0.5V to +7.0V

DC Program Voltage............................................. 4.5 to 5.5V

Current into Outputs .................................................... 16 mA

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Latch-up Current.....................................................> 200 mA

Supply Voltage to Ground Potential............... –0.5V to +7.0V

Operating Range^[2]

Ambient

Junction

Temperature

Output

Condition

Range

Temperature^[2]

V_CC

V_CCO

Commercial

0°C to +70°C

–40°C to +85°C

–55°C to +125°C

0°C to +90°C

–40°C to +105°C

–55°C to +130°C

5V

5V ± 0.25V

5V ± 0.5V

5V ± 0.25V

3.3V ± 0.3V

5V ± 0.5V

3.3V ± 0.3V

5V ± 0.5V

3.3V ± 0.3V

3.3V

5V

Industrial

Military^[3]

3.3V

5V

3.3V

5.0V Device Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min. Typ. Max. Unit

V_OH

Output HIGH Voltage

V_CC= Min.

V_CC= Max.

I_OH= –3.2 mA (Com’l/Ind)^[4]2.4

V

I_OH= –2.0 mA (Mil)^[4]

2.4

V_OHZ

Output HIGH Voltage with

Output Disabled^[5]

I_OH= 0 µA (Com’l)^[6]

4.2

4.5

V

I_OH= 0 µA (Ind/Mil)^[6]

I_OH= –100 µA (Com’l)^[6]

I_OH= –150 µA (Ind/Mil)^[6]

I_OL= 16 mA (Com’l/Ind)^[4]

I_OL= 12 mA (Mil)^[4]

V

3.6

V

3.6

V

V_OL

Output LOW Voltage

V_CC= Min.

0.5

V

0.5

V

V_IH

V_IL

I_IX

Input HIGH Voltage

Input LOW Voltage

Input Load Current

Output Leakage Current

Guaranteed Input Logical HIGH Voltage for all Inputs^[7]

Guaranteed Input Logical LOW Voltage for all Inputs^[7]

V_I= GND OR V_CC, Bus-Hold Disabled

2.0

–0.5

–10

V_CCmax

0.8

V

10

µA

I_OZ

I_OS

I_BHL

V_O= GND or V_CC, Output Disabled, Bus-Hold Disabled –50

50

OutputShortCircuitCurrent^{[8, 5]}V_CC= Max., V_OUT= 0.5V

–30

+75

–160 mA

Input Bus-Hold LOW

Sustaining Current

V_CC= Min., V_IL= 0.8V

V_CC= Min., V_IH= 2.0V

V_CC= Max.

µA

I_BHH

Input Bus-Hold HIGH

Sustaining Current

–75

µA

+500 µA

–500 µA

I_BHLO

Input Bus-Hold LOW

Overdrive Current

I_BHHO

Input Bus-Hold HIGH

Overdrive Current

V_CC= Max.

Notes:

2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the

Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”

3.

T_Ais the “Instant On” case temperature.

4. I_OH= –2 mA, I_OL= 2 mA for TDO.

5. Tested initially and after any design or process changes that may affect these parameters.

6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled

during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.

7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V_OUT= 0.5V has been chosen to avoid test

problems caused by tester ground degradation.

Document #: 38-03007 Rev. *C

Page 14 of 62

Ultra37000 CPLD Family

Inductance^[5]

44-

84-

100-

160-

208-

Test

Lead

Parameter

Description

Conditions TQFP PLCC CLCC PLCC CLCC TQFP TQFP PQFP Unit

L

Maximum Pin V_IN= 5.0V

2

5

2

8

5

8

9

11

nH

Inductance

at f = 1 MHz

Capacitance^[5]

Parameter

Description

Test Conditions

Max.

Unit

pF

C_I/O

C_CLK

C_DP

Input/Output Capacitance

V_IN= 5.0V at f = 1 MHz at T_A= 25°C

10

12

16

Clock Signal Capacitance

Dual Function Pins^[9]

pF

Endurance Characteristics^[5]

Parameter

Description

Minimum Reprogramming Cycles

Test Conditions

Normal Programming Conditions^[2]

Min.

1,000

Typ.

Unit

Cycles

N

10,000

DC Voltage Applied to Outputs

3.3V Device Characteristics

Maximum Ratings

in High-Z State................................................–0.5V to +7.0V

DC Input Voltage ............................................–0.5V to +7.0V

DC Program Voltage............................................. 3.0 to 3.6V

Current into Outputs ...................................................... 8 mA

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Static Discharge Voltage............................................ >2001V

(per MIL-STD-883, Method 3015)

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Latch-up Current......................................................>200 mA

Supply Voltage to Ground Potential............... –0.5V to +4.6V

Operating Range^[2]

[10]

Range

Ambient Temperature^[2]

0°C to +70°C

Junction Temperature

0°C to +90°C

V_CC

Commercial

Industrial

Military^[3]

3.3V ± 0.3V

–40°C to +85°C

–40°C to +105°C

–55°C to +130°C

–55°C to +125°C

3.3V Device Electrical Characteristics Over the Operating Range

Parameter

V_OH

Description

Output HIGH Voltage

Test Conditions

V_CC= Min. I_OH= –4 mA (Com’l)^[4]

I_OH= –3 mA (Mil)^[4]

Min.

Max.

Unit

2.4

V

V_OL

Output LOW Voltage

V_CC= Min. I_OL= 8 mA (Com’l)^[4]

I_OL= 6 mA (Mil)^[4]

0.5

V

V_IH

V_IL

Input HIGH Voltage

Input LOW Voltage

Guaranteed Input Logical HIGH Voltage for

all Inputs^[7]

2.0

5.5

0.8

V

Guaranteed Input Logical LOW Voltage for

all Inputs^[7]

–0.5

I_IX

Input Load Current

V_I= GND OR V_CC, Bus-Hold Disabled

–10

–50

10

50

µA

I_OZ

Output Leakage Current

V_O= GND or V_CC, Output Disabled, Bus-

Hold Disabled

I_OS

Output Short Circuit Current^{[8, 5]}

V_CC= Max., V_OUT= 0.5V

V_CC= Min., V_IL= 0.8V

–30

+75

–160

mA

I_BHL

Input Bus-Hold LOW Sustaining

Current

µA

Notes:

9. Dual pins are I/O with JTAG pins.

10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: V_CCis 3.3V± 0.16V.

Document #: 38-03007 Rev. *C

Page 15 of 62

Ultra37000 CPLD Family

3.3V Device Electrical Characteristics Over the Operating Range (continued)

Parameter

I_BHH

Description

Test Conditions

V_CC= Min., V_IH= 2.0V

Min.

Max.

Unit

Input Bus-Hold HIGH Sustaining

Current

–75

µA

I_BHLO

I_BHHO

Input Bus-Hold LOW Overdrive

Current

V_CC= Max.

+500

–500

µA

Input Bus-Hold HIGH Overdrive

Current

Inductance^[5]

44-

84-

100-

160-

Lead

208-

Lead

Test

Lead

Parameter

Description

Conditions TQFP PLCC CLCC PLCC CLCC TQFP TQFP PQFP Unit

L

Maximum Pin V_IN= 3.3V

2

5

2

8

5

8

9

11

nH

Inductance

at f = 1 MHz

Capacitance^[5]

Parameter

Description

Test Conditions

Max.

Unit

pF

C_I/O

C_CLK

C_DP

Input/Output Capacitance

V_IN= 3.3V at f = 1 MHz at T_A= 25°C

8

Clock Signal Capacitance

Dual Functional Pins^[9]

12

16

pF

Endurance Characteristics^[5]

Parameter

Description

Minimum Reprogramming Cycles

Test Conditions

Normal Programming Conditions^[2]

Min.

1,000

Typ.

Unit

Cycles

N

10,000

AC Characteristics

5.0V AC Test Loads and Waveforms

238Ω (COM'L)

319Ω (MIL)

3.0V

238Ω (COM’L)

319Ω (MIL)

ALL INPUT PULSES

5V

90%

10%

90%

10%

OUTPUT

170Ω (COM'L)

236Ω (MIL)

170Ω (COM’L)

236Ω (MIL)

GND

<2 ns

35 pF

5 pF

<2 ns

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Equivalent to:

THÉVENIN EQUIVALENT

99Ω (COM’L)

136Ω (MIL)

2.08V (COM'L)

2.13V (MIL)

OUTPUT

5 OR 35 pF

Document #: 38-03007 Rev. *C

Page 16 of 62

Ultra37000 CPLD Family

AC Characteristics

3.3V AC Test Loads and Waveforms

295Ω (COM'L)

393Ω (MIL)

295Ω (COM’L)

393Ω (MIL)

ALL INPUT PULSES

3.3V

3.0V

GND

90%

10%

90%

10%

OUTPUT

340Ω (COM'L)

453Ω (MIL)

340Ω (COM’L)

453Ω (MIL)

35 pF

5 pF

<2 ns

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Equivalent to:

THÉVENIN EQUIVALENT

158Ω (COM’L)

270Ω (MIL)

1.77V (COM'L)

OUTPUT

1.77V (MIL)

5 OR 35 pF

Parameter^[11]

V_X

Output Waveform—Measurement Level

t_ER(–)

1.5V

V_OH

0.5V

V_X

t_ER(+)

t_EA(+)

t_EA(–)

2.6V

1.5V

V_the

V_OL

V_OH

0.5V

V_X

0.5V

V_OL

(d) Test Waveforms

Switching Characteristics Over the Operating Range^[12]

Parameter

Description

Unit

Combinatorial Mode Parameters

[13, 14, 15]

t_PD

Input to Combinatorial Output

ns

[13, 14, 15]

t_PDL

Input to Output Through Transparent Input or Output Latch

Input to Output Through Transparent Input and Output Latches

Input to Output Enable

t_PDLL

[13, 14, 15]

t_EA

[11, 13]

t_ER

Input to Output Disable

Input Register Parameters

t_WL

Clock or Latch Enable Input LOW Time^[8]

ns

Notes:

11.

t_ERmeasured with 5-pF AC Test Load and t_EAmeasured with 35-pF AC Test Load.

12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.

13. Logic Blocks operating in Low-Power Mode, add t_LPto this spec.

14. Outputs using Slow Output Slew Rate, add t_SLEWto this spec.

15. When V_CCO= 3.3V, add t_3.3IOto this spec.

Document #: 38-03007 Rev. *C

Page 17 of 62

Ultra37000 CPLD Family

Switching Characteristics Over the Operating Range^[12](continued)

Parameter

Description

Unit

ns

t_WH

t_IS

Clock or Latch Enable Input HIGH Time^[8]

Input Register or Latch Set-up Time

Input Register or Latch Hold Time

ns

t_IH

ns

[13, 14, 15]

t_ICO

Input Register Clock or Latch Enable to Combinatorial Output

Input Register Clock or Latch Enable to Output Through Transparent Output Latch

ns

t_ICOL

ns

Synchronous Clocking Parameters

[14, 15]

t_CO

Synchronous Clock (CLK₀, CLK₁, CLK₂, or CLK₃) or Latch Enable to Output

ns

[13]

t_S

Set-Up Time from Input to Sync. Clk (CLK₀, CLK₁, CLK₂, or CLK₃) or Latch Enable

Register or Latch Data Hold Time

t_H

[13, 14, 15]

[13]

t_CO2

Output Synchronous Clock (CLK₀, CLK₁, CLK₂, or CLK₃) or Latch Enable to Combinatorial Output ns

Delay (Through Logic Array)

t_SCS

Output Synchronous Clock (CLK₀, CLK₁, CLK₂, or CLK₃) or Latch Enable to Output Synchronous ns

Clock (CLK₀, CLK₁, CLK₂, or CLK₃) or Latch Enable (Through Logic Array)

[13]

t_SL

t_HL

Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK₀ns

CLK₁, CLK₂, or CLK₃) or Latch Enable

Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK₀,

CLK₁, CLK₂, or CLK₃) or Latch Enable

ns

Product Term Clocking Parameters

[13, 14, 15]

t_COPT

t_SPT

Product Term Clock or Latch Enable (PTCLK) to Output

ns

Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)

Register or Latch Data Hold Time

t_HPT

[13]

t_ISPT

Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or

Latch Enable (PTCLK)

t_IHPT

Buried Register Used as an Input Register or Latch Data Hold Time

ns

[13, 14, 15]

t_CO2PT

Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)

Pipelined Mode Parameters

[13]

t_ICS

Input Register Synchronous Clock (CLK₀, CLK₁, CLK₂, or CLK₃) to Output Register Synchronous ns

Clock (CLK₀, CLK₁, CLK₂, or CLK₃)

Operating Frequency Parameters

f_MAX1Maximum Frequency with Internal Feedback (Lesser of 1/t_SCS, 1/(t_S+ t_H), or 1/t_CO

f_MAX2Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t_WL+ t_WH),

[5]

)

MHz

[5]

1/(t_S+ t_H), or 1/t_CO

)

[5]

f_MAX3

f_MAX4

Maximum Frequency with External Feedback (Lesser of 1/(t_CO+ t_S) or 1/(t_WL+ t_WH

)

MHz

Maximum Frequency in Pipelined Mode (Lesser of 1/(t_CO+ t_IS), 1/t_ICS, 1/(t_WL+ t_WH), 1/(t_IS+ t_IH), MHz

[5]

or 1/t_SCS

)

Reset/Preset Parameters

t_RW

Asynchronous Reset Width^[5]

ns

[13]

t_RR

Asynchronous Reset Recovery Time^[5]

Asynchronous Reset to Output

Asynchronous Preset Width^[5]

[13, 14, 15]

t_RO

t_PW

[13]

t_PR

Asynchronous Preset Recovery Time^[5]

[13, 14, 15]

t_PO

User Option Parameters

Asynchronous Preset to Output

t_LP

Low Power Adder

ns

t_SLEW

t_3.3IO

Slow Output Slew Rate Adder

3.3V I/O Mode Timing Adder^[5]

Document #: 38-03007 Rev. *C

Page 18 of 62

Ultra37000 CPLD Family

Switching Characteristics Over the Operating Range^[12](continued)

Parameter

Description

Unit

JTAG Timing Parameters

t_{S JTAG}

t_{H JTAG}

t_{CO JTAG}

f_JTAG

Set-up Time from TDI and TMS to TCK^[5]

Hold Time on TDI and TMS^[5]

Falling Edge of TCK to TDO^[5]

ns

Maximum JTAG Tap Controller Frequency^[5]

Switching Characteristics Over the Operating Range^[12]

200 MHz 167 MHz 154 MHz 143 MHz

125 MHz

100 MHz

83 MHz

66 MHz

Parameter

Unit

Combinatorial Mode Parameters

[13, 14, 15]

t_PD

6

11

12

8

6.5

12.5

13.5

8.5

7.5

14.5

15.5

11

8.5

16

17

13

10

12

15

20

22

24

ns

[13, 14, 15]

t_PDL

16.5

17.5

14

17

18

16

19

20

19

t_PDLL

[13, 14, 15]

t_EA

[11, 13]

t_ER

8

8.5

11

14

Input Register Parameters

t_WL

t_WH

t_IS

2.5

2

2.5

2

2.5

2

2.5

2

3

2

3

4

3

5

ns

3

5

2.5

4

t_IH

2

4

[13, 14, 15]

t_ICO

11

12

11

12

11

12

12.5

14

12.5

16

18

19

21

24

26

t_ICOL

Synchronous Clocking Parameters

[14, 15]

t_CO

4

4.5

11

6

6.5^[16]

6.5^[17]

8^[18]

10

ns

[13]

t_S

4

0

4

0

5

0

5

0

5.5^[16]

0

6^[17]

0

8^[18]

0

10

0

t_H

[13, 14, 15]

[13]

t_CO2

t_SCS

9.5

10

12

14

16

19

24

15

0

5

7.5

0

6

7.5

0

6.5

8.5

0

7

9

0

8^[16]

10

0

10

12

0

12

15

0

[13]

t_SL

t_HL

Product Term Clocking Parameters

[13, 14, 15]

t_COPT

t_SPT

7

10

15

13

19

13

19

13

21

15

24

20

ns

2.5

0

2.5

0

2.5

0

3

5

0

9

5.5

0

6

7

t_HPT

[13]

t_ISPT

t_IHPT

0

6

6.5

7.5

11

14

19

30

[13, 14,

t_CO2PT

12

14

15]

Pipelined Mode Parameters

[13]

t_ICS

5

6

7

8^[16]

10

12

15

ns

Notes:

16. The following values correspond to the CY37512 and CY37384 devices: t_CO= 5 ns, t_S= 6.5 ns, t_SCS= 8.5 ns, t_ICS= 8.5 ns, f_MAX1= 118 MHz.

17. The following values correspond to the CY37192V and CY37256V devices: t_CO= 6 ns, t_S= 7 ns, f_MAX2= 143 MHz, f_MAX3= 77 MHz, and f_MAX4= 100 MHz;

and for the CY37512 devices: t_S= 7 ns.

18. The following values correspond to the CY37512V and CY37384V devices: t_CO= 6.5 ns, t_S= 9.5 ns, and f_MAX2= 105 MHz.

Document #: 38-03007 Rev. *C

Page 19 of 62

Ultra37000 CPLD Family

Switching Characteristics Over the Operating Range^[12](continued)

200 MHz 167 MHz 154 MHz 143 MHz 125 MHz

100 MHz

83 MHz

66 MHz

Parameter

Operating Frequency Parameters

Unit

f_MAX1

f_MAX2

f_MAX3

f_MAX4

200

125

167

200

125

167

154

200

105

154

143

167

91

125^[16]

100

83

125^[18]

66

100

50

MHz

154

83

153^[17]

80^[17]

100

62.5

83

125

118

66

Reset/Preset Parameters

t_RW

8

10

12

14

15

17

20

22

26

20

22

26

ns

[13]

t_RR

10

[13, 14, 15]

t_RO

12

13

14

15

18

21

t_PW

8

10

12

14

15

17

[13]

t_PR

10

[13, 14, 15]

t_PO

12

User Option Parameters

t_LP

2.5

3

2.5

3

2.5

3

2.5

3

2.5

3

2.5

3

2.5

3

2.5 ns

ns

t_SLEW

3

[19]

t_3.3IO

0.3

0.3 ns

JTAG Timing Parameters

t_{S JTAG}

t_{H JTAG}

t_{CO JTAG}

f_JTAG

0

ns

20

ns

20 MHz

Switching Waveforms

Combinatorial Output

INPUT

t

PD

COMBINATORIAL

OUTPUT

Note:

19. Only applicable to the 5V devices.

Document #: 38-03007 Rev. *C

Page 20 of 62

Ultra37000 CPLD Family

Switching Waveforms (continued)

Registered Output with Synchronous Clocking

INPUT

t

S

H

SYNCHRONOUS

CLOCK

t

CO

REGISTERED

OUTPUT

t

CO2

REGISTERED

OUTPUT

t

WL

WH

SYNCHRONOUS

CLOCK

Registered Output with Product Term Clocking

Input Going Through the Array

INPUT

t

HPT

SPT

PRODUCT TERM

CLOCK

t

COPT

REGISTERED

OUTPUT

Registered Output with Product Term Clocking

Input Coming From Adjacent Buried Register

INPUT

t

IHPT

ISPT

PRODUCT TERM

CLOCK

t

CO2PT

REGISTERED

OUTPUT

Document #: 38-03007 Rev. *C

Page 21 of 62

Ultra37000 CPLD Family

Switching Waveforms (continued)

Latched Output

INPUT

t

HL

SL

LATCH ENABLE

t

CO

PDL

LATCHED

OUTPUT

Registered Input

REGISTERED

INPUT

t

IH

IS

INPUT REGISTER

CLOCK

t

ICO

COMBINATORIAL

OUTPUT

t

WL

WH

CLOCK

Clock to Clock

INPUT REGISTER

CLOCK

t

SCS

ICS

OUTPUT

REGISTER CLOCK

Document #: 38-03007 Rev. *C

Page 22 of 62

Ultra37000 CPLD Family

Switching Waveforms (continued)

Latched Input

LATCHED INPUT

t

IH

IS

LATCH ENABLE

t

ICO

PDL

COMBINATORIAL

OUTPUT

t

WL

WH

LATCH ENABLE

Latched Input and Output

LATCHED INPUT

t

PDLL

LATCHED

OUTPUT

t

SL

ICOL

t

HL

INPUT LATCH

ENABLE

t

ICS

OUTPUT LATCH

ENABLE

t

WL

WH

LATCH ENABLE

Document #: 38-03007 Rev. *C

Page 23 of 62

Ultra37000 CPLD Family

Switching Waveforms (continued)

Asynchronous Reset

t

RW

INPUT

t

RO

REGISTERED

OUTPUT

t

RR

CLOCK

Asynchronous Preset

t

PW

INPUT

t

PO

REGISTERED

OUTPUT

t

PR

CLOCK

Output Enable/Disable

INPUT

t

EA

ER

OUTPUTS

Document #: 38-03007 Rev. *C

Page 24 of 62

Ultra37000 CPLD Family

Power Consumption

Typical 5.0V Power Consumption

CY37032

60

50

40

30

20

10

High Speed

Low Power

0

50

100

150

200

250

Frequency (M Hz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 5.0V, T_A= Room Temperature

V

CY37064

90

80

70

60

50

40

30

20

10

0

High Speed

Low Power

0

20

40

60

80

100

120

140

160

180

Frequency (M Hz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 5.0V, T_A= Room Temperature

V

Document #: 38-03007 Rev. *C

Page 25 of 62

Ultra37000 CPLD Family

Typical 5.0V Power Consumption (continued)

CY37128

160

140

120

100

80

High Speed

Low Power

60

40

20

0

20

40

60

80

100

120

140

160

180

Frequency (M Hz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 5.0V, T_A= Room Temperature

V

CY37192

300

250

200

150

100

50

High Speed

Low Power

0

20

40

60

80

100

120

140

160

180

Frequency (M Hz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

V_CC= 5.0V, T_A= Room Temperature

Document #: 38-03007 Rev. *C

Page 26 of 62

Ultra37000 CPLD Family

Typical 5.0V Power Consumption (continued)

CY37256

300

High Speed

250

200

150

100

50

Low Power

0

20

40

60

80

100

120

140

160

180

Frequency (M Hz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 5.0V, T_A= Room Temperature

V

CY37384

500

450

400

350

300

250

200

150

100

50

High Speed

Low Power

0

20

40

60

80

100

120

140

160

Frequency (MHz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 5.0V, T_A= Room Temperature

V

Document #: 38-03007 Rev. *C

Page 27 of 62

Ultra37000 CPLD Family

Typical 5.0V Power Consumption (continued)

CY37512

600

High Speed

500

400

300

200

100

0

Low Power

0

20

40

60

80

100

120

140

160

Frequency (M Hz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 5.0V, T_A= Room Temperature

V

Typical 3.3V Power Consumption

CY37032V

30

High Speed

25

20

15

10

5

Low Power

0

20

40

60

80

100

120

140

160

Frequency (MHz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

V_CC= 3.3V, T_A= Room Temperature

Document #: 38-03007 Rev. *C

Page 28 of 62

Ultra37000 CPLD Family

Typical 3.3V Power Consumption (continued)

CY37064V

45

40

35

30

25

20

15

10

5

High Speed

Low Power

0

20

40

60

80

100

120

140

Frequency (MHz)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

V

_CC= 3.3V, T_A= Room Temperature

CY37128V

80

70

60

50

40

30

20

10

0

H igh S peed

Low P ow er

0

20

40

60

80

100

120

140

F requ ency (M H z)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

V_CC= 3.3V, T_A= Room Temperature

Document #: 38-03007 Rev. *C

Page 29 of 62

Ultra37000 CPLD Family

Typical 3.3V Power Consumption (continued)

CY37192V

1 2 0

1 0 0

8 0

6 0

4 0

2 0

0

H ig h S p e e d

L o w P o w e r

0

2 0

4 0

6 0

F re q u e n c y (M H z )

8 0

1 0 0

1 2 0

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

V

_CC= 3.3V, T_A= Room Temperature

CY37256V

1 4 0

1 2 0

1 0 0

8 0

H ig h S p e e d

L o w P o w e r

6 0

4 0

2 0

0

2 0

4 0

6 0

8 0

1 0 0

1 2 0

F re q u e n c y (M H z )

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 3.3V, T_A= Room Temperature

V

Document #: 38-03007 Rev. *C

Page 30 of 62

Ultra37000 CPLD Family

Typical 3.3V Power Consumption (continued)

CY37384V

200

180

160

140

120

100

8 0

H igh S peed

Low P ow er

6 0

4 0

2 0

0

1 0

20

30

40

50

6 0

70

80

90

Freq uency (M H z)

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 3.3V, T_A= Room Temperature

V

CY37512V

2 5 0

2 0 0

1 5 0

1 0 0

5 0

H ig h S p e e d

L o w P o w e r

0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

F re q u e n c y (M H z )

The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.

_CC= 3.3V, T_A= Room Temperature

V

Document #: 38-03007 Rev. *C

Page 31 of 62

Ultra37000 CPLD Family

Pin Configurations^[20]

44-pin TQFP (A44)

Top View

44 43 42 41 40 39 38 37 36 35 34

I/O /TDI

27

1

I/O /TCK

5

33

I/O

6

I/O

26

32

31

2

3

4

5

6

I/O

7

I/O

25

I/O

24

CLK /I

30

29

28

27

2

0

JTAG

CLK /I

EN

GND

4

1

GND

I

3

CLK /I

7

1

8

0

CLK /I

3

I/O

26

25

24

23

8

2

I/O

23

I/O

22

I/O

9

I/O

10

I/O

11

10

11

I/O

21

12 13 14 15 16 17 18 19 20 21 22

44-pin PLCC (J67) / CLCC (Y67)

Top View

6

5

4

3

2

1

44 43 42 41 40

I/O /TDI

27

I/O

26

39

38

37

36

35

34

33

32

31

30

29

I/O /TCK

5

7

I/O

6

8

9

10

11

12

I/O

25

I/O

24

I/O

7

CLK₂/I₀

JTAG_EN

CLK /I

4

1

GND

I

3

CLK /I

13

14

15

16

17

1

0

CLK₃/I₂

I/O

8

I/O

23

I/O

9

I/O

22

I/O

10

11

21

18 19 20 21 22 23 24 25 26 27 28

Note:

20. For 3.3V versions (Ultra37000V), V_CCO= V_CC

.

Document #: 38-03007 Rev. *C

Page 32 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

48-ball Fine-Pitch BGA (BA50)

Top View

1

2

3

4

I/O

5

I/O

6

7

8

A

B

C

D

E

F

I/O

TCK

V

I/O

V

I/O

5

CC

3

2

1

0

31

29

30

28

25

22

20

18

CC

27

TDI

V

I/O

CLK / I

1 4

CC

4

7

26

24

CLK / I

GND

I

3

2

0

6

JTAG

CLK / I

3 2

EN

8

9

23

CLK / I

I/O

V

CC

0

1

12

11

14

10

15

16

17

21

I/O

V

I/O

13

TMS

CC

19

TDO

84-lead PLCC (J83) / CLCC (Y84)

Top View

11 10

9

8

7

6

5

4

3

2

84 83 82 81 80 79 78 77 76 75

1

GND

74

I/O

12

13

14

15

16

17

8

9

73

I/O

55

/TDI

72

71

70

69

68

67

I/O

54

53

52

/TCK

I/O

10

11

I/O

12

I/O

51

50

49

48

I/O

13

14

18

19

20

21

15

66

CLK /I

0

CLK /I

3

4

3

65

64

V

CCO

GND

22

23

V

63

62

61

60

59

58

CCO

CLK /I

1

16

17

CLK /I

2

I/O

24

25

I/O

47

I/O

46

18

26

27

28

I/O

45

I/O

19

20

21

I/O

44

I/O

43

57

56

55

54

29

I/O

42

I/O

22

23

30

I/O

41

31

I/O

40

32 33

36 37

40 41 42

46 47 48 49 50 51 52 53

43 44 45

GND

34 35

38 39

Note:

21. This pin is a N/C, but Cypress recommends that you connect it to V_CCto ensure future compatibility.

Document #: 38-03007 Rev. *C

Page 33 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

100-lead TQFP (A100)

Top View

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

TDI

TCK

75

74

73

1

GND

V

CCO

2

3

4

I/O

8

55

54

I/O

9

72

71

I/O

10

11

53

52

51

50

49

48

5

6

7

8

I/O

70

69

I/O

12

13

14

15

68

9

67

66

10

11

12

13

CLK /I

3

CLK /I

4

3

0

65

64

GND

NC

V

CCO

N/C

GND

CLK

63

62

V

CCO

14

15

16

17

CLK /I

2

/I

1

61

60

59

I/O

I O

16

/

47

46

I/O

17

18

I/O

45

18

19

20

21

58

I/O

19

20

21

44

43

57

56

55

54

53

I/O

42

41

I/O

22

23

22

23

I/O

40

GND

NC

V

CCO

NC

24

25

52

51

26 27 28 29 30 31 32 33 34 35 36

38 39 40 41 42 43 44 45 46 47 48 49 50

37

Document #: 38-03007 Rev. *C

Page 34 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

100-ball Fine-Pitch BGA (BB100) for CY37064V

Top View

1

2

3

4

5

6

7

8

9

10

I/O

A

B

C

D

NC

I/O

7

6

5

2

62

63

60

58

59

57

55

56

I/O

V

CC

NC

9

8

4

1

I/O

TCK

NC

V

I/O

NC

I/O

V

TDI

I/O

10

11

CC

3

61

51

CC

54

I/O

NC

I/O

CLK

I/O

12

15

13

0

52

49

3

53

/ I

4

E

I/O

CLK

NC

GND

I/O

CLK

/ I

14

0

48

2

50

/ I

0

3

F

I/O

NC

I/O

NC

I

I/O

17

22

16

19

2

47

G

CLK

I/O

NC

1

21

18

46

45

44

43

/ I

1

H

J

I/O

TMS

V

I/O

NC

I/O

V

TDO

I/O

23

24

CC

20

29

32

33

34

42

35

36

CC

41

NC

I/O

NC

I/O

39

26

25

28

27

31

30

37

38

40

K

I/O

NC

100-ball Fine-Pitch BGA (BB100) for CY37128V

Top View

1

NC

2

3

4

5

6

7

8

9

10

I/O

A

B

C

I/O

9

8

7

6

5

4

3

2

1

76

77

78

74

72

73

71

68

67

70

69

66

I/O

V

CC

I/O

11

10

I/O

V

I/O

V

CC

12

13

CC

75

63

TCK

NC

TDI

D

E

I/O

CLK

I/O

14

17

15

18

16

19

0

79

64

61

3

65

62

/ I

4

CLK

GND

I/O

CLK

/ I

I/O

0

60

2

/ I

0

3

JTAG

EN

F

I/O

I

I/O

22

27

21

26

20

24

59

55

58

54

2

57

G

CLK

I/O

NC

1

23

56

40

53

/ I

1

H

I/O

V

I/O

V

I/O

28

33

CC

25

39

52

CC

47

51

50

TMS

TDO

J

I/O

V

I/O

29

30

32

31

35

34

CC

38

41

42

43

44

45

46

48

49

K

I/O

NC

36

37

Document #: 38-03007 Rev. *C

Page 35 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

160-Lead TQFP (A160) / CQFP (U162)

for CY37128(V) and CY37256(V)

Top View

GND

1

V

120

119

118

117

CCO

I/O

16

2

I/O

111

I/O

3

17

I/O

I/O /TDI

108

110

109

4

I/O

18

19

5

116

115

I/O /TCK

20

6

I/O

107

I/O

21

7

I/O

106

114

113

112

I/O

22

8

I/O

105

I/O

23

9

I/O

104

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

GND

111

110

I/O

24

I/O

103

I/O

102

I/O

25

109

108

107

106

I/O

26

I/O

101

I/O

27

I/O

100

I/O

28

I/O

99

I/O

29

105

104

I/O

98

97

96

I/O

30

I/O

31

103

102

101

100

CLK /I

3

CLK /I

4

3

0

V

GND

CCO

GND

V

CCO

CLK /I

2

I/O

95

99

98

1

32

33

34

35

36

37

38

39

I/O

94

97

96

95

94

I/O

93

I/O

92

I/O

91

90

93

92

I/O

89

88

91

90

89

GND

I/O

40

I/O

87

86

88

87

I/O

41

I/O

42

85

84

86

85

84

I/O

43

I/O

44

83

82

I/O

45

46

47

83

82

81

I/O

81

80

GND

V

CCO

Document #: 38-03007 Rev. *C

Page 36 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

160-Lead TQFP (A160) for CY37192(V)

Top View

GND

NC

1

V

120

119

118

117

CCO

2

I/O

104

I/O

3

16

I/O

TDI

I/O

103

102

4

I/O

17

18

5

116

115

TCK

6

101

I/O

19

7

I/O

114

113

112

100

99

I/O

20

8

I/O

21

9

98

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

GND

111

110

I/O

22

I/O

97

I/O

96

I/O

23

109

108

107

106

I/O

24

I/O

95

I/O

25

I/O

94

I/O

26

I/O

93

I/O

27

105

104

I/O

92

91

90

I/O

28

I/O

29

103

102

101

100

CLK /I

3

CLK /I

4

3

0

V

GND

CCO

GND

V

CCO

CLK /I

2

I/O

89

99

98

1

30

31

32

33

34

35

36

37

I/O

88

97

96

95

94

I/O

87

I/O

86

I/O

85

84

93

92

I/O

83

82

91

90

89

GND

I/O

38

I/O

81

80

88

87

I/O

39

I/O

40

79

78

86

85

84

I/O

41

I/O

42

77

76

I/O

43

44

45

83

82

81

I/O

75

NC

GND

V

CCO

Document #: 38-03007 Rev. *C

Page 37 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

208-Lead PQFP (N208) / CQFP (U208)

Top View

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

GND

I/O

20

I/O

21

I/O

22

I/O

23

I/O

24

TCK

I/O

25

I/O

26

I/O

27

I/O

28

I/O

29

GND

I/O

30

I/O

31

I/O

32

I/O

33

I/O

34

NC

I/O

35

I/O

36

I/O

37

I/O

38

I/O

39

V

CCO

1

2

3

4

5

6

7

8

I/O

139

138

137

136

135

TDI

I/O

134

I/O

9

133

132

131

130

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

GND

I/O

129

I/O

128

127

126

125

124

123

122

121

120

CLK /I

3

4

3

V

CLK /I

CC

0

GND

V

CCO

V

GND

NC

CCO

GND

CLK /I

2

I/O

119

I/O

118

I/O

117

I/O

116

I/O

115

NC

I/O

114

I/O

113

I/O

112

I/O

111

CLK /I

1

I/O

1

40

41

42

43

44

45

46

47

48

49

I/O

39

40

41

I/O

GND

110

GND

I/O

109

I/O

50

51

52

53

54

42

I/O

108

43

44

I/O

107

I/O

106

45

I/O

105

NC

46

47

48

49

I/O

104

55

56

57

58

59

I/O

103

I/O

V

I/O

102

I/O

101

I/O

100

GND

50

51

52

CC0

Document #: 38-03007 Rev. *C

Page 38 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

256-Ball PBGA (BG256)

Top View

1

2

3

4

5

6

7

I/O

8

9

10

11

12

13

14

NC

15

16

17

18

19

20

A

B

C

D

E

F

GND

I/O

NC

I/O

NC

I/O

A

B

C

D

E

F

21

20

16

18

12

15

17

9

7

8

4

5

6

0

1

2

3

190

191

189

187

188

CC

186

185

184

183

182

181

180

178

175

174

173

169

168

166

162

160

156

154

152

149

145

I/O

NC

I/O

NC

I/O

23

19

22

11

171

172

170

167

164

161

158

155

151

147

NC

I/O

NC

I/O

NC

I/O

165

14

10

13

179

177

176

I/O

NC

GND

NC

V

GND

NC

V

GND I/O

V

NC

GND I/O

TDI

24

27

30

33

35

39

42

43

47

49

52

54

57

61

64

68

71

CCO

I/O

159

26

25

28

31

34

37

41

45

163

TCK

V

NC

CCO

G

H

J

I/O

G

H

J

32

29

157

153

150

146

NC

GND

GND I/O

I/O

38

40

44

36

148

144

CC

K

L

V

CLK /I

3 4

NC

K

L

CC

I/O

V

CLK /I I/O

NC

46

2

3

143

141

137

134

M

N

P

R

T

CLK /I CLK /I I/O

I/O

M

N

P

R

T

0

1

48

139

140

136

133

130

127

123

117

115

142

138

135

132

129

126

125

120

119

I/O

GND

GND I/O

I/O

50

53

56

60

63

67

70

73

51

55

59

62

66

69

72

77

I/O

58

131

V

NC

CCO

I/O

65

124

128

122

121

118

116

U

V

W

Y

GND

I/O

V

I/O

GND

I/O

V

I/O

GND I/O

V

NC

TDO

NC

GND I/O

U

V

W

Y

76

78

79

80

CCO

82

85

86

87

91

92

93

94

CC

98

97

96

102

101

100

112

109

107

106

CCO

I/O

I

I/O

114

I/O

75

74

81

83

84

88

89

90

2

105

104

103

113

110

108

I/O

NC

95

TMS

4

NC

I/O

NC

17

NC

99

111

1

2

3

5

6

7

8

9

10

11

12

13

14

15

16

18

19

20

Document #: 38-03007 Rev. *C

Page 39 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

256-Ball Fine-Pitch BGA (BB256)

Top View

1

2

3

4

5

6

7

8

9

10

11

12

I/O

13

I/O

14

I/O

15

16

A

B

C

D

E

F

GND

I/O

V

I/O

GND

I/O

V

GND

26

25

24

23

22

20

19

18

17

16

CC

11

18

CC

17

16

6

7

2

7

GND

I/O

GND

I/O

5

I/O

1

I/O

6

I/O

1

I/O

6

I/O

5

GND

27

28

31

34

38

42

15

14

10

18

17

16

15

14

13

11

16

15

I/O

NC

I/O

1

I/O

4

I/O

0

I/O

5

I/O

0

NC

I/O

3

I/O

4

29

9

4

3

2

1

0

19

18

16

I/O

NC

I/O

0

I/O

3

I/O

9

I/O

4

I/O

9

I/O

0

I/O

1

I/O

2

32

30

33

37

41

47

51

55

59

61

64

13

8

18

17

16

15

14

13

12

16

I/O

9

V

I/O

8

I/O

3

I/O

8

I/O

7

I/O

8

I/O

9

35

21

36

40

46

50

54

58

72

73

74

75

76

12

7

CC

17

15

V

TCK

V

I/O

8

I/O

2

V

TDI

I/O

4

I/O

5

I/O

6

V

CC

6

18

14

10

CC

G

H

J

I/O

V

I/O

7

I/O

8

I/O

9

CLK

I/O

0

I/O

1

I/O

2

I/O

3

43

CC

39

45

5

14

3

15

/I

4

GND

CLK

I/O

GND

I/O

4

I/O

5

CLK

/I

I/O

6

I/O

7

GND

0

44

48

52

86

CC

2

/I

0

3

NC

I/O

0

I/O

1

I

2

I/O

2

I/O

3

49

14

K

L

I/O

CLK

I/O

1

I/O

5

V

I/O

6

I/O

7

I/O

8

I/O

9

57

56

60

62

65

67

69

1

53

91

92

93

94

95

96

97

98

99

10

13

CC

13

12

13

/I

1

V

TMS

V

I/O

2

V

TDO

I/O

2

I/O

3

I/O

4

V

CC

M

N

P

R

T

I/O

V

I/O

3

I/O

8

I/O

2

I/O

7

I/O

9

I/O

0

I/O

1

63

66

68

77

78

82

83

10

11

13

12

I/O

4

I/O

9

I/O

3

NC

I/O

6

I/O

7

I/O

8

87

88

89

90

10

NC

I/O79

I/O

0

I/O

5

I/O

0

I/O

4

I/O

8

NC

I/O

4

I/O

5

84

11

12

GND

I/O

GND

I/O

6

I/O

1

I/O

5

I/O

9

I/O

1

I/O

3

GND

70

71

80

81

85

11

12

GND

V

I/O

7

V

I/O

6

I/O

0

I/O

2

GND

CC

12

Document #: 38-03007 Rev. *C

Page 40 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

352-Lead BGA (BG352)

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

A

B

C

D

E

F

GND GND I/O

GND NC I/O

I/O

I/O I/O

I/O

GND GND

19

18

37

36

41

43

46

51

54

57

58

15

17

16

13

14

12

34

35

33

21

31

32

30

20

28

29

25

26

10

11

7

8

6

4

5

3

1

263

260

261

259

257

258

256

254

255

253

239

252

237

234

232

231

233

236

229

228

230

243

250

249

251

248

246

247

244

245

225

226

I/O

V

I/O

GND

2

CC

240

224

222

221

218

215

212

209

206

I/O

I/O I/O

I/O

23

39

42

45

48

49

52

55

38

40

27

24

9

0

262

238

235

227

223

220

217

214

213

210

207

197

202

199

198

195

192

175

172

169

168

189

186

182

154

NC

NC I/O

V

NC GND GND

V

GND GND NC

V

NC

NC I/O

CCO

TCK I/O

NC

TDI I/O

I/O

44

47

22

63

242

241

219

216

211

208

205

204

G

H

J

I/O

V

50

CCO

53

CCO

K

L

NC

NC I/O

56

I0

GND

GND GND GND GND GND GND

GND I/O

I4 I/O

59

M

N

P

R

T

I/O

I1

GND

I3 I/O

I/O

61

64

65

68

71

88

91

94

95

74

77

81

109

60

203

200

CC

V

I/O

V

I/O

CC

62

67

70

85

86

89

92

73

76

79

108

CCO

201

196

193

178

177

174

171

190

187

184

155

180

148

149

I/O

V

66

69

84

87

90

93

72

75

78

80

82

CCO

GND

NC

GND I/O

NC I/O

I/O

194

179

176

173

170

191

188

185

183

181

U

V

W

Y

V

I/O

CCO

I/O

110

153

152

AA I/O

AB I/O

AC I/O

111

N/C

NC I/O

I/O

N/C

NC I/O

I/O

V

NC GND GND

V

GND GND NC

V

I/O

NC

112

113

102

101

CCO

150

161

162

151

163

165

164

AD I/O

I/O

I2 I/O

I/O

83

117

116

118

97

100

105

103

104

120

106

107

123

121

122

126

124

125

129

127

128

133

130

132

136

134

135

139

137

138

142

140

141

157

143

156

159

160

158

166

144

167

146

147

145

AE GND NC I/O

AF GND GND I/O

I/O

V

CC

I/O

NC GND

GND GND

115

114

119

98

99

I/O

TMS I/O

I/O

TDO I/O

96

131

Document #: 38-03007 Rev. *C

Page 41 of 62

Ultra37000 CPLD Family

Pin Configurations^[20](continued)

400-Ball Fine-Pitch BGA (BB400)

Top View

A

B

C

D

E

F

GND GND

NC

I/O

V

I/O

GND GND I/O

7

V

I/O

9

I/O

3

I/O

2

I/O

0

NC

GND GND

17

16

15

20

19

14

13

12

18

35

29

28

27

26

34

33

37

CC

11

25

CC

23

25

24

21

23

22

25

24

22

21

20

19

17

18

23

22

24

23

GND GND GND

NC

I/O

GND GND I/O

6

I/O

8

I/O

1

I/O

9

NC

GND GND GND

10

25

NC

GND GND GND I/O

I/O

GND GND I/O

5

I/O

7

I/O

8

I/O

5

GND GND GND

NC

9

8

25

I/O

NC

GND I/O

I/O

GND GND I/O

4

I/O

5

I/O

6

I/O

1

I/O

4

I/O

3

GND

NC

I/O

22

44

46

21

22

41

50

49

56

25

24

25

23

24

21

20

7

I/O

NC

I/O

3

I/O

3

I/O

4

I/O

0

I/O

8

NC

I/O

1

I/O

2

I/O

5

I/O

6

43

23

42

7

4

3

2

1

0

26

25

24

22

I/O

NC

I/O

2

I/O

2

I/O

9

I/O

7

I/O

0

I/O

1

I/O

0

I/O

2

I/O

3

I/O

4

47

45

40

39

48

55

65

69

85

90

75

77

32

6

25

24

22

21

20

19

17

16

18

22

G

H

J

I/O

1

V

I/O

6

I/O

7

I/O

8

I/O

9

I/O

2

I/O

3

I/O

4

I/O

5

53

52

51

38

36

54

64

68

84

72

74

76

11

96

99

10

31

5

CC

24

21

V

TCK

V

I/O

9

I/O

0

V

TDI

I/O

6

I/O

0

I/O

1

V

CC

30

60

61

66

70

12

CC

26

20

19

16

13

14

CC

I/O

V

I/O

8

I/O

2

I/O

3

CLK

/I

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

59

58

57

CC

62

63

20

19

20

3

4

K

L

GND GND GND GND I/O

CLK

/I

GND GND I/O

8

I/O

9

CLK

/I

I/O

0

I/O

1

GND GND GND GND

0

2

3

NC

GND GND I/O

3

I/O

5

I

2

I/O

6

I/O

7

67

19

M

N

P

R

T

I/O

CLK

/I

I/O

6

I/O

2

I/O

2

I/O

4

V

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

89

88

87

86

91

92

10

11

71

12

13

19

CC

17

16

17

18

15

17

1

V

TMS

V

I/O

8

I/O

7

I/O

3

I/O

2

V

TDO

I/O

0

I/O

8

I/O

9

V

CC

I/O

4

V

I/O

9

I/O

4

I/O

7

I/O

3

I/O

1

I/O

2

I/O

3

I/O

0

I/O

1

I/O

2

I/O

3

95

80

82

83

94

79

81

93

78

11

73

11

10

11

16

18

16

15

16

17

18

15

17

18

17

19

18

I/O

8

I/O

5

I/O

7

I/O

0

I/O

0

I/O

5

I/O

8

I/O

4

I/O

5

NC

I/O

4

I/O

5

I/O

6

I/O

9

I/O

1

12

16

I/O

0

I/O

9

NC

I/O

6

I/O

8

I/O

2

I/O

1

I/O

1

I/O

6

I/O

9

I/O

6

I/O

6

I/O

7

NC

I/O

4

I/O

5

I/O

7

I/O

0

10

15

16

U

V

W

Y

NC

GND I/O

1

I/O

2

I/O

9

I/O

4

I/O

3

I/O

2

GND GND I/O

0

I/O

7

I/O

8

I/O

0

I/O

1

I/O

3

GND

NC

I/O

8

11

97

10

15

14

NC

GND GND GND I/O

3

I/O

5

V

I/O

3

GND GND I/O

1

V

I/O

9

I/O1

44

I/O

2

GND GND GND

NC

CC

GND GND GND

NC

I/O

6

I/O

4

GND GND I/O

2

I/O

0

I/O

5

I/O

7

NC

GND GND GND

14

GND GND

NC

I/O

0

I/O

1

I/O

7

I/O

5

GND GND I/O

3

I/O

1

I/O

6

I/O

8

I/O

9

NC

GND GND

98

14

Document #: 38-03007 Rev. *C

Page 42 of 62

Ultra37000 CPLD Family

Ordering Information

C Y 3 7 5 1 2 V P 4 0 0 - 8 3 B B C

Cypress Semiconductor ID

Family Type

37 = Ultra37000 Family

Operating Conditions

Commercial

Industrial

Military

0°C to +70°C

-40°C to +85°C

-55°C to +125°C

Macrocell Density

32 = 32 Macrocells

64 = 64 Macrocells

128 = 128 Macrocells

192 = 192 Macrocells

256 = 256 Macrocells

384 = 384 Macrocells

512 = 512 Macrocells

Package Type

A

U

N

= Thin Quad Flat Pack (TQFP)

= Ceramic Quad Flat Pack (CQFP)

= Plastic Quad Flat Pack (PQFP)

Operating Reference Voltage

V = 3.3V Supply Voltage

(5.0V if not specified)

NT = Thermally Enhanced Plastic Quad Flat Pack

(EQFP)

J

Y

= Plastic Leaded Chip Carrier (PLCC)

= Ceramic Leaded Chip Carrier (CLCC)

Pin Count

BG = Ball Grid Array (BGA)

BA = Fine-Pitch Ball Grid Array (FBGA)

0.8mm Lead Pitch

BB = Fine-Pitch Ball Grid Array (FBGA)

1.0mm Lead Pitch

P44 = 44 Leads

P48 = 48 Leads

P84 = 84 Leads

P100 = 100 Leads

P160 = 160 Leads

P208 = 208 Leads

P256 = 256 Leads

P352 = 352 Leads

P400 = 400 Leads

Speed

125 = 125 MHz

200 = 200 MHz 100 = 100 MHz

167 = 167 MHz 83 = 83 MHz

154 = 154 MHz 66 = 66 MHz

143 = 143 MHz

5.0V Ordering Information

Macro-

cells

Speed

(MHz)

Package

Name

Operating

Range

Ordering Code

CY37032P44-200AC

CY37032P44-200JC

CY37032P44-154AC

CY37032P44-154JC

CY37032P44-154AI

CY37032P44-154JI

CY37032P44-125AC

CY37032P44-125JC

CY37032P44-125AI

CY37032P44-125JI

CY37064P44-200AC

CY37064P44-200JC

CY37064P84-200JC

CY37064P100-200AC

Package Type

32

200

A44

J67

A44

J67

A44

J67

A44

J67

A44

J67

A44

J67

J83

A100

44-Lead Thin Quad Flat Pack

Commercial

Industrial

44-Lead Plastic Leaded Chip Carrier

44-Lead Thin Quad Flat Pack

154

44-Lead Plastic Leaded Chip Carrier

44-Lead Thin Quad Flat Pack

44-Lead Plastic Leaded Chip Carrier

44-Lead Thin Quad Flat Pack

125

200

Commercial

Industrial

44-Lead Plastic Leaded Chip Carrier

44-Lead Thin Quad Flat Pack

44-Lead Plastic Leaded Chip Carrier

44-Lead Thin Quad Flat Pack

64

Commercial

44-Lead Plastic Leaded Chip Carrier

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

Document #: 38-03007 Rev. *C

Page 43 of 62

Ultra37000 CPLD Family

5.0V Ordering Information (continued)

Macro-

cells

Speed

(MHz)

Package

Name

Operating

Ordering Code

CY37064P44-154AC

CY37064P44-154JC

CY37064P84-154JC

CY37064P100-154AC

CY37064P44-154AI

CY37064P44-154JI

CY37064P84-154JI

CY37064P100-154AI

5962-9951902QYA

CY37064P44-125AC

CY37064P44-125JC

CY37064P84-125JC

CY37064P100-125AC

CY37064P44-125AI

CY37064P44-125JI

CY37064P84-125JI

CY37064P100-125AI

5962-9951901QYA

CY37128P84-167JC

CY37128P100-167AC

CY37128P160-167AC

CY37128P84-125JC

CY37128P100-125AC

CY37128P160-125AC

CY37128P84-125JI

CY37128P100-125AI

CY37128P160-125AI

5962-9952102QYA

CY37128P84-100JC

CY37128P100-100AC

CY37128P160-100AC

CY37128P84-100JI

CY37128P100-100AI

CY37128P160-100AI

5962-9952101QYA

CY37192P160-154AC

CY37192P160-125AC

CY37192P160-125AI

CY37192P160-83AC

CY37192P160-83AI

Package Type

Range

64

154

A44

J67

44-Lead Thin Quad Flat Pack

Commercial

44-Lead Plastic Leaded Chip Carrier

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

44-Lead Thin Quad Flat Pack

J83

A100

A44

Industrial

J67

44-Lead Plastic Leaded Chip Carrier

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

44-Lead Ceramic Leadless Chip Carrier

44-Lead Thin Quad Flat Pack

J83

A100

Y67

Military

125

A44

Commercial

J67

44-Lead Plastic Leaded Chip Carrier

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

44-Lead Thin Quad Flat Pack

J83

A100

A44

Industrial

J67

44-Lead Plastic Leaded Chip Carrier

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

44-Lead Ceramic Leadless Chip Carrier

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

160-Lead Thin Quad Flat Pack

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

160-Lead Thin Quad Flat Pack

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

160-Lead Thin Quad Flat Pack

84-Lead Ceramic Leaded Chip Carrier

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

160-Lead Thin Quad Flat Pack

84-Lead Plastic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

160-Lead Thin Quad Flat Pack

84-Lead Ceramic Leaded Chip Carrier

160-Lead Thin Quad Flat Pack

J83

A100

Y67

Military

128

167

125

J83

Commercial

A100

A160

J83

Commercial

Industrial

A100

A160

J83

A100

A160

Y84

Military

100

J83

Commercial

A100

A160

J83

Industrial

A100

A160

Y84

Military

192

154

125

A160

Commercial

Industrial

83

Commercial

Industrial

Document #: 38-03007 Rev. *C

Page 44 of 62

Ultra37000 CPLD Family

5.0V Ordering Information (continued)

Macro-

cells

Speed

(MHz)

Package

Name

Operating

Ordering Code

CY37256P160-154AC

CY37256P208-154NC

CY37256P256-154BGC

CY37256P160-125AC

CY37256P208-125NC

CY37256P256-125BGC

CY37256P160-125AI

CY37256P208-125NI

CY37256P256-125BGI

5962-9952302QZC

Package Type

Range

256

154

A160

N208

160-Lead Thin Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Commercial

BG256 256-Lead Ball Grid Array

125

A160

N208

160-Lead Thin Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Commercial

Industrial

BG256 256-Lead Ball Grid Array

A160

N208

160-Lead Thin Quad Flat Pack

208-Lead Plastic Quad Flat Pack

BG256 256-Lead Ball Grid Array

U162

A160

N208

160-Lead Ceramic Quad Flat Pack

Military

83

CY37256P160-83AC

CY37256P208-83NC

CY37256P256-83BGC

CY37256P160-83AI

CY37256P208-83NI

CY37256P256-83BGI

5962-9952301QZC

160-Lead Thin Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Commercial

BG256 256-Lead Ball Grid Array

A160

N208

160-Lead Thin Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Industrial

BG256 256-Lead Ball Grid Array

U162

N208

160-Lead Ceramic Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Military

384

512

125

83

CY37384P208-125NC

CY37384P256-125BGC

CY37384P208-83NC

CY37384P256-83BGC

CY37384P208-83NI

CY37384P256-83BGI

CY37512P208-125NC

CY37512P256-125BGC

CY37512P352-125BGC

CY37512P208-100NC

CY37512P256-100BGC

CY37512P352-100BGC

CY37512P208-100NI

CY37512P256-100BGI

CY37512P352-100BGI

5962-9952502QZC

Commercial

BG256 256-Lead Ball Grid Array

N208 208-Lead Plastic Quad Flat Pack

BG256 256-Lead Ball Grid Array

N208 208-Lead Plastic Quad Flat Pack

BG256 256-Lead Ball Grid Array

N208 208-Lead Plastic Quad Flat Pack

Commercial

Industrial

125

100

Commercial

BG256 256-Lead Ball Grid Array

BG352 352-Lead Ball Grid Array

N208

208-Lead Plastic Quad Flat Pack

Commercial

Industrial

BG256 256-Lead Ball Grid Array

BG352 352-Lead Ball Grid Array

N208

208-Lead Plastic Quad Flat Pack

BG256 256-Lead Ball Grid Array

BG352 352-Lead Ball Grid Array

U208

N208

208-Lead Ceramic Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Military

83

CY37512P208-83NC

CY37512P256-83BGC

CY37512P352-83BGC

CY37512P208-83NI

CY37512P256-83BGI

CY37512P352-83BGI

5962-9952501QZC

Commercial

BG256 256-Lead Ball Grid Array

BG352 352-Lead Ball Grid Array

N208

208-Lead Plastic Quad Flat Pack

Industrial

Military

BG256 256-Lead Ball Grid Array

BG352 352-Lead Ball Grid Array

U208

208-Lead Ceramic Quad Flat Pack

Document #: 38-03007 Rev. *C

Page 45 of 62

Ultra37000 CPLD Family

3.3V Ordering Information

Macro-

cells

Speed

(MHz)

Package

Name

Operating

Ordering Code

CY37032VP44-143AC

CY37032VP48-143BAC

CY37032VP44-100AC

CY37032VP48-100BAC

CY37032VP44-100AI

CY37032VP48-100BAI

CY37064VP44-143AC

CY37064VP48-143BAC

CY37064VP100-143AC

CY37064VP100-143BBC

CY37064VP44-100AC

CY37064VP48-100BAC

CY37064VP100-100AC

CY37064VP100-100BBC

CY37064VP44-100AI

CY37064VP48-100BAI

CY37064VP100-100BBI

CY37064VP100-100AI

5962-9952001QYA

Package Type

Range

32

143

A44

BA50

A44

44-Lead Thin Quad Flat Pack

48-Lead Fine Pitch Ball Grid Array

44-Lead Thin Quad Flat Pack

48-Lead Fine Pitch Ball Grid Array

44-Lead Thin Quad Flat Pack

48-Lead Fine Pitch Ball Grid Array

44-Lead Thin Quad Flatpack

Commercial

100

Commercial

Industrial

BA50

A44

BA50

A44

64

143

100

Commercial

BA50

A100

48-Lead Fine-Pitch Ball Grid Array

100-Lead Thin Quad Flatpack

BB100 100-Lead Fine-Pitch Ball Grid Array

A44

BA50

A100

44-Lead Thin Quad Flatpack

48-Lead Fine-Pitch Ball Grid Array

100-Lead Thin Quad Flatpack

Commercial

Industrial

BB100 100-Lead Fine-Pitch Ball Grid Array

A44

44-Lead Thin Quad Flatpack

BA50

48-Lead Fine-Pitch Ball Grid Array

BB100 100-Lead Fine-Pitch Ball Grid Array

A100

Y67

100-Lead Thin Quad Flatpack

44-Lead Ceramic Leaded Chip Carrier

100-Lead Thin Quad Flat Pack

Military

128

125

83

CY37128VP100-125AC

CY37128VP100-125BBC

CY37128VP160-125AC

CY37128VP100-83AC

CY37128VP100-83BBC

CY37128VP160-83AC

CY37128VP100-83AI

CY37128VP100-83BBI

CY37128VP160-83AI

5962-9952201QYA

A100

Commercial

BB100 100-Lead Fine-Pitch Ball Grid Array

A160

A100

160-Lead Thin Quad Flat Pack

100-Lead Thin Quad Flat Pack

Commercial

Industrial

BB100 100-Lead Fine-Pitch Ball Grid Array

A160

A100

160-Lead Thin Quad Flat Pack

100-Lead Thin Quad Flat Pack

BB100 100-Lead Fine-Pitch Ball Grid Array

A160

Y84

160-Lead Thin Quad Flat Pack

84-Lead Ceramic Leaded Chip Carrier

160-Lead Thin Quad Flat Pack

Military

192

100

66

CY37192VP160-100AC

CY37192VP160-66AC

CY37192VP160-66AI

A160

Commercial

Industrial

Document #: 38-03007 Rev. *C

Page 46 of 62

Ultra37000 CPLD Family

3.3V Ordering Information (continued)

Macro-

cells

Speed

(MHz)

Package

Name

Operating

Ordering Code

CY37256VP160-100AC

CY37256VP208-100NC

CY37256VP256-100BGC

CY37256VP256-100BBC

CY37256VP160-66AC

CY37256VP208-66NC

CY37256VP256-66BGC

CY37256VP256-66BBC

CY37256VP160-66AI

CY37256VP256-66BGI

CY37256VP256-66BBI

5962-9952401QZC

Package Type

Range

256

100

A160

N208

160-Lead Thin Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Commercial

BG256 256-Lead Ball Grid Array

BB256 256-Lead Fine-Pitch Ball Grid Array

66

A160

N208

160-Lead Thin Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Commercial

Industrial

BG256 256-Lead Ball Grid Array

BB256 256-Lead Fine-Pitch Ball Grid Array

A160

160-Lead Thin Quad Flat Pack

BG256 256-Lead Ball Grid Array

BB256 256-Lead Fine-Pitch Ball Grid Array

U162

N208

160-Lead Ceramic Quad Flat Pack

208-Lead Plastic Quad Flat Pack

Military

384

512

83

66

CY37384VP208-83NC

CY37384VP256-83BGC

CY37384VP208-66NC

CY37384VP256-66BGC

CY37384VP208-66NI

CY37384VP256-66BGI

CY37512VP208-83NC

CY37512VP256-83BGC

CY37512VP352-83BGC

CY37512VP400-83BBC

CY37512VP208-66NC

CY37512VP256-66BGC

CY37512VP352-66BGC

CY37512VP400-66BBC

CY37512VP208-66NI

CY37512VP256-66BGI

CY37512VP352-66BGI

CY37512VP400-66BBI

5962-9952601QZC

Commercial

BG256 256-Lead Ball Grid Array

N208 208-Lead Plastic Quad Flat Pack

BG256 256-Lead Ball Grid Array

N208 208-Lead Plastic Quad Flat Pack

BG256 256-Lead Ball Grid Array

N208 208-Lead Plastic Quad Flat Pack

Commercial

Industrial

83

66

Commercial

BG256 256-Lead Ball Grid Array

BG352 352-Lead Ball Grid Array

BB400 400-Lead Fine-Pitch Ball Grid Array

N208

208-Lead Plastic Quad Flat Pack

Commercial

Industrial

Military

BG256 256-Lead Ball Grid Array

BG352 352-Lead Ball Grid Array

BB400 400-Lead Fine-Pitch Ball Grid Array

N208

208-Lead Plastic Quad Flat Pack

BG256 256-Lead Ball Grid Array

BG352 352-Lead Ball Grid Array

BB400 400-Lead Fine-Pitch Ball Grid Array

U208

208-Lead Ceramic Quad Flat Pack

Document #: 38-03007 Rev. *C

Page 47 of 62

Ultra37000 CPLD Family

Package Diagrams

44-lead Thin Plastic Quad Flat Pack A44

51-85064-*B

44-Lead Plastic Leaded Chip Carrier J67

51-85003-*A

Document #: 38-03007 Rev. *C

Page 48 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

44-Pin Ceramic Leaded Chip Carrier Y67

51-80014-**

Document #: 38-03007 Rev. *C

Page 49 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA BA48D

51-85109-*C

84-Lead Plastic Leaded Chip Carrier J83

51-85006-*A

Document #: 38-03007 Rev. *C

Page 50 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

84-Pin Ceramic Leaded Chip Carrier Y84

51-80095-*A

Document #: 38-03007 Rev. *C

Page 51 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

100-Pin Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-*B

Document #: 38-03007 Rev. *C

Page 52 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100

51-8 5107-*B

Document #: 38-03007 Rev. *C

Page 53 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

160-Pin Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (TQFP) A160

51-85049-*B

Document #: 38-03007 Rev. *C

Page 54 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

160-Lead Ceramic Quad Flatpack (Cavity Up) U162

51-80106-**

Document #: 38-03007 Rev. *C

Page 55 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

208-Lead Plastic Quad Flatpack N208

51-85069-*B

Document #: 38-03007 Rev. *C

Page 56 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

208-Lead Ceramic Quad Flatpack (Cavity Up) U208

51-80105-*A

Document #: 38-03007 Rev. *C

Page 57 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

256-Ball FBGA (17 x 17 mm) BB256

51-85108-*C

Document #: 38-03007 Rev. *C

Page 58 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

388-Lead PBGA (35 x 35 x 2.33 mm) BG388

51-85103-*C

Document #: 38-03007 Rev. *C

Page 59 of 62

Ultra37000 CPLD Family

Package Diagrams (continued)

400-Ball FBGA (21 x 21 x 1.4 mm) BB400

51-85111-*A

Warp is a registered trademark, and In-System Reprogrammable, ISR, Warp Professional, Warp Enterprise, and Ultra37000 are

trademarks, of Cypress Semiconductor.ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trade-

mark of Microsoft Corporation. All product and company names mentioned in this document are the trademarks of their respective

holders.

Document #: 38-03007 Rev. *C

Page 60 of 62

Ultra37000 CPLD Family

Addendum

3.3V Operating Range

(CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC)

Range

Ambient Temperature^[2]

Junction Temperature

V_CC

Commercial

0°C to +70°C

0°C to +90°C

3.3V ± 0.16V

Document #: 38-03007 Rev. *C

Page 61 of 62

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Ultra37000 CPLD Family

Document History Page

Document Title: Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs

Document Number: 38-03007

Issue

Date

Orig. of

Change

REV. ECN NO.

Description of Change

**

106272

124942

04/18/01

03/21/03

SZV

Change from Spec number: 38-00475 to 38-03007

*A

OOR

Updated 3.3V V_CCrequirements for –144 speeds

Added an Addendum

*B

*C

126262

128125

05/09/03

07/16/03

TEH

Changed pinout for CY37128V BB100 package

HOM

Obsoleted following 3.3V PLCC packaged devices:

CY37032VP44-143JC

CY37032VP44-100JC

CY37032VP44-100JI

CY37064VP44-143JC

CY37064VP84-143JC

CY37064VP44-100JC

CY37064VP84-100JC

CY37064VP44-100JI

CY37064VP84-100JI

CY37128VP84-125JC

CY37128VP84-83JC

CY37128VP84-83JI

Document #: 38-03007 Rev. *C

Page 62 of 62


型号：	CY37032VP48-100BAI
厂家：	CYPRESS
描述：	5V, 3.3V, ISR⑩ High-Performance CPLDs 5V ， 3.3V ， ISR ™高性能的CPLD
文件：	总62页 (文件大小：1780K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY37032VP48-100BAI [CYPRESS]

相关型号：

CY37032VP48-143BAC

CY37064

CY37064P

CY37064P100-125AC

CY37064P100-125AI

CY37064P100-125AXC

CY37064P100-125AXI

CY37064P100-154AC

CY37064P100-154AI

CY37064P100-200AC

CY37064P100-200ACT

CY37064P100-200AXC