CY37064P44-167YMB [CYPRESS]
EE PLD, 6.5ns, 64-Cell, CMOS, CQCC44, CERAMIC, LCC-44;
| 型号： | CY37064P44-167YMB |
| 厂家： | 
CYPRESS |
| 描述： | EE PLD, 6.5ns, 64-Cell, CMOS, CQCC44, CERAMIC, LCC-44 时钟 输入元件 可编程逻辑 |
| 文件： | 总20页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6
PRELIMINARY
CY37064
UltraLogic™ 64-Macrocell ISR™ CPLD
— t = 3.5 ns
Features
S
— t = 4.5 ns
CO
• 64 macrocells in four logic blocks
• In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
• Product-term clocking
• IEEE 1149.1 JTAG boundary scan
• Programmable slew rate control on individual I/Os
• Low power option on individual logic block basis
• 5V and 3.3V I/O capability
• User-Programmable Bus Hold capabilities on all I/Os
• Simple Timing Model
— Design changes don’t cause pinout changes
— Design changes don’t cause timing changes
• Up to 64 I/Os
— plus 5 dedicated inputs including 4 clock inputs
• High speed
• PCI compliant
• 44–100 pins in TQFP, PLCC, and CLCC packages
— f
= 167 MHz
MAX
• Pinout compatible with the CY37064V, CY37032/
37032V, CY37128/37128V, CY7C372i, CY7C373i
— t = 6.5 ns
PD
Logic Block Diagram (100-pin TQFP)
Clock/
Input
Input
1
4
4
4
36
36
LOGIC
16 I/Os
LOGIC
16 I/Os
I/O −I/O
BLOCK
BLOCK
I/O −I/O
0
15
16
36
16
16
36
48
63
A
D
PIM
16 I/Os
16 I/Os
LOGIC
BLOCK
B
LOGIC
BLOCK
C
I/O −I/O
I/O −I/O
16
32
47
16
31
32
32
TDI
37064-1
JTAG Tap
Controller
TCLK
TMS
TDO
Selection Guide
CY37064-200
CY37064-167
CY37064-125
Maximum Propagation Delay, t (ns)
6.0
4
6.5
4
10
5.5
6.5
30
PD
Minimum Set-Up, t (ns)
S
Maximum Clock to Output, t (ns)
4
4
CO
Typical Supply Current, I (mA) in Low Power Mode
30
30
CC
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA95134
•
408-943-2600
January 6, 1999
PRELIMINARY
CY37064
noise reduction. In the fast edge rate mode, outputs switch at
3V/ns max. and in the slow edge rate mode, outputs switch at
1V/ns max. There is a nominal delay for I/Os using the slow
edge rate mode.
Functional Description
The CY37064 is an In-System Reprogrammable (ISR) Com-
plex Programmable Logic Device (CPLD) and is part of the
Ultra37000™ family of high-density, high-speed CPLDs. Like
all members of the Ultra37000 family, the CY37064 is de-
signed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
3.3V or 5V I/O Operation
The CY37064 operates with a 5V supply, and can support 5V
or 3.3V I/O levels. V
connections provide the capability of
CCO
interfacing to either a 5V or 3.3V bus. By connecting the V
CCO
pins to 5V the user insures 5V TTL levels on the outputs. If
# of
# Buried
# I/O
Package
Types
V
is connected to 3.3V the output levels meet 3.3V JEDEC
Pins
Macrocells
Macrocells
CCO
standard CMOS levels and are 5V tolerant. A nominal timing
44
84
32
0
32
64
64
TQFP, PLCC
PLCC
delay is incurred on output buffers when V
This device requires 5V ISR programming.
is set to 3.3V.
CCO
100
0
TQFP
In-System Reprogramming
The CY37064 can be programmed in system using IEEE
1149.1 compliant JTAG programming protocol. The CY37064
can also be programmed on a number of traditional parallel
programmers including Cypress’s Impulse3 programmer
and industry standard third-party programmers. For an over-
view of ISR programming, refer to the Ultra37000 Family data
sheet and for UltraISR cable and software specifications, refer
to InSRkit: ISR Programming data sheet (CY3600i).
For a more detailed description of the architecture and fea-
tures of the CY37064 see the Ultra37000 family data sheet.
Fully Routable with 100% Logic Utilization
The CY37064 is designed with a robust routing architecture
which allows utilization of the entire device with a fixed pinout.
This makes Ultra37000 optimal for implementing on-board de-
sign changes using ISR without changing pinouts.
User-Programmable Bus Hold
Simple Timing Model
All outputs of the CY37064 can either be configured into bus
hold mode or left floating. When in bus hold mode, the undriv-
en outputs retain their last value with a weak latch. This feature
allows the designer the flexibility of either eliminating or includ-
ing external pull-up/pull-down resistors. Enabling this feature
affects all I/Os simultaneously.
The CY37064 features a very simple timing model with pre-
dictable delays. Unlike other high-density CPLD architectures,
there are no hidden speed delays such as fanout effects, inter-
connect delays, or expander delays. The timing model allows
for design changes with ISR without causing changes to sys-
tem performance.
Design Tools
Low Power Operation
Development software for the CY37064 is available from
Cypress’s Warp or third-party bolt-in software packages as
well as a number of third-party development packages. Please
refer to the Warp or third-party tool support data sheets for
further information.
Each Logic Block of the CY37064 can be configured as either
High-Speed (default) or Low-Power. In the Low-Power mode,
the logic block consumes approximately 50% less power and
slows down by t .
LP
Output Slew Rate Control
Each output can be configured with either a fast edge rate
(default) for high performance, or a slow edge rate for added
2
PRELIMINARY
CY37064
Pin Configurations
44-pin TQFP
Top View
44 43 42 41 40 39 38 37 36 35 34
I/O /TDI
27
1
I/O /TCLK
5
33
32
31
I/O
6
I/O
26
2
3
4
5
6
I/O
7
I/O
25
I/O
24
CLK /I
2
0
30
29
28
27
CLK /I
JTAG
4
1
EN
GND
CLK /I
GND
I
0
7
1
3
I/O 8
CLK /I
26
8
3
2
I/O
9
9
I/O
I/O
25
24
23
23
22
I/O
10
10
11
I/O
11
I/O
21
12 13 14 15 16 17 18 19 20 21 22
37064–2
44-pin PLCC/CLCC
Top View
6
5
4
3
2
1
44 43 42 41 40
I/O
27
39
38
37
36
35
34
33
32
31
30
29
/TDI
I/O
/TCLK
7
5
I/O
6
I/O
26
8
I/O
7
I/O
25
9
CLK /I
2
I/O
24
0
10
11
12
13
14
15
16
17
JTAG
CLK /I
1
EN
4
GND
GND
CLK /I
I
0
1
8
9
3
I/O
CLK /I
3
2
I/O
I/O
I/O
23
I/O
22
10
11
I/O
I/O
21
18 19 20 21 22 23 24 25 26 27 28
37064–3
3
PRELIMINARY
CY37064
Pin Configurations (continued)
84-pin PLCC
Top View
11 10
9
8
7
6
5
4
3
2
84 83 82 81 80 79 78 77 76 75
1
GND
74
I/O
I/O
12
13
14
15
16
17
8
9
73
I/O
55
/TDI
72
71
70
69
68
67
I/O
I/O
I/O
54
53
52
/TCLK
I/O
10
I/O
11
I/O
12
I/O
I/O
I/O
I/O
51
50
I/O
13
I/O
14
18
49
48
I/O
15
19
20
21
66
65
64
CLK /I
0
0
CLK /I
3
4
3
VCCO
GND
GND
22
23
VCCO
63
62
61
60
59
58
CLK /I
1
1
CLK /I
2
I/O
16
24
25
I/O
47
I/O
17
18
I/O
46
I/O
26
27
28
I/O
45
I/O
I/O
I/O
19
20
21
I/O
44
I/O
43
57
56
55
54
29
I/O
42
I/O
I/O
22
23
30
31
32
I/O
41
I/O
40
33
36 37
40 41 42
46 47 48 49 50 51 52 53
43 44 45
GND
34 35
38 39
37064-4
4
PRELIMINARY
CY37064
Pin Configurations (continued)
100-pin TQFP
Top View
100
98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
99
TDI
VCCO
TCLK
GND
1
75
74
73
2
3
4
I/O
I/O
I/O
8
55
54
I/O
I/O
9
72
71
I/O
I/O
I/O
I/O
I/O
I/O
10
11
53
52
51
50
49
48
5
6
7
8
I/O
70
69
I/O
I/O
I/O
I/O
12
13
14
15
68
9
67
66
10
11
12
13
CLK /I
3
CLK /I
4
3
0
0
65
64
GND
NC
VCCO
N/C
63
62
VCCO
GND
14
15
16
17
CLK
CLK /I
2
/I
1
1
61
60
59
I/O
I/O
I O
16
/
47
46
I/O
17
18
I/O
I/O
45
18
19
20
21
58
I/O
I/O
I/O
I/O
I/O
19
20
21
44
43
57
56
55
54
53
I/O
I/O
42
41
I/O
I/O
22
23
22
23
I/O
40
GND
NC
VCCO
NC
24
25
52
51
26 27 28 29 30 31 32 33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
37064-5
5
PRELIMINARY
CY37064
DC Voltage Applied to Outputs
Maximum Ratings
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Program Voltage .............................................4.5 to 5.5V
Current into Outputs.....................................................16 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Latch-Up Current .....................................................>200 mA
Operating Range[1]
Ambient
Temperature
Junction
Temperature
Output
Condition
[1]
Range
V
V
CCO
CC
Commercial
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
0°C to +90°C
–40°C to +125°C
–55°C to +130°C
5V
5V ± 0.25V
5V ± 0.25V
5V ± 0.5V
5V ± 0.5V
5V ± 0.5V
5V ± 0.5V
5V ± 0.25V
3.3V ± 0.3V
5V ± 0.5V
3.3V
5V
Industrial
3.3V
5V
3.3V ± 0.3V
5V ± 0.5V
[2]
Military
3.3V
3.3V ± 0.3V
Shaded areas contain advance information.
Notes:
1. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the
Ultra37000 family devices see the Ultra37000 family data sheet.
2. TA is the “instant on” case temperature.
6
PRELIMINARY
CY37064
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
V
Output HIGH Voltage
V
= Min.
I
OH
(Com’l/Ind)
= –3.2 mA
2.4
V
OH
CC
[3]
[3]
I
I
I
I
I
= –2.0 mA (Mil)
2.4
V
V
V
V
V
V
OH
OH
OH
OL
OL
[4]
V
Output HIGH Voltage with Out-
put Disabled
V
V
= Max.
= Min.
= 0 µA (Com’l/Ind)
= –50 µA (Com’l/Ind)
4.0
3.6
0.5
0.5
OHZ
CC
CC
[7]
[4]
[3]
V
Output LOW Voltage
= 16 mA (Com’l/Ind)
OL
[3]
= 12 mA (Mil)
V
Input HIGH Voltage
Input LOW Voltage
Guaranteed Input Logical HIGH voltage
2.0
V
CCmax
IH
IL
[5]
for all inputs
V
Guaranteed Input Logical LOW voltage
for all inputs
–0.5
0.8
V
[5]
I
I
Input Load Current
V = GND OR V
CC
–10
–50
0
10
50
µA
µA
µA
IX
I
Output Leakage Current
V = GND or V , Output Disabled
O CC
OZ
V
= Max., V = 3.3V, Output
−70
−125
CC
O
[4]
Disabled
I
I
I
I
I
Output Short Circuit
Current
V
V
V
V
V
= Max., V = 0.5V
OUT
–30
+75
–75
–160
mA
µA
µA
µA
µA
OS
CC
CC
CC
CC
CC
[6, 7]
Input Bus Hold LOW Sustaining
Current
= Min., V = 0.8V
IL
BHL
Input Bus Hold HIGH
Sustaining Current
= Min., V = 2.0V
BHH
BHLO
BHHO
IH
Input Bus Hold LOW Overdrive
Current
= Max.
= Max.
+500
–500
Input Bus Hold HIGH Overdrive
Current
Inductance[7]
44-lead 44-lead
44-lead 84-lead 100-lead
Parameter
Description
Maximum Pin Inductance
Test Conditions
= 5.0V at f = 1 MHz
TQFP
PLCC
CLCC
PLCC
TQFP
Unit
L
V
2
5
2
8
8
nH
IN
Capacitance[7]
Parameter
Description
Test Conditions
= 5.0V at f = 1 MHz at T = 25°C
Max.
8
Unit
C
C
Input/Output Capacitance
Clock Signal Capacitance
V
V
pF
pF
I/O
IN
IN
A
= 5.0V at f = 1 MHz at T = 25°C
12
CLK
A
Endurance Characteristics[7]
Parameter
Description
Test Conditions
Min.
1,000
Typ.
Unit
Cycles
[1]
N
Minimum Reprogramming Cycles
Normal Programming Conditions
10,000
Notes:
3. OH = –2 mA, IOL = 2 mA for TDO.
I
4. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered
significantly by a small leakage current. Note that all I/Os are output disabled during ISR programming. Refer to the application note “Understanding Bus Hold”
for additional information.
5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
6. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
7. Tested initially and after any design or process changes that may affect these parameters.
7
PRELIMINARY
CY37064
AC Test Loads and Waveforms
238 (COM'L)
Ω
238 (COM'L)
Ω
319 (MIL)
Ω
319 (MIL)
Ω
ALL INPUT PULSES
90%
10%
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
170 (COM'L)
Ω
170 (COM'L)
Ω
35 pF
5 pF
236 (MIL)
Ω
236 (MIL)
Ω
<2 ns
<2 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
37064-6
(c)
37064-8
37064-7
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
99 (COM'L)
Ω
136 (MIL)
Ω
2.08V (COM'L)
OUTPUT
2.13V (MIL)
5 OR 35 pF
37064-9
[8]
Parameter
V
Output Waveform—Measurement Level
X
t
t
t
1.5V
2.6V
1.5V
ER(–)
ER(+)
EA(+)
V
OH
0.5V
0.5V
V
X
37064-10
V
X
V
V
OL
37064-11
V
OH
0.5V
0.5V
X
37064-12
t
V
the
EA(–)
V
X
V
OL
37064-13
(d) Test Waveforms
Note:
8.
tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
8
PRELIMINARY
CY37064
[9]
Switching Characteristics Over the Operating Range
37064-200
37064-167
37064-125
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
Combinatorial Mode Parameters
[10, 11, 12]
t
t
Input to Combinatorial Output
6
6.5
10
10
13
ns
ns
PD
[10, 11, 12]
[10, 11, 12]
Input to Output Through Transparent Input or
Output Latch
8.5
PDL
t
Input to Output Through Transparent Input and
Output Latches
10.5
12
15
ns
PDLL
[10, 11, 12]
t
t
Input to Output Enable
Input to Output Disable
9
9
10
10
14
14
ns
ns
EA
[10]
ER
Input Register Parameters
[7]
t
t
t
t
t
Clock or Latch Enable Input LOW Time
2.5
2.5
2
2.5
2.5
2
3
3
2
2
ns
ns
ns
ns
ns
WL
WH
IS
[7]
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
2
2
IH
[10, 11, 12]
[10, 11, 12]
Input Register Clock or Latch Enable to Combina-
torial Output
11
12
11
12
12.5
16
ICO
t
Input Register Clock or Latch Enable to Output
Through Transparent Output Latch
ns
ICOL
Synchronous Clocking Parameters
[11, 12]
t
Synchronous Clock (CLK , CLK , CLK , or CLK )
or Latch Enable to Output
4
4
6.5
14
ns
ns
CO
0
1
2
3
[10]
t
Set-Up Time from Input to Sync. Clk (CLK , CLK ,
4
0
4
0
5.5
0
S
0
1
CLK , or CLK ) or Latch Enable
2
3
t
t
Register or Latch Data Hold Time
Output Synchronous Clock (CLK , CLK , CLK , or
ns
ns
H
[10, 11, 12]
[10]
9.5
10
CO2
0
1
2
CLK ) or Latch Enable to Combinatorial Output
3
Delay (Through Logic Array)
t
Output Synchronous Clock (CLK , CLK , CLK , or
5
6
8
ns
SCS
0
1
2
CLK ) or Latch Enable to Output Synchronous
3
Clock (CLK , CLK , CLK , or CLK ) or Latch
0
1
2
3
Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch
to Output Register Synchronous Clock (CLK
[10]
t
t
7.5
0
7.5
0
10
0
ns
ns
SL
0
CLK , CLK , or CLK ) or Latch Enable
1
2
3
Hold Time for Input Through Transparent Latch
from Output Register Synchronous Clock (CLK ,
HL
0
CLK , CLK , or CLK ) or Latch Enable
1
2
3
Product Term Clocking Parameters
[10, 11, 12]
t
Product Term Clock or Latch Enable (PTCLK) to
Output
7
7.5
–2
11
–2
ns
ns
COPT
t
Set-Up Time from Input to Product Term Clock or
Latch Enable (PTCLK)
2.5
2.5
2.5
2.5
3
3
SPT
t
t
Register or Latch Data Hold Time
ns
ns
HPT
[10]
Set-Up Time for Buried Register used as an Input
Register from Input to Product Term Clock or Latch
Enable (PTCLK)
–2
ISPT
Notes:
9. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
10. Logic Blocks operating in low power mode, add tLP to this spec.
11. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
12. When VCCO= 3.3V, add t3.3IO to this spec.
9
PRELIMINARY
CY37064
[9]
Switching Characteristics Over the Operating Range (continued)
37064-200
37064-167
37064-125
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
t
t
Buried Register Used as an Input Register or Latch
Data Hold Time
6
6.5
9
ns
IHPT
[10, 11, 12]
Product Term Clock or Latch Enable (PTCLK) to
Output Delay (Through Logic Array)
12
14
19
ns
CO2PT
Pipelined Mode Parameters
[10]
t
Input Register Synchronous Clock (CLK , CLK ,
5.0
6
8
ns
ICS
0
1
CLK , or CLK ) to Output Register Synchronous
2
3
Clock (CLK , CLK , CLK , or CLK )
0
1
2
3
Operating Frequency Parameters
f
Maximum Frequency with Internal Feedback
200
200
167
200
125
158
MHz
MHz
MAX1
[7]
(Lesser of 1/t
, 1/(t + t ), or 1/t
)
SCS
S
H
CO
f
Maximum Frequency Data Path in Output Regis-
tered/Latched Mode (Lesser of 1/(t + t ), 1/(t
S
MAX2
WL
WH
+ t ), or 1/t
)
H
CO
f
f
Maximum Frequency with External Feedback
(Lesser of 1/(t + t ) or 1/(t + t ))
125
154
125
154
83
MHz
MHz
MAX3
CO
S
WL
WH
Maximum Frequency in Pipelined Mode (Lesser of
125
MAX4
1/(t
+ t ), 1/t , 1/(t
)
+ t ), 1/(t + t ), or
CO
IS
ICS
WL
WH
IS
IH
1/t
SCS
Reset/Preset Parameters
[7]
t
t
t
t
t
t
Asynchronous Reset Width
8
8
10
12
ns
ns
ns
ns
ns
ns
RW
[10]
[7]
[7]
Asynchronous Reset Recovery Time
Asynchronous Reset to Output
10
10
RR
RO
[10, 11, 12]
12
12
13
13
15
15
[7]
Asynchronous Preset Width
8
8
10
12
PW
[10]
Asynchronous Preset Recovery Time
Asynchronous Preset to Output
10
10
PR
[10, 11, 12]
PO
User Option Parameters
t
t
t
Low Power Adder
4
2
4
2
4
2
ns
ns
ns
LP
Slow Output Slew Rate Adder
3.3V I/O mode timing Adder
SLEW
3.3IO
0.1
0.1
0.1
JTAG Timing Parameters
t
t
t
f
Set-Up Time from TDI and TMS to TCK
Hold Time on TDI and TMS
0
0
0
ns
ns
S JTAG
H JTAG
CO JTAG
JTAG
20
20
20
Falling Edge of TCK to TDO
20
20
20
20
20
20
ns
Maximum JTAG Tap Controller Frequency
MHz
10
PRELIMINARY
CY37064
Typical I Characteristics
cc
90
80
70
60
50
40
30
20
10
0
High Speed
Low Power
0
20
40
60
80
100
120
140
160
180
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
Vcc = 5.0V, TA = Room Temperature
11
PRELIMINARY
CY37064
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
37064-14
Registered Output with Synchronous Clocking
INPUT
tS
tH
SYNCHRONOUS
CLOCK
tCO
REGISTERED
OUTPUT
tCO2
REGISTERED
OUTPUT
tWH
tWL
SYNCHRONOUS
CLOCK
37064-15
Registered Output with Product Term Clocking
Input Going Through the Array
INPUT
tSPT
tHPT
PRODUCT TERM
CLOCK
tCOPT
REGISTERED
OUTPUT
tWH
tWL
PRODUCT TERM
CLOCK
37064-16
12
PRELIMINARY
CY37064
Switching Waveforms (continued)
Registered Output with Product Term Clocking
Input Coming From Adjacent Buried Register
INPUT
tISPT
tIHPT
PRODUCT TERM
CLOCK
tCO2PT
REGISTERED
OUTPUT
tWH
tWL
PRODUCT TERM
CLOCK
37064-17
Latched Output
INPUT
tSL
tHL
LATCH ENABLE
tPDL
tCO
LATCHED
OUTPUT
37064-18
Registered Input
REGISTERED
INPUT
tIS
tIH
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
CLOCK
37064-19
13
PRELIMINARY
CY37064
Switching Waveforms (continued)
Clock to Clock
INPUT REGISTER
CLOCK
tICS
tSCS
OUTPUT
REGISTER CLOCK
37064-20
Latched Input
LATCHED INPUT
tIS
tIH
LATCH ENABLE
tPDL
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
LATCH ENABLE
37064-21
Latched Input and Output
LATCHED INPUT
tPDLL
LATCHED
OUTPUT
tICOL
tSL
tHL
INPUT LATCH
ENABLE
tICS
OUTPUT LATCH
ENABLE
tWH
tWL
LATCH ENABLE
37064-22
14
PRELIMINARY
CY37064
Switching Waveforms (continued)
Asynchronous Reset
tRW
INPUT
tRO
REGISTERED
OUTPUT
tRR
CLOCK
37064-23
Asynchronous Preset
tPW
INPUT
tPO
REGISTERED
OUTPUT
tPR
CLOCK
37064-24
Output Enable/Disable
INPUT
tER
tEA
OUTPUTS
37064–25
15
PRELIMINARY
CY37064
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
100-Pin Thin Quad Flatpack
200
CY37064P100-200AC
CY37064P84-200JC
CY37064P44-200AC
CY37064P44-200JC
CY37064P100-167AC
CY37064P84-167JC
CY37064P44-167AC
CY37064P44-167JC
CY37064P100-167AI
CY37064P84-167JI
CY37064P44-167AI
CY37064P44-167JI
CY37064P44-167YMB
CY37064P100-125AC
CY37064P84-125JC
CY37064P44-125AC
CY37064P44-125JC
CY37064P100-125AI
CY37064P84-125JI
CY37064P44-125AI
CY37064P44-125JI
CY37064P44-125YMB
A100
J83
Commercial
Commercial
Industrial
84-Pin Plastic Leaded Chip Carrier
44-Pin Thin Quad Flatpack
A44
J67
44-Pin Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
167
A100
J83
84-Pin Plastic Leaded Chip Carrier
44-Pin Thin Quad Flatpack
A44
J67
44-Pin Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
A100
J83
84-Pin Plastic Leaded Chip Carrier
44-Pin Thin Quad Flatpack
A44
J67
44-Pin Plastic Leaded Chip Carrier
44-Pin Ceramic Leadless Chip Carrier
100-Pin Thin Quad Flatpack
Y67
A100
J83
Military
125
Commercial
84-Pin Plastic Leaded Chip Carrier
44-Pin Thin Quad Flatpack
A44
J67
44-Pin Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
A100
J83
Industrial
84-Pin Plastic Leaded Chip Carrier
44-Pin Thin Quad Flatpack
A44
J67
44-Pin Plastic Leaded Chip Carrier
44-Pin Ceramic Leadless Chip Carrier
Y67
Military
In-System Reprogrammable, ISR, UltraLogic, FLASH370, Ultra37000, InSRkit, Impulse3, and Warp are trademarks of
Cypress Semiconductor Corporation.
Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
Document #: 38−00714–A
16
PRELIMINARY
CY37064
Package Diagrams
44-Lead Thin Plastic Quad Flat Pack A44
51-85064-B
17
PRELIMINARY
CY37064
Package Diagrams (continued)
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
44-Lead Plastic Leaded Chip Carrier J67
51-85003-A
18
PRELIMINARY
CY37064
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
51-85006-A
19
PRELIMINARY
CY37064
Package Diagrams (continued)
44-Pin Ceramic Leaded Chip Carrier
Y67
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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