CY37064VP84-143JC [CYPRESS]
EE PLD, 8.5ns, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84;
| 型号： | CY37064VP84-143JC |
| 厂家： | 
CYPRESS |
| 描述： | EE PLD, 8.5ns, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84 时钟 输入元件 可编程逻辑 |
| 文件： | 总19页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY37064V
TM
TM
UltraLogic 3.3V 64-Macrocell ISR CLPD
— t = 10 ns
Features
PD
— t = 5.5 ns
S
• 64 macrocells in four logic blocks
• 3.3V In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
— t = 6.5 ns
CO
• Product-term clocking
• IEEE 1149.1 JTAG boundary scan
• Programmable slew rate control on individual I/Os
• Low power option on individual logic block basis
• User-Programmable Bus Hold capabilities on all I/Os
• Simple Timing Model
— Design changes don’t cause pinout changes
— Design changes don’t cause timing changes
• IEEE standard 3.3V operation
— 3.3V ISR
[1]
— 5V tolerant
• PCI compliant
• 44 100 pins in TQFP, PLCC and CLCC packages
−
• Up to 64 I/Os
• Pinout compatible with the CY37064, CY37032/37032V,
CY37128/37128V
— plus 5 dedicated inputs including 4 clock inputs
• High speed
— f
= 125 MHz
MAX
Logic Block Diagram (100-pin TQFP)
Clock/
Input
Input
1
4
4
4
36
36
LOGIC
16 I/Os
LOGIC
16 I/Os
BLOCK
I/O0−I/O15
I/O16−I/O31
BLOCK
I/O48−I/O63
16
36
16
16
36
A
D
16 I/Os
PIM
16 I/Os
LOGIC
BLOCK
B
LOGIC
BLOCK
C
16
I/O32−I/O47
32
32
TDI
JTAG Tap
Controller
TCLK
TMS
TDO
37064V-1
Selection Guide
CY37064V-143
CY37064V-100
Maximum Propagation Delay, t (ns)
8.5
5.0
6.0
30
12
7.5
6.5
30
PD
Minimum Set-Up, t (ns)
S
Maximum Clock to Output, t (ns)
CO
Typical Supply Current, I (mA) in Low Power Mode
CC
Note:
1. Due to the 5V tolerant nature of the I/Os, the I/Os are not clamped to VCC
.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA95134
•
408-943-2600
January 6, 1999
PRELIMINARY
CY37064V
Functional Description
the logic block consumes approximately 50% less power and
slows down by t
.
LP
The CY37064V is an In-System Reprogrammable (ISR) Com-
plex Programmable Logic Device (CPLD) and is part of the
Ultra37000™ family of high-density, high-speed CPLDs. Like
all members of the Ultra37000 family, the CY37064V is de-
signed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Output Slew Rate Control
Each output can be configured with either a fast edge rate
(default) for high performance, or a slow edge rate for added
noise reduction. In the fast edge rate mode, outputs switch at
3V/ns max. and in the slow edge rate mode, outputs switch at
1V/ns max. There is a nominal delay for I/Os using the slow
edge rate mode.
# of
# Buried
Macrocells
# I/O
Macrocells
Package
Types
Pins
44
84
32
0
32
64
64
TQFP, PLCC
PLCC
In-System Reprogramming
The CY37064V can be programmed in system using IEEE
1149.1 compliant JTAG programming protocol. The
CY37064V can also be programmed on a number of traditional
parallel programmers including Cypress’s Impulse3 pro-
grammer and industry standard third-party programmers. For
an overview of ISR programming, refer to the Ultra37000 Fam-
ily data sheet and for UltraISR cable and software specifica-
tions, refer to InSRkit: ISR Programming data sheet
(CY3600i).
100
0
TQFP
For a more detailed description of the architecture and fea-
tures of the CY37064V see the Ultra37000 family data sheet.
Fully Routable with 100% Logic Utilization
The CY37064V is designed with a robust routing architecture
which allows utilization of the entire device with a fixed pinout.
This makes Ultra37000 optimal for implementing on-board de-
sign changes using ISR without changing pinouts.
User-Programmable Bus Hold
All outputs of the CY37064V can either be configured into bus
hold mode or left floating. When in bus hold mode, the undriv-
en outputs retain their last value with a weak latch. This feature
allows the designer the flexibility of either eliminating or includ-
ing external pull-up/pull-down resistors. Enabling this feature
affects all I/Os simultaneously.
Simple Timing Model
The CY37064V features a very simple timing model with pre-
dictable delays. Unlike other high-density CPLD architectures,
there are no hidden speed delays such as fanout effects, inter-
connect delays, or expander delays. The timing model allows
for design changes with ISR without causing changes to sys-
tem performance.
Design Tools
Development software for the CY37064V is available from Cy-
press’s Warp or third-party bolt-in software packages as well
as a number of third-party development packages. Please re-
fer to the Warp or third-party tool support data sheets for fur-
ther information.
Low-Power Operation
Each Logic Block of the CY37064V can be configured as either
High-Speed (default) or Low-Power. In the Low-Power mode,
2
PRELIMINARY
CY37064V
Pin Configurations
44-pin TQFP
Top View
44 43 42 41 40 39 38 37 36 35 34
I/O /TDI
27
1
I/O /TCLK
5
33
32
31
I/O
6
I/O
26
2
3
4
5
6
I/O
7
I/O
25
I/O
24
CLK /I
2
0
30
29
28
27
CLK /I
JTAG
4
1
EN
GND
CLK /I
GND
I
0
7
1
3
I/O 8
CLK /I
26
8
3
2
I/O
9
9
I/O
I/O
25
24
23
23
22
I/O
10
10
11
I/O
11
I/O
21
12 13 14 15 16 17 18 19 20 21 22
37064V–2
44-pin PLCC/CLCC
Top View
6
5
4
3
2
1
44 43 42 41 40
I/O
I/O
I/O
I/O
39
38
37
36
35
34
33
32
31
30
29
/TDI
I/O
/TCLK
7
27
26
25
24
5
I/O
6
8
I/O
7
9
CLK /I
2
0
10
11
12
13
14
15
16
17
JTAG
CLK /I
1
EN
4
GND
GND
CLK /I
I
0
1
8
9
3
I/O
CLK /I
3
2
I/O
I/O
I/O
23
I/O
22
10
11
I/O
I/O
21
18 19 20 21 22 23 24 25 26 27 28
37064V–3
3
PRELIMINARY
CY37064V
Pin Configurations (continued)
84-pin PLCC
Top View
11 10
9
8
7
6
5
4
3
2
84 83 82 81 80 79 78 77 76 75
1
GND
74
I/O
I/O
12
13
14
15
16
17
8
9
73
I/O
55
/TDI
72
71
70
69
I/O
I/O
I/O
54
53
52
/TCLK
I/O
10
I/O
11
I/O
12
I/O
I/O
51
50
I/O
13
68
67
I/O
14
18
I/O
I/O
49
48
I/O
15
19
20
21
66
CLK /I
0
0
CLK /I
3
4
3
65
64
VCC
GND
VCC
GND
22
23
63
62
61
60
59
58
CLK /I
1
1
I/O
16
I/O
17
CLK /I
2
24
25
I/O
47
I/O
46
I/O
18
26
27
28
I/O
45
I/O
I/O
I/O
19
20
21
I/O
44
I/O
43
57
56
55
54
29
I/O
42
I/O
I/O
22
23
30
31
I/O
41
I/O
40
32 33
36 37
40 41 42
46 47 48 49 50 51 52 53
43 44 45
GND
34 35
38 39
37064V-4
4
PRELIMINARY
CY37064V
Pin Configurations (continued)
100-pin TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TDI
VCC
TCLK
GND
75
74
73
1
2
3
4
I/O
I/O
I/O
55
54
8
I/O
I/O
9
72
71
I/O
I/O
I/O
I/O
I/O
I/O
10
11
53
52
51
50
49
48
5
6
7
8
I/O
70
69
I/O
I/O
I/O
I/O
12
13
14
15
68
9
67
66
10
11
12
13
CLK /I
3
CLK /I
0
4
3
0
65
64
GND
NC
VCC
N/C
63
62
VCC
GND
14
15
16
17
CLK /I
2
CLK
/I
1
1
61
60
59
I/O
I/O
I O
16
/
47
46
I/O
17
18
I/O
I/O
45
18
19
20
21
58
I/O
I/O
I/O
I/O
I/O
19
20
21
44
43
57
56
55
54
53
I/O
I/O
42
41
I/O
I/O
22
23
22
23
I/O
40
GND
NC
VCC
NC
24
25
52
51
47
48 49 50
26 27 28 29 30 31 32 33 34 35 36
38 39 40 41 42 43 44 45 46
37
37064V-5
Maximum Ratings
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage...........................................3.0V to 3.6V
Current into Outputs...................................................... 8 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Latch-Up Current..................................................... >200 mA
5
PRELIMINARY
CY37064V
Operating Range[2]
Ambient
Temperature
Junction
Temperature
[2]
Range
V
CC
Commercial
0°C to + 70°C
0°C to + 90°C
–40°C to + 125°C
–55°C to + 130°C
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
Industrial
–40°C to + 85°C
[3]
Military
–55°C to + 125°C
Shaded areas contain advance information.
Electrical Characteristics Over the Operating Range
Parameter
Description
Output HIGH Voltage
Test Conditions
Min.
Max.
Unit
[4]
V
V
V
= Min.
= Min.
I
I
I
I
= –4 mA (Com’l)
2.4
V
OH
CC
CC
OH
OH
OL
OL
[4]
= –3 mA (Mil)
[4]
V
Output LOW Voltage
= 8 mA (Com’l)
0.5
V
OL
[4]
= 6 mA (Mil)
V
Input HIGH Voltage
Input LOW Voltage
Guaranteed Input Logical HIGH voltage for
all inputs
2.0
V
V
V
IH
IL
CCmax
[5]
V
Guaranteed Input Logical LOW voltage for
–0.5
0.8
[5]
all inputs
I
I
I
I
Input Load Current
V = GND OR V
CC
–10
–50
–30
+75
10
50
µA
µA
mA
µA
IX
I
Output Leakage Current
Output Short Circuit Current
V = GND or V , Output Disabled
O CC
OZ
[6, 7]
V
V
= Max., V
= 0.5V
–160
OS
CC
CC
OUT
Input Bus Hold LOW Sustaining
Current
= Min., V = 0.8V
IL
BHL
I
I
I
Input Bus Hold HIGH Sustaining
Current
V
V
V
= Min., V = 2.0V
–75
µA
µA
µA
BHH
CC
CC
CC
IH
Input Bus Hold LOW Overdrive
Current
= Max.
= Max.
+500
–500
BHLO
BHHO
Input Bus Hold HIGH Overdrive
Current
Inductance[7]
44-lead
44-lead 44-lead 84-lead 100-lead
Parameter
Description
Maximum Pin Inductance
Test Conditions
= 3.3V at f = 1 MHz
TQFP
PLCC
CLCC
PLCC
TQFP
Unit
nH
L
V
2
5
2
8
8
IN
Notes:
2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the
Ultra37000 family devices see the Ultra37000 family data sheet.
3. TA is the “instant on” case temperature.
4. IOH = –2 mA, IOL = 2 mA for TDO.
5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
6. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
7. Tested initially and after any design or process changes that may affect these parameters.
6
PRELIMINARY
CY37064V
Capacitance[7]
Parameter
Description
Test Conditions
= 3.3V at f = 1 MHz at T = 25°C
Max.
8
Unit
pF
C
C
Input/Output Capacitance
Clock Signal Capacitance
V
V
I/O
IN
IN
A
= 3.3V at f = 1 MHz at T = 25°C
12
pF
CLK
A
Endurance Characteristics[7]
Parameter
Description
Minimum Reprogramming Cycles
Test Conditions
Min.
1,000
Typ.
10,000
Unit
[2]
N
Normal Programming Conditions
Cycles
AC Test Loads and Waveforms
238 (COM'L)
Ω
238 (COM'L)
Ω
319 (MIL)
Ω
319 (MIL)
Ω
ALL INPUT PULSES
5V
5V
3.0V
GND
90%
10%
90%
10%
OUTPUT
OUTPUT
170 (COM'L)
Ω
170 (COM'L)
Ω
35 pF
5 pF
236 (MIL)
Ω
236 (MIL)
Ω
<2 ns
<2 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(c)
37064V-6
37064V-7
37064V-8
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
99 (COM'L)
Ω
136 (MIL)
Ω
2.08V (COM'L)
2.13V (MIL)
OUTPUT
5 OR 35 pF
37064V-9
[8]
Parameter
V
Output Waveform−Measurement Level
X
t
t
t
1.5V
2.6V
1.5V
ER(–)
ER(+)
EA(+)
V
OH
0.5V
0.5V
V
X
37064V-10
V
X
V
V
OL
37064V-11
V
OH
0.5V
0.5V
X
37064V-12
t
V
the
EA(–)
V
X
V
OL
37064V-13
(d) Test Waveforms
Note:
8.
tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
7
PRELIMINARY
CY37064V
[9]
Switching Characteristics Over the Operating Range
37064V-143
37064V-100
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Combinatorial Mode Parameters
[10, 11]
t
t
t
Input to Combinatorial Output
8.5
12
12
16.5
17
ns
ns
ns
PD
[10, 11]
Input to Output Through Transparent Input or Output Latch
PDL
[10, 11]
Input to Output Through Transparent Input and Output
Latches
13.5
PDLL
[10, 11]
t
t
Input to Output Enable
Input to Output Disable
13
13
16
16
ns
ns
EA
[10]
ER
Input Register Parameters
[7]
t
t
t
t
t
Clock or Latch Enable Input LOW Time
2.5
2.5
2
3
3
ns
ns
ns
ns
ns
WL
WH
IS
[7]
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
2.5
2.5
2
IH
[10, 11]
[10, 11]
Input Register Clock or Latch Enable to Combinatorial
Output
12.5
14
16
18
ICO
t
Input Register Clock or Latch Enable to Output Through
Transparent Output Latch
ns
ICOL
Synchronous Clocking Parameters
[11]
t
Synchronous Clock (CLK , CLK , CLK , or CLK ) or Latch
Enable to Output
6
6
ns
ns
CO
0
1
2
3
[10]
t
Set-Up Time from Input to Synchronous Clock (CLK , CLK ,
5
0
7
0
S
0
1
CLK , or CLK ) or Latch Enable
2
3
t
t
Register or Latch Data Hold Time
Output Synchronous Clock (CLK , CLK , CLK , or CLK ) or
ns
ns
H
[10, 11]
[10]
12
16
CO2
0
1
2
3
Latch Enable to Combinatorial Output Delay (Through Logic
Array)
t
t
t
Output Synchronous Clock (CLK , CLK , CLK , or CLK ) or
7
9
0
10
12
0
ns
ns
ns
SCS
0
1
2
3
Latch Enable to Output Synchronous Clock (CLK , CLK ,
0
1
CLK , or CLK ) or Latch Enable (Through Logic Array)
2
3
[10]
Set-Up Time from Input Through Transparent Latch to Out-
put Register Synchronous Clock (CLK , CLK , CLK , or
SL
HL
0
1
2
CLK ) or Latch Enable
3
Hold Time for Input Through Transparent Latch from Output
Register Synchronous Clock (CLK , CLK , CLK , or CLK )
0
1
2
3
or Latch Enable
Product Term Clocking Parameters
[10, 11]
t
Product Term Clock or Latch Enable (PTCLK) to Output
11
13
ns
ns
COPT
SPT
t
Set-Up Time from Input to Product Term Clock or Latch
Enable (PTCLK)
3
3
3
3
t
t
Register or Latch Data Hold Time
ns
ns
HPT
[10]
Set-Up Time for Buried Register Used as an Input Register
from Input to Product Term Clock or Latch Enable (PTCLK)
−2
−2
ISPT
Notes:
9. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
10. Logic Blocks operating in low power mode, add tLP to this spec.
11. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
8
PRELIMINARY
CY37064V
[9]
Switching Characteristics Over the Operating Range (continued)
37064V-143
37064V-100
Parameter
Description
Min.
Max.
Min.
Max.
Unit
t
t
Buried Register Used as an Input Register or Latch Data
Hold Time
7.5
11
ns
IHPT
[10, 11]
Product Term Clock or Latch Enable (PTCLK) to Output
Delay (Through Logic Array)
19
21
ns
ns
CO2PT
Pipelined Mode Parameters
[10]
t
Input Register Synchronous Clock (CLK , CLK , CLK , or
7
10
ICS
0
1
2
CLK ) to Output Register Synchronous Clock (CLK , CLK ,
3
0
1
CLK , or CLK )
2
3
Operating Frequency Parameters
f
Maximum Frequency with Internal Feedback
143
167
100
143
MHz
MHz
MAX1
[7]
(Lesser of 1/t
, 1/(t + t ), or 1/t
)
SCS
S
H
CO
f
Maximum Frequency Data Path in Output Regis-
tered/Latched Mode (Lesser of 1/(t + t ), 1/(t + t ), or
MAX2
WL
WH
S
H
1/t
)
CO
f
f
Maximum Frequency with External Feedback
(Lesser of 1/(t + t ) or 1/(t + t ))
91
80
MHz
MHz
MAX3
CO
S
WL
WH
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
+
125
100
MAX4
CO
t ), 1/t , 1/(t + t ), 1/(t + t ), or 1/t )
IS
ICS
WL
WH
IS
IH
SCS
Reset/Preset Parameters
[7]
t
t
t
t
t
t
Asynchronous Reset Width
8
12
14
ns
ns
ns
ns
ns
ns
RW
[10]
[7]
Asynchronous Reset Recovery Time
10
RR
RO
[10, 11]
Asynchronous Reset to Output
14
14
18
18
[7]
Asynchronous Preset Width
8
12
14
PW
[10]
[7]
Asynchronous Preset Recovery Time
Asynchronous Preset to Output
10
PR
[10, 11]
PO
User Option Parameters
t
t
Low Power Adder
4
2
4
2
ns
ns
LP
Slow Output Slew Rate Adder
SLEW
JTAG Timing Parameters
t
t
t
f
Set-Up time from TDI and TMS to TCK
Hold Time on TDI and TMS
0
0
ns
ns
S JTAG
H JTAG
CO JTAG
JTAG
20
20
Falling Edge of TCK to TDO
20
20
20
20
ns
Maximum JTAG Tap Controller Frequency
MHz
9
PRELIMINARY
CY37064V
Typical I Characteristics
cc
45
40
35
30
25
20
15
10
5
High Speed
Low Power
0
0
20
40
60
80
100
120
140
Frequency (M Hz)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
cc = 3.3V, TA = Room Temperature
10
PRELIMINARY
CY37064V
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
37064V-14
Registered Output with Synchronous Clocking
INPUT
tS
tH
SYNCHRONOUS
CLOCK
tCO
REGISTERED
OUTPUT
tCO2
REGISTERED
OUTPUT
tWH
tWL
SYNCHRONOUS
CLOCK
37064V-15
Registered Output with Product Term Clocking
Input Going Through the Array
INPUT
tSPT
tHPT
PRODUCT TERM
CLOCK
tCOPT
REGISTERED
OUTPUT
tWH
tWL
PRODUCT TERM
CLOCK
37064V-16
11
PRELIMINARY
CY37064V
Switching Waveforms (continued)
Registered Output with Product Term Clocking
Input Coming From Adjacent Buried Register
INPUT
tISPT
tIHPT
PRODUCT TERM
CLOCK
tCO2PT
REGISTERED
OUTPUT
tWH
tWL
PRODUCT TERM
CLOCK
37064V-17
Latched Output
INPUT
tSL
tHL
LATCH ENABLE
tPDL
tCO
LATCHED
OUTPUT
37064V-18
Registered Input
REGISTERED
INPUT
tIS
tIH
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
CLOCK
37064V-19
12
PRELIMINARY
CY37064V
Switching Waveforms (continued)
Clock to Clock
INPUT REGISTER
CLOCK
tICS
tSCS
OUTPUT
REGISTER CLOCK
37064V-20
Latched Input
LATCHED INPUT
tIS
tIH
LATCH ENABLE
tPDL
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
LATCH ENABLE
37064V-21
Latched Input and Output
LATCHED INPUT
tPDLL
LATCHED
OUTPUT
tICOL
tSL
tHL
INPUT LATCH
ENABLE
tICS
OUTPUT LATCH
ENABLE
tWH
tWL
LATCH ENABLE
37064V-22
13
PRELIMINARY
CY37064V
Switching Waveforms (continued)
Asynchronous Reset
tRW
INPUT
tRO
REGISTERED
OUTPUT
tRR
CLOCK
37064V-23
Asynchronous Preset
tPW
INPUT
tPO
REGISTERED
OUTPUT
tPR
CLOCK
37064V-24
OutputEnable/Disable
INPUT
tER
tEA
OUTPUTS
37064V–25
14
PRELIMINARY
CY37064V
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
100-Pin Thin Quad Flatpack
143
CY37064VP100-143AC
CY37064VP84-143JC
CY37064VP44-143AC
CY37064VP44-143JC
CY37064VP100-100AC
CY37064VP84-100JC
CY37064VP44-100AC
CY37064VP44-100JC
CY37064VP100-100AI
CY37064VP84-100JI
CY37064VP44-100AI
CY37064VP44-100JI
CY37064VP44-100YMB
A100
J83
Commercial
Commercial
Industrial
84-Pin Plastic Leaded Chip Carrier
44-Pin Thin Quad Flatpack
A44
J67
44-Pin Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
100
A100
J83
84-Pin Plastic Leaded Chip Carrier
44-Pin Thin Quad Flatpack
A44
J67
44-Pin Plastic Leaded Chip Carrier
100-Pin Thin Quad Flatpack
A100
J83
84-Pin Plastic Leaded Chip Carrier
44-Pin Thin Quad Flatpack
A44
J67
44-Pin Plastic Leaded Chip Carrier
44-Pin Ceramic Leaded Chip Carrier
Y67
Military
In-System Reprogrammable, ISR, UltraLogic, Ultra37000, InSRkit, Warp, and Impulse3 are trademarks of Cypress
Semiconductor Corporation.
Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
Document #: 38−00715–A
15
PRELIMINARY
CY37064V
Package Diagrams
44-Lead Thin Plastic Quad Flat Pack A44
51-85064-B
16
PRELIMINARY
CY37064V
Package Diagrams (continued)
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
44-Lead Plastic Leaded Chip Carrier J67
51-85003-A
17
PRELIMINARY
CY37064V
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
51-85006-A
18
PRELIMINARY
CY37064V
Package Diagrams (continued)
44-Pin Ceramic Leaded Chip Carrier Y67
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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