Delta39K PLL and Clock Tree
.
Table 1. Valid Skew Option Values
Skew Option
Time when data
must be ready
Time when new data
reaches output pin
No EXTERNAL
Feedback
EXTERNAL
Feedback
pll_in
tS
tP
tCO
0, 45, 90, 135, 180, 225, 270, 315
0
Larger
Smaller
Table 2. Valid De-skew Option Values
De-skew Option[1]
effective tS
effective tCO
(clock-to-out time)
(setup time)
gclk0-3
No De-skew
Desired
Clock Tree De-skew Board De-skew
tDS
tCO
tS
tDS
Desired
Desired
DIRECT
CLOCK_TREE
EXTERNAL
Note:
1. Add a ‘prefix to each of the options when instantiating in Verilog.
Figure 3. De-skewed Clock and Adjusted tS and tCO
.
There are two options for de-skewing a clock using the PLL.
Both of these involve the insertion of a delay into the PLL
feedback path, which decreases the effective clock-to-out
time by the delay value but increases the effective set-up time
requirement by the same amount. Please see Figure 3 for a
description of this.
If EXTERNAL is selected as the method of feedback, only
Phase 0 may be selected as the phase adjustment option
value in the LPM instantiation for the on-chip global clock that
drives the off-chip clock used as the external feedback. If
CLOCK_TREE or DIRECT is selected, any of the eight phas-
es may also be selected. The four global clocks, INTCLK[3:0],
may be inverted locally at the macrocell register or I/O register
used in order to create additional phases. The resulting phase
delay would be 180° for clocks that have been generated by
the PLL and have passed through a divider with a binary di-
vide value (1, 2, 4, 8, or 16). The phase delay is the same for
clocks that have been derived directly from one of the
GCLK[3:0] input pins without using the PLL. However, if any
of these global clocks have been generated by the PLL and
pass through a divider with a non-binary divide value (3, 5, or
6), the amount of phase delay will vary based on their
non-50% duty cycles.
The first option is to insert a delay equal to the delay of the
clock tree in the 39K by selecting the feedback path labeled
“CLOCK_TREE” in Figure 1.
The second option is to feedback a PLL-generated off-chip
clock through the GCLK[1] pin to ext_fdbk. This means that
whatever delay that is associated with the connection be-
tween the off-chip clock and GCLK[1] will become included in
the PLL’s feedback path. This delay will directly determine to
what extent gclk0-3 are de-skewed. This path is indicated as
a dashed line and is labeled “EXTERNAL” in Figure 1.
Using the DIRECT feedback path means that an internal
trace directly connects the PLL output to the PLL feedback
input. This configuration should be used when no de-skew is
desired. This path is labeled “DIRECT” in Figure 1.
Clock Multiplication and Division
Designers may use the PLL and Clock Tree to multiply or di-
vide the incoming clock to generate multiple frequencies, to
increase or decrease incoming clock speeds, or to correct the
incoming clock’s duty cycle.
When gclk0-3 have been derived from any of the 7 phase-de-
layed or skewed PLL outputs, selecting CLOCK_TREE or
EXTERNAL as the method of feedback in order to implement
de-skew will cancel part or all of this skew. Therefore, it is not
possible to improve set-up and clock-to-out times simulta-
neously on a single clock.
The clock can be multiplied by a factor of 1, 2, 4 or 8. Each
multiply option selects an element, which is effectively a
counter or divider set to the appropriate value, for use in the
feedback path. The result is a PLL-generated clock that is
either the same speed as or is multiplied up to 8 times faster
than the incoming clock.
Selecting a Phase Adjustment Option
Only one of the three feedback option values may be inserted
into the LPM instantiation. Selecting the EXTERNAL option
will require the use of an off-chip clock, and will constrain the
number of valid values that may be selected for the Multipli-
cation/Division and Phase Adjustment options. To view these
constraints, please see Tables 1, 2 and 4.
The PLL-generated clock may be divided by one of eight fac-
tors after the incoming clock has been multiplied. Division se-
lections are 1, 2, 3, 4, 5, 6, 8, and 16.
Selecting a Multiplication/Division Option
The Voltage Controlled Oscillator (VCO), the core of the
Delta39K PLL is designed to operate within the frequency
range of 100 MHz to 266 MHz. When using the DIRECT or
CLOCK_TREE feedback configurations the pll_in frequency
(GCLK0) and multiply option must be selected to ensure the
VCO is operating within this range. Valid pll_in frequencies for
each multiply option are detailed in Table 3. Note the maxi-
mum input frequency to the PLL is limited to 133MHz. In these
2