CY39050Z484-83MBI [CYPRESS]
Loadable PLD, 15ns, 768-Cell, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484;
| 型号： | CY39050Z484-83MBI |
| 厂家： | 
CYPRESS |
| 描述： | Loadable PLD, 15ns, 768-Cell, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484 输入元件 可编程逻辑 |
| 文件： | 总7页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Delta39K™ PLL and Clock Tree
The Delta39K PLL and the global clock tree provide design-
Introduction
ers with functionality that can be configured to meet various
design requirements. This functionality includes clock phase
adjustment, clock multiplication and division, Spread Aware™
feature, lock detection, off-chip clocking and buffering, and
JTAG support.
The purpose of this application note is to provide information
and instruction in utilizing the functionality of the Delta39K™
Phase-Locked Loop (PLL) and associated clock tree.
Delta39K is a family of high-density Complex Programmable
Logic Devices (CPLDs) containing on-chip components such
as Single-Port RAM, advanced Dual-Port RAM, and a PLL.
The Delta39K PLL can be used in any system requiring clock
frequency or clock phase manipulation.
Clock Phase Adjustment
Designers may use the PLL and clock tree to re-position the
edges of the PLL-generated clock in order to shift perfor-
mance toward either improved set-up time or improved
clock-to-out time. The clock's phase, or the position of its edg-
es relative to the PLL input, may be adjusted in either of two
ways: Skewing the clock moves its phase backward on the
time axis, while de-skewing the clock moves its phase fore-
word on the time axis.
For Delta39K, programming is defined as the loading of a
user’s design into the on-chip FLASH device internal to the
Delta39K package. Configuration, on the other hand, is the
loading of a user’s design into the volatile Delta39K die.
Overview of PLL & Clock Tree
Within each 3.3V/2.5V Delta39K device, a single on-chip PLL
resides as part of a larger clocking scheme. Four local dedi-
cated clock input pins, referred to here as GCLK[3:0], provide
direct inputs to this clock tree. GCLK[0] and GCLK[1] may
also be used as an input port and external feedback port,
respectively to the PLL. Within the clock tree are four global
clocks, referred to here as INTCLK[3:0], which are accessible
to any macrocell, I/O cell, or memory block. GCLK[3:0] and
the outputs of the PLL feed a set of multiplexors which source
INTCLK[3:0]. Figure 1 contains a block diagram of the clock
tree and PLL.
There are eight options for skewing the incoming clock. The
clock can be skewed so that the phase is delayed 0°, 45°, 90°,
135°, 180°, 225°, 270°, or 315°. A 45° phase shift increment
is equal to a delay of 1/8th of the clock's period length. Note
that adding delay to the incoming clock has the effect of in-
creasing effective clock-to-out time while decreasing the ef-
fective setup time requirements. Refer to Figure 2 for an ex-
ample.
Time when data
Time when new data
must be ready
reaches output pin
EXTERNAL
Off-chip clock
pll_in
tP
tS
tCO
CLOCK_TREE
Delay
Any I/O Cell
Any Macrocell
Any Memory
4
4
4
DIRECT
Smaller
Larger
effective tS
effective tCO
Feedback
ext_fdbk
[1]
(clock to out time)
(setup time)
I
x
(1,2,4,8)
N
T
pll_in
gclk0
Source
Divide
Divide
Divide
Divide
tSK
tSK
tCO
C
L
gclk0-3
8
8
0
[0]
2
K
45
90
[3:0]
gclk1
gclk2
gclk3
tS
135
180
225
270
315
Lock
4
8
Figure 2. Skewed Clock and Adjusted tS and tCO
.
G
C
8
8
L
K
[0:3]
4
lock_detect
Figure 1. Delta39K Phase Locked Loop and Clock Tree.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 6, 2001
Delta39K PLL and Clock Tree
.
Table 1. Valid Skew Option Values
Skew Option
Time when data
must be ready
Time when new data
reaches output pin
No EXTERNAL
Feedback
EXTERNAL
Feedback
pll_in
tS
tP
tCO
0, 45, 90, 135, 180, 225, 270, 315
0
Larger
Smaller
Table 2. Valid De-skew Option Values
De-skew Option[1]
effective tS
effective tCO
(clock-to-out time)
(setup time)
gclk0-3
No De-skew
Desired
Clock Tree De-skew Board De-skew
tDS
tS
tDS
Desired
Desired
DIRECT
CLOCK_TREE
EXTERNAL
Note:
1. Add a ‘prefix to each of the options when instantiating in Verilog.
Figure 3. De-skewed Clock and Adjusted tS and tCO
.
There are two options for de-skewing a clock using the PLL.
Both of these involve the insertion of a delay into the PLL
feedback path, which decreases the effective clock-to-out
time by the delay value but increases the effective set-up time
requirement by the same amount. Please see Figure 3 for a
description of this.
If EXTERNAL is selected as the method of feedback, only
Phase 0 may be selected as the phase adjustment option
value in the LPM instantiation for the on-chip global clock that
drives the off-chip clock used as the external feedback. If
CLOCK_TREE or DIRECT is selected, any of the eight phas-
es may also be selected. The four global clocks, INTCLK[3:0],
may be inverted locally at the macrocell register or I/O register
used in order to create additional phases. The resulting phase
delay would be 180° for clocks that have been generated by
the PLL and have passed through a divider with a binary di-
vide value (1, 2, 4, 8, or 16). The phase delay is the same for
clocks that have been derived directly from one of the
GCLK[3:0] input pins without using the PLL. However, if any
of these global clocks have been generated by the PLL and
pass through a divider with a non-binary divide value (3, 5, or
6), the amount of phase delay will vary based on their
non-50% duty cycles.
The first option is to insert a delay equal to the delay of the
clock tree in the 39K by selecting the feedback path labeled
“CLOCK_TREE” in Figure 1.
The second option is to feedback a PLL-generated off-chip
clock through the GCLK[1] pin to ext_fdbk. This means that
whatever delay that is associated with the connection be-
tween the off-chip clock and GCLK[1] will become included in
the PLL’s feedback path. This delay will directly determine to
what extent gclk0-3 are de-skewed. This path is indicated as
a dashed line and is labeled “EXTERNAL” in Figure 1.
Using the DIRECT feedback path means that an internal
trace directly connects the PLL output to the PLL feedback
input. This configuration should be used when no de-skew is
desired. This path is labeled “DIRECT” in Figure 1.
Clock Multiplication and Division
Designers may use the PLL and Clock Tree to multiply or di-
vide the incoming clock to generate multiple frequencies, to
increase or decrease incoming clock speeds, or to correct the
incoming clock’s duty cycle.
When gclk0-3 have been derived from any of the 7 phase-de-
layed or skewed PLL outputs, selecting CLOCK_TREE or
EXTERNAL as the method of feedback in order to implement
de-skew will cancel part or all of this skew. Therefore, it is not
possible to improve set-up and clock-to-out times simulta-
neously on a single clock.
The clock can be multiplied by a factor of 1, 2, 4 or 8. Each
multiply option selects an element, which is effectively a
counter or divider set to the appropriate value, for use in the
feedback path. The result is a PLL-generated clock that is
either the same speed as or is multiplied up to 8 times faster
than the incoming clock.
Selecting a Phase Adjustment Option
Only one of the three feedback option values may be inserted
into the LPM instantiation. Selecting the EXTERNAL option
will require the use of an off-chip clock, and will constrain the
number of valid values that may be selected for the Multipli-
cation/Division and Phase Adjustment options. To view these
constraints, please see Tables 1, 2 and 4.
The PLL-generated clock may be divided by one of eight fac-
tors after the incoming clock has been multiplied. Division se-
lections are 1, 2, 3, 4, 5, 6, 8, and 16.
Selecting a Multiplication/Division Option
The Voltage Controlled Oscillator (VCO), the core of the
Delta39K PLL is designed to operate within the frequency
range of 100 MHz to 266 MHz. When using the DIRECT or
CLOCK_TREE feedback configurations the pll_in frequency
(GCLK0) and multiply option must be selected to ensure the
VCO is operating within this range. Valid pll_in frequencies for
each multiply option are detailed in Table 3. Note the maxi-
mum input frequency to the PLL is limited to 133MHz. In these
2
Delta39K PLL and Clock Tree
configurations any one of the eight division settings may be
individually selected for gclk[0-3].
Table 4. Valid Multiply & Divide Options: EXTERNAL
Selected
When the EXTERNAL feedback option is selected only mul-
tiplication by a factor of one and division by a factor of one
may be selected for the off-chip clock that is being used in the
feedback path. The other three PLL generated clocks may
use any of the eight division settings. Valid pll_in frequencies,
multiply and divide options for this configuration are detailed
in table 4.
Valid Multiply
Option
Valid Divide Option
pll_in
Freq
VCO
Freq[3]
(MHz) Value (MHz)
gclk0-3
Freq
Off-chip
Freq
Value
(MHz)
(MHz)
50-133
1
100-266
For Feedback Path
100-266 50-133
Note that if an on-chip clock is sent off-chip, it will be further
divided by two on top of any divide settings chosen
1
Multiplying an input frequency allows one to use slower fre-
quencies throughout the board (externally) and use faster fre-
quencies internally. (Assuming they are not needed other
places so as to make this less advantageous). This allows for
less power consumption, less electromagnetic interference
(EMI), and less undesirable high speed signal integrity is-
sues.
For Non-Feedback Path
1-6,8,16 6.25-266 3.125-133
Spread Aware™ Feature
The PLLs incorporated in all Delta39K CPLDs are Spread
Aware. This feature refers to the ability of the PLL to track a
spread-spectrum input clock such that its spread is seen on
the output clock. Spread-spectrum is a method of 'spreading'
or modulating a fundamental or original frequency in a con-
trolled, oscillatory manner, such that the electromagnetic en-
ergy broadcast at any given component in the frequency
spectrum is below the maximum value imposed by FCC reg-
ulations. Spread Aware does not mean that the PLL is capa-
ble of generating a spread-spectrum output from a non
spread-spectrum input.
Also, designs requiring a given throughput or bandwidth run-
ning at a lower frequency and wider bus-width, can be in-
creased to a higher frequency, while the bus-width can be
reduced to a narrower width. This way, less logic resources
(real estate) can be used on the Cypress CPLD, while main-
taining the same throughput.
Table 3. Valid Multiply & Divide Options: DIRECT or
CLOCK_TREE Selected
Valid Multiply
Option
Valid Divide Option
gclk0-3 Off-chip
When configured with a x1, x2 or x4 multiply option the
Delta39K PLL is Spread Aware whereas the x8 multiply op-
tion does not support the Spread Aware feature.
pll_in
Freq
VCO
Freq
(MHz)
Freq
Freq[2]
(MHz)
Designers may choose to use the spread aware Delta39K
PLL with a spread spectrum input clock. Down spread, up
spread, or some form of middle spread such as center spread
may be used on the incoming clock. However, the total
amount of spread in either or both directions should be limited
to 0.6% of the fundamental frequency. The modulation fre-
quency of the spread should be 50 kHz or less in order to
ensure that the PLL will meet the performance specified in the
data sheet and maintain its intended 1 MHz loop bandwidth.
Value
(MHz)
Value
(MHz)
N/A DC-12.5
N/A
N/A
DC-12.5 DC-6.25
8
4
2
1
12.5- 33 100-266 1-6,8,16 6.25-266 3.125-133
25-66 100-266 1-6,8,16 6.25-266 3.125-133
50-133 100-266 1-6,8,16 6.25-266 3.125-133
100-133 100-133 1-6,8,16 6.25-133 3.125-66
Lock Detection
A finite amount of time is required from the moment that the
incoming clock signal is placed on the GCLK[0] pin, and thus
drives the source of the PLL, to the time that the PLL actually
achieves steady-state operation, or lock. Designs that contain
logic that will not operate properly until a valid clock signal is
present at the output of the PLL, are dependent upon the PLL
first achieving lock. Designs such as these may require a sig-
nal to indicate when the PLL has reached lock. The PLL can
be configured to generate a lock detect signal at a dedicated
I/O pin. This pin is fed by a multiplexor that can be configured
to select either a general-purpose I/O function or a lock de-
tection indicator function for this pin.
N/A 133-fMAX
N/A
N/A
133-fMAX 66-fMAX
Notes:
2. An off-chip clock is the output of a toggle flip-flop, which acts as a /2.
3. When an off-chip clock is fed back to ext_fdbk, the toggle flip-flop is effectively placed into the feedback path, resultingin an implicit x2 on top of the x1 multiplication
setting.
3
Delta39K PLL and Clock Tree
module off_chip_example(clkin, offchipclock);
JTAG Support
input clkin;
The Delta39K PLL supports the JTAG instruction INTEST.
When the Delta39K device is in JTAG mode and is executing
the instruction INTEST, the clock driving the TCK pin is mul-
tiplexed onto INTCLK[3:0]. This allows the internal logic to be
controlled by the JTAG clock, TCK, instead of the system
clock, and enables the user to verify proper operation of his
or her design in a given device. For more information about
JTAG programming, please refer to the application note titled
'Using IEEE 1149.1 Boundary Scan (JTAG) With Cypress
Ultra37000 CPLDs,' which can be downloaded from ht-
tp://www.cypress.com/pld/pldappnotes.html.
output offchipclock;
wire plloutclock;
reg offchipclock;
assign plloutclock = clkin;
always@ (posedge plloutclock)
Off-Chip Clocking and Buffering
begin
The Delta39K global clocks, INTCLK[3:0], may be driven
off-chip by clocking a macrocell or I/O register configured as
a toggle flip-flop (TFF). This way, upon every rising edge of
the INTCLK clock used, the register output level will toggle
from its current state (HIGH or LOW) to the opposite state
(LOW or HIGH). Since, for every two rising edges of the IN-
TCLK clock used a single rising edge at the register output is
generated, a periodic signal that is half the frequency of the
register's clock will result. In order to illustrate how to imple-
ment off-chip clocks in source code, sample code in both
VHDL and Verilog is listed below:
if (plloutclock)
offchipclock <= ~( offchipclock);
end
endmodule
Listing 1b: Verilog Example of Off-chip Clock
Multiple identical output clocks can be buffered from a single
global clock by driving multiple outputs or 'copies' to the same
output described, above.
Overview of Software Support
The Delta39K PLL can be configured in either VHDL or Ver-
ilog code using Warp Enterprise™, Warp Professional™, or
Warp® Release 6.0 or later software. The methodology for
implementing this configuration is via a component, module,
or LPM instantiation. Since Delta39K contains a single PLL,
each design project should contain only one instantiation of
the PLL.
library ieee;
use ieee.std_logic_1164.all;
entity off_chip_example is
port (
clkin:
in std_logic;
Selecting a Target Device
offchipclk: buffer std_logic
When creating a new project or editing a current project to
target a device, only 2.5V/3.3V devices in the Delta39K family
should be selected if PLL functionality is desired. These de-
vices are indicated by a 'V' in the package name, while low
voltage device selections include a “Z” in the package name
and do not offer PLL functionality. An example of such a de-
vice selection is “CY39100V676-125MBC”.
);
end off_chip_example;
architecture off_chip_arch of off_chip_example is
signal shifted_clock: std_logic;
begin
Component / Module or LPM Instantiation
The PLL configuration may be implemented by instantiating
the PLL component “cy_c39kpll.” For Warp to recognize
these instantiations, the user must place the appropriate
VHDL 'library' and 'use' statements or Verilog ‘include’ state-
ments in the source code file where the PLL instantiation re-
sides. For an example of the PLL instantiation in source code,
please see Listing 2a and 2b. In these samples, 'clkin' is mul-
tiplied by 4, while clock signals 'm1p0clock', 'm2p45clock',
'm4p0clock', and 'm4p90clock' are internal clocks accessible
to every register on the selected Delta39K device. Each of the
four internal clocks is configured with different divide and
phase shift selections. 'm1p0clock' is also configured to tog-
gle 'off chip clock' as an off-chip clock. The method of feed-
back selected is 'DIRECT'.
plloutclock<=clkin;
p1: process (plloutclock)
begin
if (plloutclock'event and plloutclock= '1') then
offchipclock <= not(offchipclock);
end if;
end process;
end off_chip_arch;
library ieee;
Listing 1a: VHDL Example of Off-chip Clock
use ieee.std_logic_1164.all;
4
Delta39K PLL and Clock Tree
end pll_arch;
library cypress;
Listing 2a: VHDL Sample of PLL Instantiation
use cypress.lpmpkg.all;
use cypress.rtlpkg.all;
`include "lpm.v"
`include "rtl.v"
entity pll_example is
port (
`define DIRECT 0
clkin:
instd_logic;
module pll_example(clkin, offchipclock);
offchipclock: bufferstd_logic
);
input clkin;
end pll_example;
output offchipclock;
architecture pll_arch of pll_example is
signal m1p0clock: std_logic;
begin
reg m1p0clock;
reg offchipclock;
defparam U0.feedback = `DIRECT; // optional
U0: cy_c39kpll
generic map(
defparam U0.multiply
= 4;// optional
defparam U0.gclk0_phase = 0;// optional
defparam U0.gclk0_divide = 4;// optional
defparam U0.gclk1_phase = 0;// optional
defparam U0.gclk1_divide = 1;// optional
defparam U0.gclk2_phase = 0;// optional
defparam U0.gclk2_divide = 1;// optional
defparam U0.gclk3_phase = 0;// optional
defparam U0.gclk3_divide = 1;// optional
cy_c39kpll U0(
feedback
multiply
=> DIRECT,-- optional
=> 4,-- optional
gclk0_phase => 0,-- optional
gclk0_divide => 4,-- optional
gclk1_phase => 0,-- optional
gclk1_divide => 1,-- optional
gclk2_phase => 0,-- optional
gclk2_divide => 1,-- optional
gclk3_phase => 0,-- optional
gclk3_divide => 1 -- optional
)
.pll_in( clkin ),
//.ext_fdbk(0),// optional
//.lock_detect(),// optional
port map(
.gclk0 (m1p0clock), // optional
.gclk1 (),// optional
pll_in
=> clkin,
ext_fdbk
=> zero,-- optional
.gclk2 (),// optional
lock_detect => open,-- optional
.gclk3 ());
// optional
gclk0
gclk1
gclk2
gclk3
);
=> m1p0clock,-- optional
=> open,-- optional
always @(posedge m1p0clock)
=> open, -- optional
=> open -- optional
begin
offchipclock = ~(offchipclock);
end
endmodule
p0: process (m1p0clock)
begin
Listing 2b: Verilog Sample of PLL Instantiation
The PLL instantiation can be pasted into the source code by
selecting “CY 39kPLL” from the “Template” pull-down on the
toolbar. The text of the PLL instantiation will be automatically
inserted directly at the last cursor position in the source code
displayed in the editor window. There will be default values
listed for some of the instantiation items, but those that are
either blank or require modification must be typed in manually
if (m1p0clock'event and m1p0clock = '1') then
offchipclock <= not(offchipclock);
end if;
end process;
5
Delta39K PLL and Clock Tree
by the user. For a brief description of each port and LPM
property, please see Figure 5 and Table 6.
contained within the PLL and Clock Tree. Operating outside
of these ranges may result in poor performance, non-opera-
bility, or damage to the board or related devices.
Report File Information
When the 'Detailed Report File' option has been selected
from the 'Messaging' tab in 'the 'Compiler Options' dialogue
box, all PLL and clock tree configuration information is printed
into the Warp report file after compilation. Specifically, this
information can be found in the 'DESIGN EQUATIONS' sec-
tion of the report file under 'Clock/PLL listing'. Please see
Figure 4 for a snapshot of this text. To select the appropriate
compiler setting, select 'Compiler Options' from the 'Project'
dropdown menu in Warp.
Table 5. Valid Operating Ranges for Clock Tree and PLL
Operating Range
Item
(MHz)
DC-fMAX
DC-fMAX
DC-fMAX/2
12.5-133
50-133
GCLK[3:0]
INTCLK[3:0]
Off-chip clock
pll_in
ext_fdbk
gclk0-gclk3
VCO
6.25-266
100-266
Architecture Explorer
The PLL along with the clock tree is shown as a green rect-
angular box in the upper right hand corner of Delta39K devic-
es in the Architecture Explorer. Right-clicking over this box will
open a window from which “Properties” can be selected. Do-
ing so will display the same information that is contained in
the report file screen shot, mentioned above. Please see Fig-
ure 5 for a screenshot of the PLL / Clock Tree in the Architec-
ture Explorer.
Figure 4. Screenshot of PLL in Architecture Explorer.
Using the zoom feature on this box will reveal the four clock
input connections, which are GCLK[3:0] and the four clock
output connections, which are INTCLK[3:0]. Zooming in more
closely will reveal text labels at each of these connections
identifying the input and output clock signal names assigned
in each case.
Valid Frequency Ranges
In order to ensure that the PLL and Clock Tree operate cor-
rectly and perform within the data sheet's specifications, cer-
tain ranges of operating frequency have been determined for
the inputs, outputs, and Voltage Controlled Oscillator (VCO)
6
Delta39K PLL and Clock Tree
4
gclk0 - gclk3
lock_detect
pll_in
CY_C39kPLL
ext_fdbk
LPM PROPERTIES
feedback
multiply
gclk0_phase
gclk1_phase
gclk2_phase
gclk3_phase
gclk0_divide
gclk1_divide
gclk2_divide
gclk3_divide
Figure 5. CY_C39kPLL LPM Module Ports and Proper-
ties.
Table 6. Description of PLL Instantiation Port and Properties
Name
pll_in
Type
In
Usage
Description
Required
Source reference input to PLL
External feedback input to PLL
ext_fdbk
lock_detect
gclk0
In
Out
Out
Out
Out
Out
In
Output to dedicated pin indicating lock detection
PLL output clock driving Intclk[0]
at
least
one of
these
is
gclk1
PLL output clock driving Intclk[1]
gclk2
PLL output clock driving Intclk[2]
Required
gclk3
PLL output clock driving Intclk[3]
feedback
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Property to select de-skewing method
multiply
In
Property to select multiplication factor
gclk0_phase
gclk1_phase
gclk2_phase
gclk3_phase
gclk0_divide
gclk1_divide
gclk2_divide
gclk3_divide
In
Property to select incremental delay, based on VCO frequency for gclk0
Property to select incremental delay, based on VCO frequency for gclk1
Property to select incremental delay, based on VCO frequency for gclk2
Property to select incremental delay, based on VCO frequency for gclk3
Property to select division factor for gclk0
In
In
In
In
In
Property to select division factor for gclk1
In
Property to select division factor for gclk2
In
Property to select division factor for gclk3
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical Components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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