CY39100Z256-125BBI_技术文档

Delta39K™ ISR™

CPLD Family

PRELIMINARY

CPLDs at FPGA Densities™

•Multiple I/O standards supported

Features

— LVCMOS, LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II),

HSTL (I-IV), and GTL+

•High density

— 15K to 350K usable gates

— 256 to 5376 macrocells

— 92 to 520 maximum I/O pins

•Compatible with NOBL™, ZBT™, and QDR™ SRAMs

•Programmable slew rate control on each I/O pin

•User-Programmable Bus Hold capability on each I/O pin

•Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)

•Compact PCI hot swap compatible

•Multiple package/pinout offering across all densities

— 144 to 676 pins in PQFP, BGA and FBGA packages

— Same pinout for 3.3V/2.5V and 1.8V devices

— Simplifies design migration across density

— Self-Boot™ solution in BGA and FBGA packages

•In-System Reprogrammable™ (ISR™)

— 12 Dedicated Inputs including 4 clock pins, 4 global

control signal pins and 4 JTAG interface pins for

reconfigurability

•Embedded Memory

— 40K to 840K bits embedded SRAM

• 32K to 672K bits of (single port) Cluster memory

• 8K to 168K bits of (dual port) Channel memory

•High speed - 250 MHz in-system operation

•AnyVolt™ interface

JTAG-compliant on-board programming

—

— 3.3V, 2.5V and 1.8V V versions available

CC

— Design changes don’t cause pinout changes

•IEEE1149.1 JTAG boundary scan

— 3.3V, 2.5V and 1.8V I/O capability on all versions

• Low Power Operation

0.18- m 6-layer metal SRAM-based logic process

—

µ

Development Software

— Full-CMOS implementation of product term array

Standby current as low as 100 A at 1.8V V

—

µ

•Warp™

CC

•Simple timing model

— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing.

— No penalty for using full 16 product terms / macrocell

— No delay for single product term steering or sharing

•Flexible clocking

— Active-HDL FSM graphical finite state machine editor

— Active-HDL SIM post-synthesis timing simulator

— Architecture Explorer for detailed design analysis

— Static Timing Analyzer for critical path analysis

— Available on Windows 95, 98 & NT for $99

— 4 synchronous clocks per device

— 1 spread-aware PLL drives all 4 clock networks

— Locally generated Product Term clock

— Clock polarity control at each register

•Carry chain logic for fast efficient arithmetic operations

— Supports all Cypress Programmable Logic Products

Delta39K™ ISR CPLD Family Members

[1]

Standby I

CC

Cluster

Channel

f

Speed-t

PD

T =25 C

°

MAX2

A

Typical

Gates

memory memory Maximum

Pin-to-Pin

(ns)

Device

39K15

Macrocells

256

(Kbits)

I/O Pins

(MHz)

250

222

200

181

167

154

3.3/2.5V

1.8V

8K–24K

16K–48K

32

8

134

6.5

7.0

7.5

8.0

8.5

9.0

10 mA

100 µA

200 µA

300 µA

600 µA

1000 µA

1250 µA

1500 µA

2100 µA

39K30

512

64

16

176

39K50

23K–72K

768

96

24

218

39K100

39K165

39K200

39K250

39K350

46K–144K

77K–241K

92K–288K

115K–361K

161K–505K

1536

2560

3072

3840

5376

192

320

384

480

672

48

302

80

386

96

428

120

168

470

520

Note:

1. Standby I_CCvalues are with PLL not utilized, no output load and stable inputs

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

August 9, 2000

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Delta39K Speed Bins^[2]

Device

39K15

250

222

200

181

167

154

125

X

83

X

39K30

X

39K50

X

39K100

39K165

39K200

39K250

39K350

X

Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs

[3]

Self-Boot Solution

256-FBGA 388-BGA

208-EQFP 144-FBGA 256-FBGA 484-FBGA 676-FBGA

676-FBGA

27x27 mm

1.0-mm

484-FBGA

23x23 mm

1.0-mm pitch

17x17 mm

1.0-mm

pitch

35x35 mm

1.27-mm

pitch

28X28 mm

0.5-mm

pitch

13x13 mm

1.0-mm

pitch

17x17 mm

1.0-mm

pitch

23x23 mm

1.0-mm

pitch

27x27 mm

1.0-mm

pitch

Device

39K15

pitch

134

136

92

134

176

180

134

176

39K30

39K50

218

294

218

39K100

39K165

39K200

39K250

302

362

368

302

386

428

470

520

470

520

39K350

Notes:

2. Speed bins shown here are for Commercial operating range. Please refer to Delta39K Ordering Information on page 36 for Industrial range speed bins.

3. Self-Boot Solution integrates the boot PROM with Delta39K die inside the same package.

2

Delta39K™ ISR™

CPLD Family

PRELIMINARY

PLL & Clock MUX

GCLK[3:0]

GCTL[3:0]

4

I/O Bank 7

I/O Bank 6

G CLK[3:0]

4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 0

LB 1

LB 7

LB 6

LB 5

LB 4

LB 0

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 1

LB 2

LB 3

Channel

R AM

C hannel

R AM

C hannel

RA M

Channel

R AM

PIM

LB 2

LB 3

PIM

LB 5

LB 4

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

GCLK[3:0]

4

LB

0

1

2

3

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB

7

6

5

4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

Channel

R AM

Channel

R AM

C hannel

R AM

C hannel

RA M

PIM

LB 5

LB 4

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

G CLK[3:0]

4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

LB 0

LB 1

LB 2

LB 3

LB 7

LB 6

LB 5

LB 4

Channel

R AM

Channel

R AM

C hannel

RA M

C hannel

R AM

PIM

LB 5

LB 4

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

I/O Bank 2

I/O Bank 3

Figure 1. Delta39K100 Block Diagram (3 Rows x 4 Columns) with I/O Bank Structure

3

Delta39K™ ISR™

CPLD Family

PRELIMINARY

The Delta39KZ devices accept 1.8V on the V

directly. With Delta39K’s AnyVolt technology, the I/O pins can

supply pins

General Description

CC

The Delta39K family, based on a 0.18µ, 6-layer metal CMOS

logic process, offers a wide range of high-density solutions at

unparalleled system performance. The Delta39K family is de-

signed to combine the high speed, predictable timing, and

ease of use of CPLDs with the high densities and low power

of FPGAs. With devices ranging from 15,000 to 350,000 us-

able gates, the family features devices ten times the size of

previously available CPLDs. Even at these large densities, the

Delta39K family is fast enough to implement a fully synthesiz-

able 64-bit, 66-MHz PCI core.

be connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devices

are 3.3V tolerant regardless of V

or V settings

CCIO

CC

Device

39KV

V

CCIO

CC

[4]

3.3V or 2.5V

1.8V

3.3V or 2.5V or 1.8V or 1.5V

39KZ

Note:

4. For HSTL only.

Global Routing Description

The architecture is based on Logic Block Clusters (LBC) that

are connected by Horizontal and Vertical (H&V) routing chan-

nels. Each LBC features eight individual Logic Blocks (LB) and

two cluster memory blocks. Adjacent to each LBC is a channel

memory block, which can be accessed directly from the I/O

pins. Both types of memory blocks are highly configurable and

can be cascaded in width and depth. See Figure 1 for a block

diagram of the Delta39K architecture.

The routing architecture of the Delta39K is made up of hori-

zontal and vertical (H&V) routing channels. These routing

channels allow signals from each of the Delta39K architectural

components to communicate with one another. In addition to

the horizontal and vertical routing channels that interconnect

the I/O banks, channel memory blocks, and logic block clus-

ters, each LBC contains a PIM, which is used to route signals

among the logic blocks and the cluster memory blocks.

All the members of the Delta39K family maintain Cypress’s

highly regarded In-System Reprogrammability (ISR) feature,

which simplifies both design and manufacturing flows, thereby

reducing costs. The ISR feature provides the ability to recon-

figure the devices without having design changes cause pinout

or timing changes in most cases. The Cypress ISR function is

implemented through a JTAG-compliant serial interface. Data

is shifted in and out through the TDI and TDO pins respectively.

Superior routability, simple timing, and the ISR allows users to

change existing logic designs while simultaneously fixing pi-

nout assignments and maintaining system performance.

Figure 2 is a block diagram of the routing channels that inter-

face within the Delta39K architecture. The LBC is exactly the

same for every member of the Delta39K CPLD family.

Logic Block Cluster (LBC)

The Delta39K architecture consists of several logic block clus-

ters (LBCs), each of which have 8 Logic Blocks (LB) and 2

cluster memory blocks connected via a Programmable Inter-

connect Matrix (PIM™) as shown in Figure 3. Each cluster

memory block consists of 8-Kbit single-port RAM, which is

configurable as synchronous or asynchronous. The cluster

memory blocks can be cascaded with other cluster memory

blocks within the same LBC as well as other LBCs to imple-

ment larger memory functions. If a cluster memory block is not

specifically utilized by the designer, Cypress’s Warp software

can automatically use it to implement large blocks of logic.

The entire family features JTAG for ISR and boundary scan,

and is compatible with the PCI Local Bus specification, meet-

ing the electrical and timing requirements. The Delta39K fam-

ily also features user programmable bus-hold and slew rate

control capabilities on each I/O pin.

AnyVolt Interface

All LBCs interface with each other via horizontal and vertical

routing channels.

All Delta39KV devices feature an on-chip regulator, which ac-

cepts 3.3V or 2.5V on the V supply pins and steps it down

CC

to 1.8V internally, the voltage level at which the core operates.

I/O Block

LB

72

64

Cluster

PIM

Channel memory

outputs drive

dedicated tracks in the

horizontal and vertical

routing channels

Channel

Memory

Block

Cluster

Memory

Block

Cluster

Memory

Block

72

64

H-to-V

PIM

V-to-H

PIM

Pin inputs from the I/O cells

drive dedicated tracks in the

horizontal and vertical routing

channels

Figure 2. Delta39K Routing Interface

4

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Clock Inputs

GCLK[3:0]

4

Logic

Block

0

Logic

Block

7

36

16

36

16

Logic

Block

1

Logic

Block

6

36

16

36

16

Logic

Block

2

Logic

Block

5

36

16

36

16

PIM

Logic

Block

3

Logic

Block

4

36

16

36

16

Cluster

Memory

0

Cluster

Memory

1

25

8

25

8

CC = Carry Chain

64 Inputs From

Vertical Routing

Channel

64 Inputs From

Horizontal Routing

Channel

144 Outputs to

Horizontal and Vertical

cluster-to-channel PIMs

Figure 3. Delta39K Logic Block Cluster Diagram

Logic Block (LB)

vides two important capabilities without affecting performance:

product term steering and product term sharing.

The logic block is the basic building block of the Delta39K ar-

chitecture. It consists of a product term array, an intelligent

product-term allocator, and 16 macrocells.

Product Term Steering

Product term steering is the process of assigning product

terms to macrocells as needed. For example, if one macrocell

requires ten product terms while another needs just three, the

product term allocator will “steer” ten product terms to one

macrocell and three to the other. On Delta39K devices, prod-

uct terms are steered on an individual basis. Any number be-

tween 1and 16 product terms can be steered to any macrocell.

Product Term Array

Each logic block features a 72 x 83 programmable product

term array. This array accepts 36 inputs from the PIM. These

inputs originate from device pins and macrocell feedbacks as

well as cluster memory and channel memory feedbacks. Ac-

tive LOW and active HIGH versions of each of these inputs are

generated to create the full 72-input field. The 83 product

terms in the array can be created from any of the 72 inputs.

Product Term Sharing

Product term sharing is the process of using the same product

term among multiple macrocells. For example, if more than

one function has one or more product terms in its equation that

are common to other functions, those product terms are only

programmed once. The Delta39K product term allocator al-

lows sharing across groups of four macrocells in a variable

fashion. The software automatically takes advantage of this

capability so that the user does not have to intervene.

Of the 83 product terms, 80 are for general-purpose use for the

16 macrocells in the logic block. Two of the remaining three

product terms in the logic block are used as asynchronous set

and asynchronous reset product terms. The final product term

is the Product Term clock (PTCLK) and is shared by all 16

macrocells within a logic block.

Product Term Allocator

Through the product term allocator, Warp software automati-

cally distributes the 80 product terms as needed among the 16

macrocells in the logic block. The product term allocator pro-

Note that neither product term sharing nor product term steer-

ing have any effect on the speed of the product. All worst-case

steering and sharing configurations have been incorporated in

the timing specifications for the Delta39K devices.

.

5

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Macrocell

which drives through the circuit quickly. Figure 4 shows that the

carry chain logic within the macrocell consists of two product

terms (CPT0 and CPT1) from the PTA and an input carry-in for

carry logic. The inputs to the carry chain mux are connected

directly to the product terms in the PTA. The output of the carry

chain mux generates the carry-out for the next macrocell in the

logic block as well as the local carry input that is connected to

an input of the XOR input mux. Carry-in and a configuration bit

are inputs to an AND gate. This AND gate provides a method

of segmenting the carry chain in any macrocell in the logic

block.

Within each logic block there are 16 macrocells. Each

macrocell accepts up to 16 product terms which can be output

in either registered or combinatorial mode. Figure 4 displays

the block diagram of the macrocell. The register can be asyn-

chronously preset or asynchronously reset at the macrocell

level with the separate preset and reset product terms. Each

of these product terms features programmable polarity. This

allows the registers to be preset or reset based on an AND

expression or an OR expression.

An XOR gate in the Delta39K macrocell allows for many differ-

ent types of equations to be realized. It can be used as a po-

larity mux to implement the true or complement form of an

equation in the product term array or as a toggle to turn the D

flip-flop into a T flip-flop. The carry-chain input mux allows ad-

ditional flexibility for the implementation of different types of

logic. The macrocell can utilize the carry chain logic to imple-

ment adders, subtractors, magnitude comparators, parity tree,

or even generic XOR logic. The output of the macrocell is ei-

ther registered or combinatorial.

Macrocell Clocks

Clocking of the register is highly flexible. Four global synchro-

nous clocks (GCLK[3:0]) and a Product Term (PTCLK) clock

are available at each macrocell register. Furthermore, a clock

polarity mux within each macrocell allows the register to be

clocked on the rising or the falling edge (see macrocell dia-

gram in Figure 4).

PRESET/RESET Configurations

The macrocell register can be asynchronously preset and re-

set using the PRESET and RESET mux. Both signals are ac-

tive high and can be controlled by either of two Preset/Reset

product terms (PRC[1:0] in Figure 4) or GND. In situations

where the PRESET and RESET are active at the same time,

RESET takes priority over PRESET.

Carry Chain Logic

The Delta39K macrocell features carry chain logic which is

used for fast and efficient implementation of arithmetic opera-

tions. The carry logic connects macrocells in up to 4 logic

blocks for a total of 64 macrocells. Effective data path opera-

tions are implemented through the use of carry-in arithmetic,

Carry In

(from macrocell n-1)

PRESET

Mux

0

1

C

XOR Input

3

Carry Chain

Mux

C

CPT0

CPT1

Output Mux

C

2

To PIM

C

D ^PSET

C

Q

FROM PTM

Up To 16 PTs

Clock

Clock Mux

Polarity

Mux

Q

RES

GCLK[3:0]

PTCLK

3

C

0

1

Carry Out

(to macrocell n+1)

3

C

RESET

Mux

Figure 4. Delta39K Macrocell

6

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Embedded Memory

Cluster Memory Initialization

Each member of the Delta39K family contains two types of

embedded memory blocks. The channel memory block is

placed at the intersection of horizontal and vertical routing

channels. Each channel memory block is 4096 bits in size and

can be configured as asynchronous or synchronous Dual Port

RAM, or synchronous FIFO. The memory organization is con-

figurable as 4Kx1, 2Kx2, 1Kx4 and 512x8. The second type of

memory block is located within each LBC and is referred to as

a cluster memory block. Each LBC contains two cluster mem-

ory blocks that are 8192 bits in size. Similar to the channel

memory blocks, the cluster memory blocks can be configured

as 8Kx1, 4Kx2, 2Kx4 and 1Kx8 and can be configured as ei-

ther asynchronous or synchronous single-port RAM.

The cluster memory powers up in an undefined state, but is set

to a user-defined known state during configuration. To facilitate

the use of look-up-table (LUT) logic and ROM applications, the

cluster memory blocks can be initialized with a given set of

data when the device is configured at power up. For LUT and

ROM applications, the user cannot write to memory blocks.

Channel Memory

The Delta39K architecture includes an embedded memory

block at each crossing point of horizontal and vertical routing

channels. The channel memory is a 4096-bit embedded mem-

ory block that can be configured as Asynchronous Dual-Port

memory, Synchronous Dual-Port memory, or Synchronous

FIFO memory.

Cluster Memory

Data, address, and control inputs to the channel memory are

driven from horizontal and vertical routing channels. All data

and FIFO logic outputs drive dedicated tracks in the horizontal

and vertical routing channels. The clocks for the channel mem-

ory block are selected from four global clocks and pin inputs

from the horizontal and vertical channels. The clock muxes

also include a polarity mux for each clock so that the user can

choose an inverted clock.

Each logic block cluster of the Delta39K contains two 8192-bit

cluster memory blocks. Figure 5 is a block diagram of the clus-

ter memory block and the interface of the cluster memory block

to the cluster PIM.

The output of the cluster memory block can be optionally reg-

istered to perform synchronous pipelining or to register asyn-

chronous read and write operations. The output registers con-

tain an asynchronous RESET which can be used in any type

of sequential logic circuits (e.g., state machines)

Dual-Port (Channel Memory) Configuration

Each port has distinct address inputs, as well as separate data

and control inputs that can be accessed simultaneously. The

inputs to the Dual-Port memory are driven from the horizontal

and vertical routing channels. The data outputs drive dedicat-

ed tracks in the routing channels. The interface to the routing

is such that Port A of the Dual-Port interfaces primarily with the

horizontal routing channel and Port B interfaces primarily with

There are four global clocks (GCLK[3:0]) and one local clock

available for the input and the output registers. The local clock

for the input registers is independent of the one used for the

output registers. The local clock is generated in the user-de-

sign in a macrocell or comes from an I/O pin

the vertical routing channel.

.

Write

Control

Logic

DIN[7:0]

ADDR[12:0]

W E

3

D

Q

C

2

8

C

1024x8

Asynchronous

SRAM

10

C

Cluster PIM

GCLK[3:0]

5:1

Local CLK

3

C

8

C

DOUT[7:0]

Read

Control

Logic

Q

D

C

R

RESET

2

C

GCLK[3:0]

5:1

Local CLK

3

C

Figure 5. Block Diagram of Cluster Memory Block

7

Delta39K™ ISR™

CPLD Family

PRELIMINARY

The clocks for each port of the Dual-Port configuration are

selected from four global clocks and two local clocks. One local

clock is sourced from the horizontal channel and the other from

the vertical channel. The data outputs of the dual-port memory

can also be registered. Clock for the output registers are also

selected from four global clocks and two local clocks. One

clock polarity mux per port allows the use of true or comple-

ment polarity for input and output clocking purposes.

same horizontal or vertical routing channel without any speed

penalty.

In FIFO mode, the write and read ports are controlled by sep-

arate clock and enable signals. The clocks for each port are

selected from four global clocks and two local clocks.

One local clock is sourced from the horizontal channel and the

other from the vertical channel. The data outputs from the read

port of the FIFO can also be registered. One clock polarity mux

per port allows using true or complement polarity for read and

write operations. The write operation is controlled by the clock

and the write enable pin. The read operation is controlled by

the clock and the read enable pin. The enable pins can be

sourced from horizontal or vertical channels.

Arbitration

The Dual-Port configuration of the Channel Memory Block pro-

vides arbitration when both ports are accessed at the same

time. Depending on the memory operation being attempted,

one port always gets priority. See Table 1 for details on which

port gets priority for read and write operations. An active-LOW

‘Address Match’ signal is generated when address collision

occurs.

Channel Memory Initialization

The channel memory powers up in an undefined state, but is

set to a user-defined known state during configuration. To fa-

cilitate the use of look-up-table (LUT) logic and ROM applica-

tions, the channel memory blocks can be initialized with a giv-

en set of data when the device is configured at power up. For

LUT and ROM applications, the user cannot write to memory

blocks.

Table 1. Arbitration Result: Address Match Signal

Becomes Active

Result of

Port A Port B Arbitration

Comment

Read

Read No arbitration Both ports read at the

Channel Memory Routing Interface

required

same time

Write

Read Port A gets

priority

If Port B requests first

then it will read the cur-

rent data. The output will

then change to the newly

written data by Port A

Similar to LBC outputs, the channel memory blocks feature

dedicated tracks in the horizontal and vertical routing channels

for the data outputs and the flag outputs, as shown in Figure

6. This allows the channel memory blocks to be expanded eas-

ily. These dedicated lines can be routed to I/O pins as chip

outputs or to other logic block clusters to be used in logic equa-

tions.

Read

Write

Write Port B gets

priority

If Port A requests first

then it will read the cur-

rent data. The output will

then change to the newly

written data by Port B

I/O Banks

The Delta39K interfaces the horizontal and vertical routing

channels to the pins through I/O banks. There are 8 I/O banks

per device as shown in Figure 7 and all I/Os from an I/O bank

are located in the same section of a package for PCB layout

convenience.

Write Port A gets

priority

Port B is blocked until

Port A is finished writing

FIFO (Channel Memory) Configuration

The channel memory blocks are also configurable as synchro-

nous FIFO RAM. In the FIFO mode of operation, the channel

memory block supports all normal FIFO operations without the

use of any general-purpose logic resources in the device.

Each I/O bank contains several I/O cells, and each I/O cell

contains an input/output register, an output enable register,

programmable slew rate control and programmable bus hold

control logic. Each I/O cell drives a pin output of the device; the

cell also supplies an input to the device that connects to a

dedicated track in the associated routing channel.

The FIFO block contains all of the necessary FIFO flag logic,

including the read and write address pointers. The FIFO flags

include an empty/full flag (EF), half-full flag (HF), and program-

mable almost-empty/full (PAEF) flag output. The FIFO config-

uration has the ability to perform simultaneous read and write

operations using two separate clocks. These clocks may be

tied together for a single operation or may run independently

for asynchronous read/write (w.r.t. each other) applications.

The data and control inputs to the FIFO block are driven from

the horizontal or vertical routing channels. The data and flag

outputs are driven onto dedicated routing tracks in both the

horizontal and vertical routing channels. This allows the FIFO

blocks to be expanded by using multiple FIFO blocks on the

There are four dedicated inputs (GCTl[3:0]) that are used as

Global Control Signals available to every I/O cell. These global

control signals may be used as output enables, register resets

and register clock enables as shown in Figure 8.

Each I/O bank can use any supported I/O standard by supply-

ing appropriate V

and V

voltages. All the V and

REF

CCIO

REF

V

pins in an I/O bank must be connected to the same V

CCIO

REF

and V

voltage respectively. This requirement restricts the

CCIO

number of IO standards supported by an IO bank at any given

time.

8

Delta39K™ ISR™

CPLD Family

PRELIMINARY

All channel memory

inputs are driven from

the routing channels

4096-bit Dual Port

Global Clock

Signals

Array

Configurable as

Async/Sync Dual Port or

Sync FIFO

GCLK[3:0]

Configurable as

4Kx1, 2Kx2, 1Kx4 and

512x8 block sizes

All channel memory outputs

drive dedicated tracks in the

routing channels

Horizontal Channel

Figure 6. Block Diagram of Channel Memory Block

IO Standards

I/O

Standard

Termination

bank 7

bank 6

V

(V)

V

Voltage (V

)

REF

CCIO

TT

Min

Max

LVTTL

N/A

3.3 V

3.0 V

2.5 V

1.8 V

3.3 V

N/A

1.5

LVCMOS

LVCMOS3

LVCMOS2

LVCMOS18

3.3V PCI

GTL+

Delta39K

0.9

1.3

1.1

1.7

bank 2

bank 3

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

HSTL I

3.3 V

2.5 V

1.5 V

1.5

1.3

1.7

1.5

Figure 7. Delta39K I/O Bank Block Diagram

1.15

0.68

1.35

0.9

1.25

0.75

1.5

HSTL II

0.9

HSTL III

HSTL IV

0.9

1.5

9

Delta39K™ ISR™

CPLD Family

PRELIMINARY

.

Registered OE

Mux

OE Mux

D

Q

From

Output PIM

C

3

C

Input

Mux

RES

To Routing

Channel

Register Input

Mux

C

Output Mux

Bus

Hold

I/O

Register Enable

Mux

D

E

Q

Clock

C

Polarity

Mux

Slew

Rate

RES

3

C

Control

Clock Mux

C

2

C

Register Reset

Mux

3

C

Figure 8. Block Diagram of I/O Cell

I/O Cell

pull-up resistor, is a weak latch connected to the pin that does

not degrade the device’s performance. As a latch, bus-hold

maintains the last state of a pin when the pin is placed in a

high-impedance state, thus reducing system noise in bus-in-

terface applications. Bus-hold additionally allows unused de-

vice pins to remain unconnected on the board, which is partic-

ularly useful during prototyping as designers can route new

Figure 8 is a block diagram of the Delta39K I/O cell. The I/O

cell contains a three-state input buffer, an output buffer, and a

register that can be configured as an input or output register.

The output buffer has a slew rate control option that can be

used to configure the output for a slower slew rate. The input

of the device and the pin output can each be configured as

registered or combinatorial, however only one path can be

configured as registered in a given design.

signals to the device without cutting trace connections to V

CC

or GND. For more information, see the application note “Un-

derstanding Bus-hold − A Feature of Cypress CPLDs.”

The output enable can be selected from one of the four global

control signals or from one of two Output Control Channel

(OCC) signals. The output enable can be configured as always

enabled or always disabled or it can be controlled by one of the

remaining inputs to the mux. The selection is done via a mux

Clocks

Delta39K has four dedicated clock input pins (GCLK[3:0]) to

accept system clocks. One of these clocks (GCLK[0]) may be

selected to drive an on-chip Phase-Locked Loop (PLL) for fre-

quency modulation (see Figure 9 for details).

that includes V and GND as inputs.

CC

One of the global clocks can be selected as the clock for the

I/O cell register. The clock mux output is an input to a clock

polarity mux that allows the input/output register to be clocked

on either edge of the clock.

The global clock tree for a Delta39K device can be driven by a

combination of the dedicated clock pins and/or the PLL-de-

rived clocks. The global clock tree consists of four global clocks

that go to every macrocell, memory block, and I/O cell.

Slew Rate Control

Clock Tree Distribution

The ouput buffer has a slew rate control option. This allows the

ouput buffer to slew at fast rate (3 V/ns) or a slow rate (1 V/ns).

All I/Os default to fast slew rate. For designs concerned with

meeting FCC emissions standards the slow edge provides for

lower system noise. For designs requiring very high perfor-

mance the fast edge rate provides maximum system perfor-

mance.

The global clock tree performs two primary functions. First, the

clock tree generates the four global clocks by multiplexing four

dedicated clocks from the package pins and four PLL driven

clocks. Second, the clock tree distributes the four global clocks

to every cluster, channel memory, and I/O block on the die. The

global clock tree is designed such that the clock skew is mini-

mized while maintaining an acceptable clock delay.

Programmable Bus Hold

On each I/O pin, user-programmable-bus-hold is included.

Bus-hold, which is an improved version of the popular internal

10

Delta39K™ ISR™

CPLD Family

PRELIMINARY

off-chip signal (external feedback)

INTCLK0, INTCLK1, INTCLK2, INTCLK3

Any Register

Send a global

clock off chip

GCLK1

Normal I/O signal path

Lock Detect/IO pin

C

Clock Tree

Delay

Phase selection

Divide

1-6,8,16

2

÷

C

INTCLK0

GCLK0

fb

Lock

2

Phase selection

C

Divide

1-6,8,16

÷

Clk 0⁰

INTCLK1

Clk 45⁰

GCLK1

Clk 90⁰

Clk 135⁰

Clk 180⁰

Clk 225⁰

Clk 270⁰

Clk 315⁰

Phase selection

2

GCLK0

Source

Clock

C

Divide

1-6,8,16

INTCLK2

GCLK2

2

PLL

X1, X2, X4

C

Phase selection

Divide

1-6,8,16

÷

INTCLK3

GCLK3

2

C

Figure 9. Block Diagram of Spread Aware PLL

Spread Aware™ PLL

The Voltage Controlled Oscillator (VCO), the core of the

Delta39K PLL is designed to operate within the frequency

range of 100 MHz to 266 MHz. Hence, the multiply option com-

bined with input (GCLK[0]) frequency should be selected such

that this VCO operating frequency requirement is met. This is

demonstrated in Table 2 (columns 1, 2, and 3)

Each device in the Delta39K family features an on-chip PLL

designed using Spread Aware technology for low EMI applica-

tions. In general, PLLs are used to implement time-division-

multiplex circuits to achieve higher performance with fewer de-

vice resources.

Another feature of this PLL is the ability to drive the output

clock (INTCLK) off the Delta39K chip to clock other devices on

the board, as shown in Figure 9 above. This off-chip clock is

half the frequency of the output clock as it has to go through a

register (I/O register or a macrocell register).

For example, a system that operates on a 32-bit data path that

runs at 40 MHz can be implemented with 16-bit circuitry that

runs internally at 80 MHz. PLLs can also be used to take ad-

vantage of the positioning of the internally generated clock

edges to shift performance towards improved setup, hold or

clock-to-out times.

This PLL can also be used for board de-skewing purpose by

driving a PLL output clock off-chip, routing it to the other devic-

es on the board and feeding it back to the PLL’s external feed-

back input (GCLK[1]). When this feature is used only a limited

multiply, divide and phase shift options can be used.

There are several frequency multiply (X1, X2, X4) and divide

(/1, /2, /3, /4, /5, /6. /8, /16) options available to create a wide

range of clock frequencies from a single clock input (GCLK[0]).

For increased flexibility, there are seven phase shifting options

which allow clock skew/de-skew by 45°, 90°, 135°, 180°, 225°,

270° or 315°.

Table 2 describes the valid multiply and divide options that can

be used without an external feedback. Table 3 describes the

valid multiply & divide options that can be used with an external

feedback.

Table 2. PLL Multiply and Divide Options—without External Feedback

Valid Multiply Options

Input Frequency

Valid Divide Options

(GCLK[0])

(MHz)

VCO Output

Output Frequency (INTCLK[3:0]) Off-chip Clock

f

Value Frequency (MHz)

Value

f

(MHz)

Frequency

PLLI

PLLO

25–33

4

2

1

100–133

133–200

200–266

100–133

133–200

200–266

100–133

1–6, 8, 16

6.25–133

8.33–200

12.5–266

6.25–133

8.3–200

3.12–66

33–50

4.16–100

6.25–133

3.12–66

50–66

66–100

4.16–100

6.25–133

3.12–66

12.5–266

6.25–133

100–133

11

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Table 3. PLL Multiply and Divide Options—with External Feedback

Valid Multiply Options

Valid Divide Options

Output (INTCLK) Frequency

Input (GCLK) Frequency

(MHz)

VCO Output

Off-chip Clock

Frequency

f

Value

Frequency (MHz)

Value

f

(MHz)

PLLI

PLLO

50–66

1

100–133

133–200

200–266

1

100–133

133–200

200–266

50–66

66–100

100–133

66–100

100–133

Table 5 is an example of the effect of all the available divide

and phase shift options on a VCO output of 250 MHz. It also

shows the effect of division on the duty cycle of the resultant

clock. Note that the duty cycle is 50-50 when a VCO output is

divided by an even number. Also note that the phase shift ap-

plies to VCO output and not to the divided output

Table 4 describes the valid phase shift options that can be used

with or without an external feedback.

Table 4. PLL Phase Shift Options—

with and without External Feedback

With External

Feedback

This Spread Aware PLL operates as specified in Delta39K ‘V’

devices (2.5V/3.3V). It does not operate om Delta39K ‘Z’ de-

vices (1.8V). For more details on the architecture and opera-

tion of this PLL please refer to an application note titled

“Delta39K PLL and Clock Tree.”

Without External Feedback

0°,45°, 90°, 135°, 180°, 225°, 270°, 315°

0°

Table 5. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz

Duty

Divide

Factor

Period

(ns)

Cy-

0°

45°

90°

135°

180°

225°

270°

(ns)

315°

(ns)

cle%

(ns)

1

2

4

40-60

50

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

8

3

12

16

20

24

32

64

33-67

50

4

5

40-60

50

6

8

50

16

50

12

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Timing Model

10. For synchronous systems, the input set-up time to the out-

put macrocell register and the clock to output time are shown

One important feature of the Delta39K family is the simplicity

of its timing. All combinatorial and registered/synchronous de-

lays are worst case and system performance is static (as

shown in the AC specs section) as long as data is routed

through the same horizontal and vertical channels. Figure 10

illustrates the true timing model for the 200-MHz devices. For

synchronous clocking of macrocells, a delay is incurred from

macrocell clock to macrocell clock within the same cluster and

as the parameters t

and t

shown in the Figure 10.

MCS

MCCO

These measurements are for any output and synchronous

clock, regardless of the logic placement.

The Delta39K features:

• no dedicated vs. I/O pin delays

• no penalty for using 0–16 product terms

• no added delay for steering product terms

• no added delay for sharing product terms

• no output bypass delays

in different clusters. This is shown as t

and t

in Figure

SCS

SCS2

10. For combinatorial paths, any input to any output (from cor-

ner to corner on the device), incurs a worst-case delay in the

39K100 regardless of the amount of logic or which horizontal

The simple timing model of the Delta39K family eliminates un-

expected performance penalties.

and vertical channels are used. This is the t shown in Figure

PD

t

SCS

GCLK[3:0]

4

LB

0

1

2

3

LB

7

6

LB

0

1

2

3

LB

7

6

LB

0

1

2

3

LB

7

6

5

4

LB

7

6

LB

0

1

2

3

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

P IM

PIM

P IM

LB

5

4

LB

5

4

LB

5

4

t

MCS

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

8

Kb

8

Kb

SRAM

GCLK[3:0]

4

t

SCS2

LB

0

1

2

3

LB

7

6

5

4

LB

0

1

2

3

LB

7

6

5

4

LB

0

1

2

3

LB

7

6

5

4

LB

0

1

2

3

LB

7

6

5

4

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

PIM

t

PD

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

GCLK[3:0]

4

LB

7

6

5

4

LB

0

1

2

3

LB

7

6

LB

0

1

2

3

LB

0

1

2

3

LB

7

6

5

4

LB

0

1

2

3

LB

7

6

5

4

Channel

RAM

Channel

RAM

Channel

RAM

Channel

RAM

P IM

PIM

P IM

LB

5

4

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

Cluster

RAM

t

MCCO

Figure 10. Timing Model for 39K100 Device

13

Delta39K™ ISR™

CPLD Family

PRELIMINARY

IEEE 1149.1 Compliant JTAG Operation

1076/1164 VHDL and IEEE 1364 as the Hardware Description

Language (HDL) for design entry. Warp accepts VHDL or Ver-

ilog input, synthesizes and optimizes the entered design, and

outputs a configuration bitstream for the desired Delta39K de-

vice. For simulation, Warp provides a graphical waveform sim-

ulator as well as VHDL and Verilog Timing Models.

The Delta39K family has an IEEE std 1149.1 JTAG interface

for both Boundary Scan and ISR operations.

Four dedicated pins are reserved on each device for use by

the Test Access Port (TAP).

VHDL and Verilog are open, powerful, non-proprietary Hard-

ware Description Languages (HDLs) that are standards for be-

havioral design entry and simulation. HDL allows designers to

learn a single language that is useful for all facets of the design

process.

Boundary Scan

The Delta39K family supports Bypass, Sample/Preload, Ex-

test, Intest, Idcode and Usercode boundary scan instructions.

The JTAG interface is shown in Figure 11.

Third-Party Software

Instruction Register

Cypress products are supported in a number of third-party de-

sign entry and simulation tools. Refer to the third-party soft-

ware data sheet or contact your local sales office for a list of

currently supported third party vendors.

TDI

TDO

Bypass Reg.

JTAG

TAP

CONTROLLER

TMS

Programming

Boundary Scan

idcode

There are three programming options available for Delta39K

devices. The first method is to use a PC with the Delta39K ISR

programming cable and software. With this method, the ISR

pins of the Delta39K devices are routed to a connector at the

edge of the printed circuit board. The Delta39K ISR program-

ming cable is then connected between the PC and this con-

nector. A simple configuration file instructs the ISR software of

the programming operations to be performed on each of the

Delta39K devices in the system. The ISR software then auto-

matically completes all of the necessary data manipulations

required to accomplish the programming, reading, verifying,

and other ISR functions. For more information on Cypress ISR

Interface, see the ISR Programming Kit data sheet (CY3900i).

TCLK

Usercode

ISR Prog.

Data Registers

Figure 11. JTAG Interface

In-System Reprogramming (ISR)

In-System Reprogramming is the combination of the capability

to program or reprogram a device on-board, and the ability to

support design changes without changing the system timing

or device pinout. This combination means design changes

during debug or field upgrades do not cause board respins.

The Delta39K family implements ISR by providing a JTAG

compliant interface for on-board programming, robust routing

resources for pinout flexibility, and a simple timing model for

consistent system performance.

The second method for programming Delta39K devices is on

automatic test equipment (ATE). This is accomplished through

a STAPL file created by the ISR software. Check the Cypress

website for the latest ISR software download information

(http://www.cypress.com).

The third programming option for Delta39K devices is to utilize

the embedded controller or processor that already exists in the

system. The Delta39K ISR software assists in this method by

converting the device JEDEC maps into the ISR serial stream

that contains the ISR instruction information and the address-

es and data of locations to be programmed. The embedded

controller then simply directs this ISR stream to the chain of

Delta39K devices to complete the desired reconfiguring or di-

agnostic operations. Contact your local sales office for infor-

mation on availability of this option.

Configuration

Configuration is defined as the process of loading the volatile

SRAM memory locations with the data generated from the

Warp design tools to implement user’s logic design.

Delta39K devices can be configured using two methods: serial

mode and through the IEEE std 1149.1 JTAG interface. Device

configuration can begin in 3 ways. It can be done automatically

after power-up of the system, by toggling Reconfig pin from

LOW to HIGH, or by issuing the Self Config Initiate instruction

through the IEEE std 1149.1 JTAG interface.

Third-Party Programmers

As with development software, Cypress support is available on

a wide variety of third-party programmers. All major program-

mers (including BP Micro, System General, Hi-Lo) support the

Delta39K family.

Development Software Support

Warp

Warp is a state-of-the-art HDL compiler for designing with Cy-

press programmable logic. Warp utilizes a subset of IEEE

14

Delta39K™ ISR™

CPLD Family

PRELIMINARY

V

to Ground Potential (39KV device)............–0.5V to 4.6V

Maximum Ratings

CC

to Ground Potential................................–0.5V to 4.6V

CCIO

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

DC Voltage Applied to Outputs in High Z State –0.5V to 4.5V

DC Input voltage......................... ......................–0.5V to 4.5V

Storage Temperature .................................. –65°C to +150°C

SolderingTemperature...................................................220°C

[5]

DC Current into Outputs............................................±20mA

Static Discharge Voltage (per MIL-STD-8883,

Ambient Temperature with

Power Applied............................................... –40°C to +85°C

Method 3015).............................................................>2001V

Latch-Up Current.......................................................>200 mA

Junction Temperature....................................................135°C

V

to Ground Potential (39KZ device)......... .. –0.5V to 2.5V

CC

Operating Range

Ambient

Temperature

Junction

Temperature

Output

Condition

V

/

CCJTAG

CCCNFG

Range

V

CCPRG

CCIO

CC

CCPLL

0°C to +70°C

0°C to +85°C

3.3V

2.5V

1.8V

1.5V

3.3V

2.5V

1.8V

1.5V

3.3V ± 0.3V

2.5V ± 0.2V

3.3V ± 0.3V

or

Same as

Same

as V

3.3V

±

Commercial

1.8V ± 0.15V 2.5V ± 0.2V

V

CCIO

CC

or

0.3V

[4]

1.5V ± 0.1V

1.8V ± 0.15V

–40°C to +85°C –40°C to +100°C

3.3V ± 0.3V

2.5V ± 0.2V

1.8V ± 0.15V

Industrial

[4]

1.5V ± 0.1V

DC Characteristics

V

= 3.3 V

V

= 2.5 V

V

= 1.8 V

CCIO

Parameter Description

Test Conditions

Min. Max. Min. Max. Min. Max. Unit

Data Retention V Voltage

(config data may be lost below this)

1.5

V

CC

V

DRINT

DRIO

Data Retention V

Voltage

1.2

V

CCIO

(config data may be lost below this)

I

Input Leakage Current

GND ≤ V ≤ 3.6V

–10

10

–10

10

–10

10

µA

IX

I

Output Leakage Current

GND ≤ V ≤ V

O CCIO

OZ

OS

V

= Max.,

= 0.5V

–160

–160 mA

[6]

CCIO

I

Output Short Circuit Current

OUT

Input Bus Hold LOW Sustaining

Current

+40

+30

+25

µA

V

= Min., V

= V

BHL

CC

IL

Input Bus Hold HIGH Sustaining

Current

–40

–30

–25

µA

= Min., V = V

BHH

IH

Input Bus Hold LOW Overdrive

Current

+250

+200

+150 µA

–150 µA

= Max.

BHLO

BHHO

Input Bus Hold HIGH Overdrive

Current

–250

–200

Capacitance

Parameter

Description

Test Conditions

@ f=1MHz 25°C

Min.

Max.

Unit

pF

C

Input/Output Capacitance

Clock Signal Capacitance

V =V

8

I/O

in

CCIO

V =V

5

12

pF

CLK

in

Notes:

5. DC current into outputs is 36 mA with HSTL III and 48 mA with HSTL IV

6. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V_OUT=0.5V has been chosen to avoid test problems

caused by tester ground degradation. Tested initially and after any design or process changes that may affect these parameters.

15

Delta39K™ ISR™

CPLD Family

PRELIMINARY

DC Characteristics (IO)

V

(V)

V

(V)

V

(V)

V

(V)

V (V)

IL

REF

OH

OL

IH

Input/

Output

V

OL

(max.)

CCIO

(V)

Standard

@ I

=

V

(min.) @ I =

OL

Min.

2.0 V

1.7 V

Max.

Min.

Max.

OH

LVTTL

3.3

3.0

2.5

–4 mA

2.4

4 mA

0.4

V

+0.3 –0.3V

0.8V

0.7V

CCIO

LVCMOS

LVCMOS3

–0.1 mA

–1.0 mA

–2.0 mA

–0.1 mA

– 2 mA

V

–0.2v 0.1 mA

–0.2v 0.1mA

0.2

CCIO

V

0.2

2.1

2.0

1.7

0.1 mA

1.0 mA

2.0 mA

0.2

LVCMOS2

0.4

0.7

1.8

3.3

V

–0.2v 0.1mA

0.2

0.65V

V

+0.3 –0.3V 0.35V

CCIO

LVCMOS18

V

–0.45v 2.0 mA

0.45

CCIO

3.3V PCI

GTL+

–0.5 mA

0.9V

1.5 mA 0.1V

0.5V

+0.5 –0.5V 0.3V

CCIO

0.9 1.1 Note 7

Note 8

8 mA

0.6

0.7

V

+0.2

+1.8

+1.0

V

–0.2

REF

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

HSTL I

1.3 1.7

3.3

–8 mA

–16 mA

–7.6 mA

V

–1.1v

V

+0.3 –0.3V

CCIO

V

–0.9v 16 mA

0.5

1.15 1.35 2.5

V

–0.62v 7.6 mA

–0.43v 15.2 mA

0.54

0.35

0.4

V

–0.18

CCIO

REF

1.15 1.35 2.5 –15.2 mA V

V

0.68 0.9

1.5

–8 mA

–16 mA

–8 mA

V

–0.4v

8 mA

V

–0.1

CCIO

REF

HSTL II

HSTL III

HSTL IV

V

–0.4v 16 mA

–0.4v 24 mA

–0.4v 48 mA

0.4

V

0.4

V

0.4

Configuration Parameters

Parameter

Description

Reconfig pin LOW time before it goes HIGH

Min

200

Units

ns

t

RECONFIG

Notes:

7. See “Power-up Sequence Requirements” below for V_CCIOrequirement.

8. 25Ω resistor terminated to termination voltage of 1.5V.

Power-up Sequence Requirements

• Upon power-up, all the outputs remain three-stated until all

• All V

s on a bank should be tied to the same potential

CCIO

the V pins have powered-up to the nominal voltage and

and powered up together.

CC

the part has completed configuration.

• All V

s (even the unused banks) need to be powered up

CCIO

• The part will not start configuration until V , V

,

CCIO

to at least 1.5V before configuration has completed.

CC

V

, V

and V

have reached

CCPRG

CCJTAG

CCCNFG

CCPLL

• Maximum ramp time for all V s should be 0V to nominal

voltage in 100 ms.

CC

nominal voltage.

• V pins can be powered up in any order.

CC

16

Delta39K™ ISR™

CPLD Family

PRELIMINARY

[9]

Switching Characteristics - Parameter Descriptions Over the Operating Range

Parameter

Description

Combinatorial Mode Parameters

Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output

on the horizontal or vertical channel associated with that cluster

t

PD

t

Global control to output enable

Global control to output disable

EA

ER

Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical

channel associated with the cluster the macrocell is in

t

PRR

PRO

Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associ-

ated with the cluster that the macrocell is in to any pin output on those same channels

t

Synchronous Clocking Parameters

Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative

t

MCS

to a global clock

Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative

to a global clock

MCH

Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with

the cluster that macrocell is in

MCCO

t

Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock

Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock

Clock to output of an I/O cell register to the output pin associated with that register

Macrocell clock to macrocell clock through array logic within the same cluster

IOS

IOH

IOCO

SCS

SCS2

ICS

Macrocell clock to macrocell clock through array logic in different clusters

I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with

Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that

the macrocell is in

t

OCS

t

f

Clock to output disable (high-impedance)

CHZ

CLZ

MAX

Clock to output enable (low-impedance)

Maximum frequency with internal feedback—within the same cluster

Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or

vertical channel

f

MAX2

Product Term Clock

t

Set-up time for macrocell used as input register from input to product term clock

Macrocell used as an input register hold time

MCSPT

MCHPT

MCCOPT

SCS2PT

Product term clock to output delay from input pin

Register to register delay through logic array with a product term clock within different clusters

Channel Interconnect Parameters

t

Adder for a signal to switch from a horizontal to vertical channel and vice-versa

Cluster to Cluster delay adder (through channels and channel PIM)

CHSW

t

CL2CL

Miscellaneous Delays

Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This

t

parameter can be added to t and t

parameter for each extra pass through the AND/OR array required

CPLD

PD

SCS

by a given signal path

t

Adder for carry chain logic per macrocell

MCCD

Delay from the input of the output buffer to the I/O pin

Delay from the I/O pin to the input of the channel buffer

IOD

IOIN

17

Delta39K™ ISR™

CPLD Family

PRELIMINARY

[9]

Switching Characteristics - Parameter Descriptions Over the Operating Range

Parameter

Description

Delay from the clock pin to the input of the clock driver

t

CKIN

IOREGPIN

Delay from the I/O pin to the input of the I/O register

PLL Parameters

t

f

Maximum cycle to cycle jitter time

PLL delay with skew adjustment

PLL delay without any skew adjustment

Lock time for the PLL

MCCJ

DWSA

DWOSA

LOCK

PLLO

PLLI

Output frequency of the PLL

Input frequency of the PLL

Cluster Memory Timing Parameter Descriptions Over the Operating Range

Parameter

Description

Asynchronous Mode Parameters

t

Cluster memory access time. Delay from address to read data out

Write enable pulse width

CLMAA

CLMPWE

CLMSA

CLMHA

CLMSD

CLMHD

Address setup to the beginning of write

Address hold after the end of write

Data set-up to the end of write

Data hold after the end of write

Synchronous Mode Parameters

t

Clock cycle time for flow-through read and write operations

Clock cycle time for pipelined read and write operations

CLMCYC1

CLMCYC2

CLMS

Address, data, and WE set-up time of pin inputs, relative to a global clock

Address, data, and WE hold time of pin inputs, relative to a global clock

Global clock to data valid on output pins for flow through data

Global clock to data valid on output pins for pipelined data

CLMH

CLMDV1

CLMDV2

Internal Parameters

t

Asynchronous cluster memory access time from input of cluster to output of cluster

CLMCLAA

Internal clock cycle time for pipelined read and write operations. It includes the delay from a global clock,

through the cluster memory and set-up into the cluster memory output register

CLMCYC3

t

Cluster memory input clock to macrocell clock

Cluster memory output clock to macrocell clock

Macrocell clock to cluster memory input clock

Macrocell clock to cluster memory output clock

CLMMACS1

CLMMACS2

MACCLMS1

MACCLMS2

Note:

9. Add t_CHSWto signals making a horizontal to vertical channel switch or vice-versa,

18

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Channel Memory Timing Parameter Descriptions Over the Operating Range

Parameter

Description

Dual Port Asynchronous Mode Parameters

t

Channel memory access time. Delay from address to read data out

Write enable pulse width

CHMAA

CHMPWE

CHMSA

CHMSD

CHMHD

CHMBA

Address setup to the beginning of write

Data set-up to the end of write

Data hold after the end of write

Channel memory asynchronous dual port address match (busy access time)

Dual Port Synchronous Mode Parameters

t

Clock cycle time for flow through read and write operations

CHMCYC1

CHMCYC2

CHMS

Clock cycle time for pipelined read and write operations

Address, data, and WE set-up time of pin inputs, relative to a global clock

Address, data, and WE hold time of pin inputs, relative to a global clock

Global clock to data valid on output pins for flow through data

Global clock to data valid on output pins for pipelined data.

CHMH

CHMDV1

CHMDV2

CHMBDV

Channel memory synchronous dual-port address match (busy, clock to data valid)

Synchronous FIFO Data Parameters

t

Read and write minimum clock cycle time

CHMCLK

CHMFS

Data, read enable, and write enable set-up time relative to pin inputs

Data, read enable, and write enable hold time relative to pin inputs

Data access time to output pins from rising edge of read clock (read clock to data valid)

Channel memory FIFO read clock to macrocell clock with read data

Macrocell clock to channel memory FIFO write clock with write data

CHMFH

CHMFRDV

CHMMACS

MACCHMS

Synchronous FIFO Flag Parameters

t

Read or write clock to respective flag output at output pins

Read or write clock to macrocell clock with FIFO flag

Master Reset Pulse Width

CHMFO

CHMMACF

CHMFRS

Master Reset Recovery Time

CHMFRSR

CHMFRSF

CHMSKEW1

CHMSKEW2

CHMSKEW3

Master Reset to Flag and Data Output Time

Read/Write Clock Skew Time for Full Flag

Read/Write Clock Skew Time for Empty Flag

Read/Write Clock Skew Time for Boundary Flags

Internal Parameters

t

Asynchronous channel memory access time from input of channel memory to output of channel memory

CHMCHAA

CHMCYC3

Internal pipelined memory access time. The delay from a global clock, through the channel memory and

setup into the channel memory output register

t

Channel memory input clock to macrocell clock

Channel memory output clock to macrocell clock

Macrocell clock to channel memory input clock

Macrocell clock to channel memory output clock

CHMMACS1

CHMMACS2

MACCHMS1

MACCHMS2

19

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Characteristics - Parameter Values Over the Operating Range

125

83

250

222

200

181

167

154

Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Combinatorial Mode Parameters

t

6.5

4.0

7.0

4.5

7.5

5.0

8.0

5.5

8.5

6.5

9.0

7.5

10

9.0

15

10

ns

PD

EA

ER

6.0

9.0

6.0

9.5

6.0

10

6.0

11

7.0

12

8.0

13

10

15

PRR

PRO

10.5

Synchronous Clocking Parameters

t

f

2.5

0.0

2.7

0.0

3.0

0.0

3.3

0.0

3.5

0.0

4.0

0.0

5.0

0.0

6.0

0.0

ns

MCS

MCH

MCCO

IOS

5.0

3.2

5.5

3.6

6.0

4.0

6.5

4.5

7.5

5.0

8.5

6.0

10

12

0.8

0.9

1.0

1.2

1.4

1.7

2.0

2.5

IOH

7.0

8.0

IOCO

SCS

SCS2

ICS

3.2

4.0

3.6

4.5

4.0

5.0

4.4

5.5

4.8

6.0

5.2

6.5

6.4

8.0

9.6

12

OCS

CHZ

CLZ

3.0

3.3

3.5

4.0

4.5

5.0

6.0

7.0

1.6

1.8

2.0

2.4

2.8

3.2

3.6

4.0

313

250

278

222

250

200

227

181

208

167

192

154

156

125

104 MHz

83 MHz

MAX

MAX2

Product Term Clocking Parameters

t

2.5

0.8

2.7

0.9

3.0

3.3

1.2

3.5

4.0

5.0

6.0

ns

MCSPT

MCHPT

MCCOPT

SCS2PT

1.0

1.4

1.7

2.0

2.5

7.0

7.5

8.0

8.5

9.0

10.0

11.0

15.0

ns

5.5

6.0

6.5

7.0

7.5

9.0

10.0

15.0

Channel Interconnect Parameters

t

0.8

1.6

0.9

1.8

1.0

2.0

1.1

2.2

1.2

2.4

1.4

2.6

1.7

2.8

2.0

3.0

ns

CHSW

CL2CL

Miscellaneous Parameters

t

2.5

0.2

2.8

3.0

3.3

3.5

3.8

4.0

5.0

ns

CPLD

0.22

0.25

0.28

0.30

0.32

0.35

0.38

MCCD

PLL Parameters

t

f

0.45

0.32

3.0

0.48

0.33

3.0

0.50

0.35

3.0

0.53

0.37

3.0

0.55

0.39

3.0

0.58

0.40

3.0

0.60

0.42

3.0

0.65

0.46

3.0

ns

MCCJ

DWSA

DWOSA

LOCK

ns

ms

[10]

6.2 266 6.2 266 6.2 266 6.2 266 6.2 266 6.2 266 6.2

25 133 25 133 25 133 25 133 25 133 25 133 25

200 6.2 200 MHz

100 25 100 MHz

PLLO

[10]

PLLI

Note:

10. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operation & specification

20

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Input & Output Standard Timing Delay Adjustments

[11]

All the timing specifications in this data sheet are specified based on 3.3V PCI compliant inputs and outputs (fast slew rates ).

Apply following adjustments if the inputs and outputs are configured to operate at other standards.

Output Delay Adjustments

Input Delay Adjustments

Input/Output

Standard

t

IOREGPIN

IOD

EA

ER

IOIN

CKIN

LVTTL

0.2

0.3

0.5

2.1

0

LVCMOS

LVCMOS3

LVCMOS2

LVCMOS18

3.3V PCI

GTL+

0

0.05

0.1

0.7

0

0.1

0.2

0.5

0

0.1

0.2

0.4

0

0.2

0.4

0.3

0

0.1

0

[12]

0.6

0.3

0.2

0.4

0.2

0.9

0.8

0.5

0.6

0.9

0.1

0

0.5

0.9

0.5

0.4

0.3

0.5

0.2

0.3

0.6

0.3

SSTL3 I

SSTL3 II

SSTL2 I

SSTL2 II

HSTL I

-0.3

-0.4

-0.1

-0.2

0.6

0

0.5

0.1

0

HSTL II

0.4

HSTL III

0.6

HSTL IV

0.7

Notes:

11. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.

12. These delays are based on falling edge output. The rising edge delay depends on the size of pull up resistor and termination voltage.

21

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Cluster Memory Timing Parameter Values Over the Operating Range

83

250

222

200

181

167

154

125

Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Asynchronous Mode Parameters

t

9.0

10

11

12

13

15

17

20

ns

CLMAA

CLMPWE

CLMSA

CLMHA

CLMSD

CLMHD

5.0

1.6

0.8

5.0

0.3

5.5

1.8

0.9

5.5

0.4

6.0

2.0

1.0

6.0

0.5

6.5

2.2

1.1

6.5

0.6

7.0

2.5

1.2

7.0

0.7

8.0

2.8

1.5

8.0

0.8

10

3.2

1.8

10

12

4.0

2.0

12

0.9

1.0

Synchronous Mode Parameters

t

9.0

6.5

2.5

0.0

9.5

7.0

2.7

0.0

10

10.5

8.0

11

9.5

3.5

0.0

13

11

15

12

20

15

ns

CLMCY1

CLMCY2

CLMS

7.5

3.0

0.0

3.3

3.8

0.0

4.0

0.0

5.0

0.0

CLMH

9.0

6.5

10

11

12

13

15

17

10

20

15

CLMDV1

CLMDV2

7.0

7.5

8.0

8.5

9.0

Internal Parameters

t

5.0

4.0

7.0

4.0

3.2

5.5

4.5

7.5

4.5

3.6

6.0

5.0

8.0

5.0

4.0

6.5

5.5

8.5

5.5

4.4

7.0

6.0

9.0

6.0

4.8

7.5

8.0

7.0

10

8.0

12

10.0

15

ns

CLMCLAA

CLMCYC3

CLMMACS1

CLMMACS2

MACCLMS1

MACCLMS2

7.0

5.5

8.5

8.0

6.6

10

8.0

12

22

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Channel Memory Timing Parameter Values

83

250

222

200

181

167

154

125

Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Dual-Port Asynchronous Mode Parameters

t

9.0

10

11

12

13

15

17

20

ns

CHMAA

CHMPWE

CHMSA

CHMHA

CHMSD

CHMHD

CHMBA

5.0

1.6

0.8

5.0

0.3

5.5

1.8

0.9

5.5

0.4

6.0

2.0

1.0

6.0

0.5

6.5

2.2

1.1

6.5

0.6

7.0

2.5

1.2

7.0

0.7

8.0

2.8

1.5

8.0

0.8

10

3.2

1.8

10

12

4.0

2.0

12

0.9

1.0

8.0

8.5

9.0

10.0

11.0

12.0

14.0

16.0 ns

Dual-Port Synchronous Mode Parameters

t

9.0

6.5

2.7

0.0

9.5

7.0

3.0

0.0

10

8.0

3.5

0.0

11

9.5

4.0

0.0

13

11

15

12

20

15

ns

CHMCYC1

CHMCYC2

CHMS

7.5

3.3

0.0

4.5

0.0

5.0

0.0

6.0

0.0

CHMH

9.0

6.5

10

11

12

13

15

17

10

20

15

ns

CHMDV1

CHMDV2

7.0

7.5

8.0

8.5

9.0

Synchronous FIFO Data Parameters

t

4.2

3.5

0.0

6.0

4.2

4.6

3.7

0.0

6.5

4.6

5.0

4.0

0.0

7.0

5.0

5.4

4.3

0.0

7.5

5.4

5.8

4.5

0.0

8.0

5.8

6.2

5.0

0.0

9.0

6.2

7.4

6.0

10.6

7.0

ns

CHMCLK

CHMFS

0.0

CHMFH

10.0

7.4

13.0

10.6

CHMFRDV

CHMMACS

MACCHMS

ns

7.4

Synchronous FIFO Flag Parameters

t

10.0

8.0

10.5

8.5

11

9

11.5

9.5

12

10

13

11

15

13

20

17

10

ns

CHMFO

CHMMACF

CHMFRS

4.0

4.5

5.0

5.5

6.0

7.0

8.0

3.2

9.0

1.6

4.2

3.6

9.5

1.8

4.6

4.0

10.0

2.0

4.4

11.0

2.2

4.8

12.0

2.4

5.5

13.0

2.6

6.6

15.0

3.2

8.0

CHMFRSR

CHMFRSF

CHMSKEW1

CHMSKEW2

CHMSKEW3

18.0 ns

4.0

ns

2.0

2.2

2.4

2.6

3.2

5.0

5.4

5.8

6.2

7.4

10.6 ns

Internal Parameters

t

6.0

4.2

8.0

4.0

4.2

6.0

6.5

4.6

8.5

4.5

4.6

6.5

7.0

5.0

9.0

5.0

7.0

7.5

5.4

8.0

5.8

11.0

6.0

5.8

8.0

9.0

6.2

12.0

7.0

6.5

9.0

10.0

7.4

13.0

10.6

16.0

10

ns

CHMCHAA

CHMCYC3

10.0

5.5

14.0

8.0

CHMMACS1

CHMMACS2

MACCHMS1

MACCHMS2

5.4

7.6

9.0

7.5

10.0

13.0

23

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms

Combinatorial Output

INPUT

t_PD

COMBINATORIAL

OUTPUT

Delta39K-1

Registered Output with Synchronous Clocking (Macrocell)

INPUT

t_MCS

t_{M C H}

SYNCHRONOUS

CLOCK

t_WH

t_WL

REGISTERED

OUTPUT

t_MCC0

Delta39K-2

Registered Input in I/O Cell

REGISTERED

INPUT

t_IOH

t_IOS

INPUT REGISTER

CLOCK

t_IOCO

COMBINATORIAL

OUTPUT

Delta39K-3

24

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Clock to Clock

INPUT REGISTER

CLOCK

t_ICS

t_SCS

OUTPUT

REGISTER CLOCK

Delta39K-4

PT Clock to PT Clock

PT CLOCK

t_MCSPT

t_SCS2PT

MACROCELL

REGISTER CLOCK

Delta39K-5

Asynchronous Reset/Preset

t_PRW

RESET/PRESET

INPUT

t_PRO

REGISTERED

OUTPUT

t_PRR

CLOCK

Delta39K-6

Output Enable/Disable

GLOBAL CONTROL

INPUT

t_ER

t_EA

OUTPUTS

Delta39K-7

25

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Cluster Memory Asynchronous Timing

WRITE

READ

ADDRESS (AT

THE CLUSTER

INPUT)

WRITE ENABLE

t_CLMPWE

INPUT

t_CLMCLAA

OUTPUT

Delta39K-8

Cluster Memory Asynchronous Timing 2

WRITE

READ

ADDRESS (AT THE

I/O PIN)

t_CLMHA

t_CLMSA

WRITE ENABLE

t_CLMPWE

INPUT

t_CLMHD

t_CLMSD

t_CLMAA

OUTPUT

Delta39K-9

26

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Cluster Memory Synchronous Timing

READ

WRITE

READ

GLOBAL

CLOCK

t_CLMCYC1

t_CLMS

t_CLMH

ADDRESS

t_CLMS

t_CLMH

t_CLMS

t_CLMH

WRITE

ENABLE

REGISTERED

INPUT

t_CLMDV1

REGISTERED

OUTPUT

Delta39K-10

Cluster Memory Internal Clocking

MACROCELL

INPUT CLOCK

t_CLMMACS1

CLUSTER MEMORY

INPUT CLOCK

t_CLMMACS2

CLUSTER MEMORY

OUTPUT CLOCK

Delta39K-11

27

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Cluster Memory Output Register Timing (Asynchronous Inputs)

ADDRESS

WRITE

ENABLE

INPUT

t_CLMCYC3

GLOBAL CLOCK

(OUTPUT REGISTER)

t_CLMDV2

EGISTERED

OUTPUT

Delta39K-12

Cluster Memory Output Register Timing (Synchronous Inputs)

ADDRESS

WRITE

ENABLE

INPUT

t_CLMCYC2(external) / t_CLMCYC3(internal)

GLOBAL CLOCK

(INPUT REGISTER)

t_CLMS

t_CLMH

GLOBAL CLOCK

(OUTPUT REGISTER)

t_CLMDV2

REGISTERED

OUTPUT

Delta39K-13

28

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Channel Memory DP Asynchronous Timing

ADDRESS

t_CHMHA

t_CHMSA

t_CHMPWE

WRITE

ENABLE

t_CHMSD

t_CHMHD

INPUT

t_CHMAA

OUTPUT

Delta39K-14

Channel Memory Internal Clocking

MACROCELL INPUT

CLOCK

t_MACCHMS1

t_CHMMACS1

CHANNEL MEMORY

INPUT CLOCK

t_CHMMACS2

t_MACCHMS2

CHANNEL MEMORY

OUTPUT CLOCK

Delta39K-15

29

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Channel Memory Internal Clocking 2

MACROCELL INPUT

CLOCK

t_CHMMACS

CHANNEL MEMORY

INPUT CLOCK

t_MACCHMS

CHANNEL MEMORY

OUTPUT CLOCK

t_CHMMACF

FIFO READ OR

WRITE CLOCK

Delta39K-16

Channel Memory DP SRAM Flow Through R/W Timing

CLOCK

t_CHMCYC1

t_CHMS

t_CHMH

A_n+1

A_n

A_n+2

ADDRESS

A_n+3

WRITE

ENABLE

t_CHMS

t_CHMH

EGISTERED

NPUT

D_n+1

t_CHMDV1

REGISTERED

OUTPUT

D_n+2

D_n

Delta39K-17

30

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Channel Memory DP SRAM Pipeline R/W Timing

CLOCK

t_CHMCYC2

t_CHMS

t_CHMH

ADDRESS

A_n+1

A_n

A_n+2

A_n+3

t_CHMH

t_CHMS

WRITE

ENABLE

t_CHMH

t_CHMS

REGISTERED

INPUT

D_n+1

t_CHMDV2

REGISTERED

OUTPUT

D_n-1

Delta39K-18

31

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Channel Memory Synchronous FIFO Empty/Write Timing

PORT B CLOCK

t_CHMCLK

t_CHMFS

t_CHMFH

WRITE ENABLE

REGISTERED

INPUT

D_n+1

EMPTY FLAG

(active low)

t_CHMSKEW2

t_CHMFO

PORT A CLOCK

READ ENABLE

RE

t_CHMFRDV

REGISTERED

OUTPUT

Delta39K-19

32

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Channel Memory Synchronous FIFO Full/Read Timing

PORT A CLOCK

t_CHMCLK

t_CHMFS

t_CHMFH

READ ENABLE

t_CHMFRDV

REGISTERED

OUTPUT

FULL FLAG

(active low)

t_CHMFO

t_CHMSKEW1t_CHMFO

PORT B CLOCK

WRITE ENABLE

t_CHMS

t_CHMH

REGISTERED

INPUT

Delta39K-20

33

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Channel Memory Synchronous FIFO Programmable Flag Timing

PORT B CLOCK

t_CHMCLK

t_CHMFH

t_CHMFS

WRITE ENABLE

PROGRAMMABLE

ALMOST-EMPTY FLAG

(active LOW)

t_CHMSKEW3

t_CHMFO

PORT A CLOCK

READ ENABLE

t_CHMFH

t_CHMFS

PORT B CLOCK

t_CHMCLK

WRITE ENABLE

t_CHMFO

PROGRAMMABLE

ALMOST-FULL FLAG

(active LOW)

t_CHMSKEW3

PORT A CLOCK

READ ENABLE

Delta39K-21

34

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Switching Waveforms (continued)

Channel Memory Synchronous FIFO Master Reset Timing

t_CHMFRS

MASTER

RESET INPUT

t_CHMFRSR

READ ENABLE /

WRITE ENABLE

t_CHMFRSF

EMPTY/FULL

PROGRAMMABLE

ALMOST EMPTY

FLAGS

t_CHMFRSF

HALF-FULL/

PROGRAMMABLE

ALMOST FULL

FLAGS

t_CHMFRSF

REGISTERED

OUTPUT

Delta39K-22

35

Delta39K™ ISR™

CPLD Family

PRELIMINARY

C Y 3 9 1 0 0 V 6 7 6 - 2 0 0 M B C

Cypress Semiconductor ID

Family Type

39 = Delta39K Family

Operating Conditions

Commercial

Industrial

0°C to +70°C

-40°C to +85°C

Gate Density

15=15k Usable Gates

30=30k Usable Gates

50=50k Usable Gates

165=165k Usable Gates

200=200k Usable Gates

250=250k Usable Gates

Package Type

N

= Plastic Quad Flat Pack (PQFP)

NT = Thermally Enhanced Quad Flat Pack (EQFP)

BG = Ball Grid Array (BGA)

BB = Fine-Pitch Ball Grid Array (FBGA)

1.0-mm Lead Pitch

MG = One Chip Solution - Ball Grid Array

MB = One Chip Solution - Fine Pitch Ball Grid Array

1.0-mm Lead Pitch

100=100k Usable Gates 350=350k Usable Gates

Operating Reference Voltage

V = 3.3V or 2.5V Supply Voltage

Z = 1.8V

Supply Voltage

Pin Count

144 = 144 Balls

208 = 208 Leads

256 = 256 Balls

388 = 388 Balls

484 = 484 Balls

676 = 676 Balls

Speed

250 = 250 MHz

222 = 222 MHz

200 = 200 MH

181 = 181 MHz

167 = 167 MHz

154 = 154 MHz

125 = 125 MHz

83 = 83 MHz

Delta39K Pin Table

Please refer to document titled “Delta39K Pin Tables” for pinouts of all the packages of all Delta39K family members. You can

access this document on the internet at: http://www.cypress.com/pld/datasheets.html.

Delta39K Part Numbers (Ordering Information)

Speed

(MHz)

Package

Name

Self-Boot

Solution

Operating

Range

Device

Ordering Code

Package Type

39K15

250

CY39015V208-250NTC

CY39015Z208-250NC

CY39015V144-250BBC

CY39015Z144-250BBC

CY39015V256-250BBC

CY39015Z256-250BBC

CY39015V256-250MBC

CY39015Z256-250MBC

CY39015V208-125NTC

CY39015Z208-125NC

CY39015V144-125BBC

CY39015Z144-125BBC

CY39015V256-125BBC

CY39015Z256-125BBC

CY39015V256-125MBC

CY39015Z256-125MBC

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

Commercial

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

125

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

36

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Delta39K Part Numbers (Ordering Information) (continued)

Speed

(MHz)

Package

Name

Self-Boot

Solution

Operating

Range

Device

Ordering Code

Package Type

39K15

125

CY39015V208-125NTI

CY39015Z208-125NI

CY39015V144-125BBI

CY39015Z144-125BBI

CY39015V256-125BBI

CY39015Z256-125BBI

CY39015V256-125MBI

CY39015Z256-125MBI

CY39015V208-83NTC

CY39015Z208-83NC

CY39015V144-83BBC

CY39015Z144-83BBC

CY39015V256-83BBC

CY39015Z256-83BBC

CY39015V256-83MBC

CY39015Z256-83MBC

CY39015V208-83NTI

CY39015Z208-83NI

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

Industrial

Commercial

Industrial

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

83

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

NT208

N208

208-Lead Plastic Quad Flat Pack

208-Lead Enhanced Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

CY39015V144-83BBI

CY39015Z144-83BBI

CY39015V256-83BBI

CY39015Z256-83BBI

CY39015V256-83MBI

CY39015Z256-83MBI

CY39030V208-222NTC

CY39030Z208-222NC

CY39030V144-222BBC

CY39030Z144-222BBC

CY39030V256-222BBC

CY39030Z256-222BBC

CY39030V256-222MBC

CY39030Z256-222MBC

CY39030V208-125NTC

CY39030Z208-125NC

CY39030V144-125BBC

CY39030Z144-125BBC

CY39030V256-125BBC

CY39030Z256-125BBC

CY39030V256-125MBC

CY39030Z256-125MBC

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

39K30

222

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

Commercial

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

125

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

37

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Delta39K Part Numbers (Ordering Information) (continued)

Speed

(MHz)

Package

Name

Self-Boot

Solution

Operating

Range

Device

Ordering Code

Package Type

39K30

125

CY39030V208-125NTI

CY39030Z208-125NI

CY39030V144-125BBI

CY39030Z144-125BBI

CY39030V256-125BBI

CY39030Z256-125BBI

CY39030V256-125MBI

CY39030Z256-125MBI

CY39030V208-83NTC

CY39030Z208-83NC

CY39030V144-83BBC

CY39030Z144-83BBC

CY39030V256-83BBC

CY39030Z256-83BBC

CY39030V256-83MBC

CY39030Z256-83MBC

CY39030V208-83NTI

CY39030Z208-83NI

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

Industrial

Commercial

Industrial

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

83

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

NT208

N208

208-Lead Plastic Quad Flat Pack

208-Lead Enhanced Quad Flat Pack

144-Lead Fine Pitch Ball Grid Array

256-Lead Fine Pitch Ball Grid Array

CY39030V144-83BBI

CY39030Z144-83BBI

CY39030V256-83BBI

CY39030Z256-83BBI

CY39030V256-83MBI

CY39030Z256-83MBI

CY39050V208-222NTC

CY39050Z208-222NC

CY39050V256-222BBC

CY39050Z256-222BBC

CY39050V388-222MGC

CY39050Z388-222MGC

CY39050V484-222MBC

CY39050Z484-222MBC

CY39050V208-125NTC

CY39050Z208-125NC

CY39050V256-125BBC

CY39050Z256-125BBC

CY39050V388-125MBC

CY39050Z388-125MBC

CY39050V484-125MBC

CY39050Z484-125MBC

BB144

BB256

MB256 256-Lead Fine Pitch Ball Grid Array

√

39K50

222

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

Commercial

BB256

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB484 484-Lead Fine Pitch Ball Grid Array

125

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

BB256

MG388 388-Lead Fine Pitch Ball Grid Array

MB484 484-Lead Fine Pitch Ball Grid Array

√

38

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Delta39K Part Numbers (Ordering Information) (continued)

Speed

(MHz)

Package

Name

Self-Boot

Solution

Operating

Range

Device

Ordering Code

Package Type

39K50

125

CY39050V208-125NTI

CY39050Z208-125NI

CY39050V256-125BBI

CY39050Z256-125BBI

CY39050V388-125MBI

CY39050Z388-125MBI

CY39050V484-125MBI

CY39050Z484-125MBI

CY39050V208-83NTC

CY39050Z208-83NC

CY39050V256-83BBC

CY39050Z256-83BBC

CY39050V388-83MGC

CY39050Z388-83MGC

CY39050V484-83MBC

CY39050Z484-83MBC

CY39050V208-83NTI

CY39050Z208-83NI

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

Industrial

Commercial

Industrial

BB256

MG388 388-Lead Fine Pitch Ball Grid Array

MB484 484-Lead Fine Pitch Ball Grid Array

√

83

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

BB256

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB484 484-Lead Fine Pitch Ball Grid Array

NT208

N208

208-Lead Plastic Quad Flat Pack

208-Lead Enhanced Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

CY39050V256-83BBI

CY39050Z256-83BBI

CY39050V388-83MGI

CY39050Z388-83MGI

CY39050V484-83MBI

CY39050Z484-83MBI

CY39100V208-200NTC

CY39100Z208-200NC

CY39100V256-200BBC

CY39100Z256-200BBC

CY39100V484-200BBC

CY39100Z484-200BBC

CY39100V388-200MGC

CY39100Z388-200MGC

CY39100V676-200MBC

CY39100Z676-200MBC

BB256

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB484 484-Lead Fine Pitch Ball Grid Array

39K100

200

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

484-Lead Fine Pitch Ball Grid Array

Commercial

BB256

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

39

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Delta39K Part Numbers (Ordering Information) (continued)

Speed

(MHz)

Package

Name

Self-Boot

Solution

Operating

Range

Device

Ordering Code

Package Type

39K100

125

CY39100V208-125NTC

CY39100Z208-125NC

CY39100V256-125BBC

CY39100Z256-125BBC

CY39100V484-125BBC

CY39100Z484-125BBC

CY39100V388-125MGC

CY39100Z388-125MGC

CY39100V676-125MBC

CY39100Z676-125MBC

CY39100V208-125NTI

CY39100Z208-125NI

CY39100V256-125BBI

CY39100Z256-125BBI

CY39100V484-125BBI

CY39100Z484-125BBI

CY39100V388-125MGI

CY39100Z388-125MGI

CY39100V676-125MBI

CY39100Z676-125MBI

CY39100V208-83NTC

CY39100Z208-83NC

CY39100V256-83BBC

CY39100Z256-83BBC

CY39100V484-83BBC

CY39100Z484-83BBC

CY39100V388-83MGC

CY39100Z388-83MGC

CY39100V676-83MBC

CY39100Z676-83MBC

CY39100V208-83NTI

CY39100Z208-83NI

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

484-Lead Fine Pitch Ball Grid Array

Commercial

BB256

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

484-Lead Fine Pitch Ball Grid Array

Industrial

BB256

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

39K100

83

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

484-Lead Fine Pitch Ball Grid Array

Commercial

BB256

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

256-Lead Fine Pitch Ball Grid Array

484-Lead Fine Pitch Ball Grid Array

Industrial

CY39100V256-83BBI

CY39100Z256-83BBI

CY39100V484-83BBI

CY39100Z484-83BBI

CY39100V388-83MGI

CY39100Z388-83MGI

CY39100V676-83MBI

CY39100Z676-83MBI

BB256

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

40

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Delta39K Part Numbers (Ordering Information) (continued)

Speed

(MHz)

Package

Name

Self-Boot

Solution

Operating

Range

Device

Ordering Code

Package Type

39K165

181

CY39165V208-181NTC

CY39165Z208-181NC

CY39165V484-181BBC

CY39165Z484-181BBC

CY39165V388-181MGC

CY39165Z388-181MGC

CY39165V676-181MBC

CY39165Z676-181MBC

CY39165V208-125NTC

CY39165Z208-125NC

CY39165V484-125BBC

CY39165Z484-125BBC

CY39165V388-125MGC

CY39165Z388-125MGC

CY39165V676-125MBC

CY39165Z676-125MBC

CY39165V208-125NTI

CY39165Z208-125NI

CY39165V484-125BBI

CY39165Z484-125BBI

CY39165V388-125MGI

CY39165Z388-125MGI

CY39165V676-125MBI

CY39165Z676-125MBI

CY39165V208-83NTC

CY39165Z208-83NC

CY39165V484-83BBC

CY39165Z484-83BBC

CY39165V388-83MGC

CY39165Z388-83MGC

CY39165V676-83MBC

CY39165Z676-83MBC

CY39165V208-83NTI

CY39165Z208-83NI

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

Commercial

Industrial

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

125

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

83

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

Commercial

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

Industrial

CY39165V484-83BBI

CY39165Z484-83BBI

CY39165V388-83MGI

CY39165Z388-83MGI

CY39165V676-83MBI

CY39165Z676-83MBI

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

41

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Delta39K Part Numbers (Ordering Information) (continued)

Speed

(MHz)

Package

Name

Self-Boot

Solution

Operating

Range

Device

Ordering Code

Package Type

39K200

167

CY39200V208-167NTC

CY39200Z208-167NC

CY39200V484-167BBC

CY39200Z484-167BBC

CY39200V388-167MGC

CY39200Z388-167MGC

CY39200V676-167MBC

CY39200Z676-167MBC

CY39200V208-125NTC

CY39200Z208-125NC

CY39200V484-125BBC

CY39200Z484-125BBC

CY39200V388-125MGC

CY39200Z388-125MGC

CY39200V676-125MBC

CY39200Z676-125MBC

CY39200V208-125NTI

CY39200Z208-125NI

CY39200V484-125BBI

CY39200Z484-125BBI

CY39200V388-125MGI

CY39200V676-125MBI

CY39200Z676-125MBI

CY39200V208-83NTC

CY39200Z208-83NC

CY39200V484-83BBC

CY39200Z484-83BBC

CY39200V388-83MGC

CY39200Z388-83MGC

CY39200V676-83MBC

CY39200Z676-83MBC

CY39200V208-83NTI

CY39200Z208-83NI

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

Commercial

Industrial

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

125

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

83

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

Commercial

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

NT208

N208

208-Lead Enhanced Quad Flat Pack

208-Lead Plastic Quad Flat Pack

484-Lead Fine Pitch Ball Grid Array

Industrial

CY39200V484-83BBI

CY39200Z484-83BBI

CY39200V388-83MGI

CY39200Z388-83MGI

CY39200V676-83MBI

CY39200Z676-83MBI

BB484

MG388 388-Lead Ball Grid Array

√

MG388 388-Lead Ball Grid Array

MB676 676-Lead Fine Pitch Ball Grid Array

42

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Serial Boot EEPROM^[13]Part Numbers (Ordering Information)

Speed

(MHz)

Package

Name

Operating

Device

Ordering Code

CY3LV010-10JC

CY3LV010-10JI

Package Type

Range

1Meg CPLD Configu-

ration EEPROM

15

10

J61

20-Lead Plastic Leaded Chip Carrier Commercial

20-Lead Plastic Leaded Chip Carrier

Industrial

Note:

13. See CY3LV010 data sheet for detailed architectural and timing information.

Package Diagrams

208-Lead Plastic Quad Flatpack (PQFP) N208

208-Lead Enhanced Quad Flat Pack (EQFP) NT208

51-85069-B

43

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Package Diagrams (continued)

388-Lead Ball Grid Array MG388

51-85103

44

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Package Diagrams (continued)

256-Ball Thin Ball Grid Array (17 x 17 x 1.6 mm) BB256/MB256

51-85108-A

45

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Package Diagrams (continued)

484-Ball Thin Ball Grid Array (23 x 23 x 1.6 mm) BB484/MB484

51-85124

46

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Package Diagrams (continued)

676-Ball FBGA (27 x 27 x 1.6 mm) BB676

51-85125

Mechanical drawings of 144FBGA will be available soon.

For package sizes and ball pitch see page 2.

47

Delta39K™ ISR™

CPLD Family

PRELIMINARY

REVISIONS MADE TO THE DATA SHEET

Change

#

Revision

Date

Revision Description

on the first page the no fanout or expander delays has been removed.

Multiple I/O standards supported

Simple Timing Model

1)

2)

Under

12/7/1999

12/7

Under the bullet

been listed

section on the first page the I/o standards have

High Performance CPLDs

On the first page, in the top right corner “

at FPGA densities”

CPLDs

” has been changed to “

3)

12/7

Development Software

4)

5)

On the front page all software bullets have been put under the heading

Warp 3

12/7

Hierarchy Navi-

On the front page under the bullet the following items have been deleted:

gator, Warp Galaxy GUI for Input, Mixed-mode Design Entry for VHDL and Schematics, Avail-

able for PC, Sun, and HP platforms for $4995,

ucts

Supports all Cypress Programmable Prod-

and

Delta39K Speed Bins

the 15, 30, 50, and 100 macrocell devices.

6)

7)

In the

table the 154 MHz speed bins have been removed from all devices in

12/7

Delta39K Speed Bins

In the

table the 125 MHz speed bins have been added to all devices in the

15, 30, 50, and 100 macrocell devices.

Delta39K Speed Bins

8)

In the

table a 250 MHz speed bin column has been added.

12/7

Device Package Offerings

9)

table the 352-FBGA heading has been changed to 352-BGA

General Description

10)

section the sentence “With devices ranging from 50,000 to 350,000

usable gates....” has been changed to “...”.....15,000 to 350,000 usable gates.”

General Description

11)

12)

In the

disabled” has been removed

section the sentence “On device power up, the bus hold feature is

12/7

Global Routing Description

In the

section the sentence “Figure 2 is a block diagram of the routing

channels and all of the LBC PIM interfaces required in the Delta39K architecture” has been changed

to “Figure 2 is a block diagram of the routing channels that interfaces with the Delta39K architecture.”

Global Routing Description

The last sentence of

LBC.” has been removed.

13)

“Figure 3 shows a block diagram of the Delta39K

12/7

14)

15)

16)

In Figure 3 the numbering of the Logic Blocks and Cluster memories in the diagram were changed.

Macrocell

12/7

Carry Chain Logic section under the

description

In the FIFO Configuration section the sentence “These clocks may be tied together for a single

operation or may run independently for synchronous....” has been changed to “...independently for

asynchronous...”

17)

18)

19)

20)

21)

22)

23)

Under the Dual Port Configuration, a section regarding Arbitration has been added

12/7

I/O Banks

Under

a block diagram of the device showing the location of the I/O banks has been added.

a table showing the I/O standards has been added.

Under

Block Diagram of Channel Memory Block

Figure 6,

Figure 8,

Figure 9,

in 12/7 Rev. deleted

Block Diagram of Dual Port Channel Memory

in 12/7 Rev. deleted

Block Diagram of FIFO Channel Memory Block

in 12/7 Rev. deleted

Switching Characteristics - Parameter Values

Cluster Memory Timing Parameter Description

Over the Operating Range table added prior to the

Over the Operating Range table.

Switching Characteristics Table

24)

25)

26)

Timing parameters added to

: tMCCCD and tSCS2PT

tADDMS

The following bullets were removed from the Delta39K features in the

no fanout delays, no expander delays, no additional delay through PIM, and no routing delays.

12/7

Channel Memory Timing:

Timing Parameter added to

Timing Model

in the section:

Timing Model paragraph

The caption was also changed to read

27)

The wording of the

was changed and now includes tMCS and tMCCO.

39K100

12/7

Switching Characteristics - Parameter Descriptions

28)

29)

table added

Channel Memory Timing Parameter Values

tADDMS added to

48

Delta39K™ ISR™

CPLD Family

PRELIMINARY

Change

#

Revision

Date

Revision Description

30)

Updated Isb spec and miscellaneous edits on first 3 pages; released first 3 pages as “Advance

Information” data sheet on 2/1/00 on the web and Cypress CD-ROM

3/4/2000

31)

32)

33)

34)

35)

36)

37)

38)

39)

40)

41)

42)

43)

44)

Updated the PLL arch. diagram and description to reflect recent arch. changes

Changed the name of “352-BGA” to “388-BGA”

3/4

5/11

Misc. text edits in the “Programming” section on p. 13

Reduced the Tj from 95C to 85C for comm and from 130C to 100C (p.14)

Vccjtag, Vcccnfg, Vccpll, Vccprg

Added

specs (p. 14)

Vdrint, Vdrio

specs (p. 14)

5 notes on Power-up sequence

(p. 15)

Added tCHMCHAA, tCHMFS, tCHMFH timing parameters

Lowered tCLMCYC3, tCHMCLK, tCHMFS, tCHMCYC3, tMACCHMS1

Edited the Timing waveforms to reflect consistency in parameter names

specs to meet design

Fixed 208-PQFP pinout diagram to reflect the latest pinout changes (p.34)

(352BGA -> 388BGA)

Part Numbers & Ordering info

Added part ordering info for 39K15, 39K30 and updated the rest

Removed the Pin Tables for all packages and all devices and created a new spec (#38-00982) titled

“Delta39K Pin Tables”

45)

46)

47)

48)

49)

50)

51)

52)

53)

54)

55)

56)

57)

58)

59)

60)

61)

62)

63)

64)

65)

66)

Added f

to the Family Members table (p.1)

5/11

5/23

5/11

5/14

5/15

6/23

7/28

MAX2

Increased Typical gate count per new formula (p.1)

Added package dimensions to “Device package offering” Table (p.2)

Miscellaneous edits in the “General Description” section (p. 4-13)

Added t

parameter (p. 15)

RECONFIG

Split the max. rating for VCC to ground potential for 39kZ and 39KV device (p.14)

Added t , t , parameters for NoBL/ZBT compatibility as per RHR’s 5/12/00 memo

CHZ CLZ

Put values for t

, t

parameter as per RHR’s 5/12/00 memo

SCS2PT MCCD

Modified tMCSPT, tMCHPT, tMCCOPT specs as per RHR’s 5/12/00 memo

Reduced t

specs as per RHR’s 5/12/00 memo

CHMMACS

Increased t

MACCHMS

Added t

parameter as per RHR’s 5/12/00 memo

CHMFRDV

Increased tCLMHD, tCHMHD, tCHMS as per RHR’s 5/12/00 memo

Added t (to replace tADDMS - the arbitration param) as per RHR’s 5/12/00 memo

CHMBA

Increased tCHMCHAA, tCHMMACS1, tMACCHMS2 as per RHR’s 5/12/00 memo

Changed name of tCHMRS to tCHMFRS and tCHMRSF to tCHMFRSF to indicate FIFO params

added Serial Boot EEPROM Part Numbers (p. 43)

removed package diagrams for all packages

Added “I/O standards delay adjustment table” (p.21)

Updated timing waveforms for Cluster memory & FIFO

Miscellaneous edits in the “General Description” section (p. 4-13)

Updated “I/O standards delay adjustment table” (p.21)

NoBL, PIM, Spread Aware,

Corporation.

, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, and Delta39K are trademarks of Cypress Semiconductor

Warp

ZBT is a trademark of IDT. QDR is a trademark of Micron, IDT, and Cypress Semiconductor Corporation.

SpeedWave, and ViewDraw are trademarks of ViewLogic.

Document #: 38-00830-B

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	CY39100Z256-125BBI
厂家：	CYPRESS
描述：	Loadable PLD, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256 输入元件可编程逻辑
文件：	总49页 (文件大小：715K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY39100Z256-125BBI [CYPRESS]

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