CY3LV512-10JC [CYPRESS]
512K / 1 Mbit CPLD Boot EEPROM; 512K / 1兆CPLD引导EEPROM
| 型号： | CY3LV512-10JC |
| 厂家： | 
CYPRESS |
| 描述： | 512K / 1 Mbit CPLD Boot EEPROM |
| 文件： | 总9页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY3LV512/010
512K / 1 Mbit CPLD Boot EEPROM
• Cascadable Read-Back to Support Higher-density CPLDs
• Low-power CMOS EEPROM Process
• Available in PLCC Package (Pin Compatible Across
Product Family)
• Operate at 3.3V VCC
• System-friendly READY Pin
• Low-power Standby Mode
Features
• EE Reprogrammable 524,288 x 1- and 1,048,576 x 1-bit
Serial Memories Designed to Store Configuration Data for
Complex Programmable Logic Devices (CPLDs)
• In-SystemProgrammableviatwo-wireBus usingCypress’s
CYDH2200E Programming Kits
• Simple Interface to SRAM-based CPLDs
• Compatible with Cypress Delta39K™ & Quantum38K™
CPLDs
Block Diagram
CEO (A2)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03002 Rev. *A
Revised December 28, 2002
PRELIMINARY
CY3LV512/010
Functional Description
Controlling the CY3LV CPLD Boot PROMs
During Configuration
The CY3LV512/010 (high-density CY3LV Series) CPLD boot
EEPROMs provide an easy-to-use, cost-effective configura-
tion memory for Complex Programmable Logic Devices. The
CY3LV Series is packaged in the popular 20-pin PLCC. These
devices support a system-friendly READY pin, which signifies
a “good” power level to the CPLD and can be used to ensure
reliable system power-up.
Most connections between the CPLD device and the CY3LV
boot PROM are simple and self-explanatory. Figure 1 shows
the five signal interface required between the
Delta39K/Quantum38K CPLD and the CY3LV boot PROM
device.
• The DATA output of the boot PROM drives DATA input of
the CPLD
• The master CPLD CCLK output drives the CLK input of the
boot PROM
• The CPLD CCE pin drives the CE input of the boot PROM
• The RESET/OE input of the boot PROM is driven by the
CPLD RESET pin
The CY3LV Series boot PROMs can be programmed with in-
dustry-standard programmers or Cypress’s CYDH2200E
CPLD boot PROM programming kit. Please refer to the data
sheet “CYDH2200E CPLD Boot PROM Programming Kit” for
details.
CPLD Master Serial Mode Summary
• The READY pin of the boot PROM is connected to the RE-
CONFIG pin of the CPLD
The I/O and logic functions of the CPLD and their associated
interconnections are established by loading configuration data
(bitstream) into the CPLD. This configuration data is loaded
either automatically upon power-up, or upon issuing JTAG-
command. The configuration data is stored in the internal
Flash memory (Self-Boot packages only) or in the external
CPLD boot PROM memory. This data is loaded from the ap-
propriate memory depending on the state of the CPLD mode
select pin (MSEL).
The READY pin is available as an open-collector indicator of
the device’s RESET status; it is driven LOW while the device
is in its POWER-ON RESET cycle and released
(three-stated) when the cycle is complete. The rising edge of
the READY (hence RECONFIG) signal causes the CPLD to
start configuring. The CONFIG_DONE, CCE and RESET out-
put of the CPLD are set LOW, CCLK is activated and CPLD
starts receiving configuration data on the DATA pin. After all
the configuration data is shifted in, the CPLD device deacti-
vates the CCLK and sets CCE, RESET and CONFIG_DONE
HIGH.
In Master Serial mode (when MSEL=1), the CPLD automati-
cally loads the configuration program from an external memo-
ry i.e., CY3LV CPLD boot PROM. These PROMs have been
designed for compatibility with the Master Serial Mode. This
document discusses the interface between Cypress’s SRAM
based CPLDs (Quantum38K and Delta39K) and CY3LV
PROMs.
A HIGH level on the RESET/OE input — during CPLD reset
— clears the boot PROM’s internal address pointer and sub-
sequent reconfiguration starts at the beginning.
The CEO output of any CY3LV drives the CE input of the next
CY3LV in a cascade chain of EEPROMs.
For more details on the other modes of configuration of these
CPLDs please refer to the application note titled “Configuring
Delta39K/Quantum38K.”
SER_EN must be connected to VCC, (except during In-System
Programming).
VCC
VCCIO
3.3V
V
VCCCNFG
VCCJTAG CCIO VCCPLL
4.7K
Ω
VCC
VCCPRG
SER_EN
VCC
DATA
Reset/OE
CE
DATA
Reset
CCE
1KΩ
0.1µF
DELTA39K/
QUANTUM38K
CCLK
MSEL
CLK
GND
READY
TCLK
TMS
TDI
CY3LV512/010
Reconfig
Config_Done
TDO
GND
1µF
Figure 1. Interface between Delta39K/Quantum38K CPLD and CY3LV boot PROM
Document #: 38-03002 Rev. *A
Page 2 of 9
PRELIMINARY
CY3LV512/010
Note:
CY3LV Series RESET Polarity
Currently, 3 revisions of Delta39K100 and 2 revisions of
Quantum38K100 devices are available marked as
CY39100Vxxx, CY39100VxxxA, and CY39100VxxxB,
CY38100Vxxx, and CY38100VxxxB. Figure 1 set-up repre-
sents the interface between CY39100VxxxB/CY38100VxxxB
and CY3LV device. To get details on interface between other
versions and CY3LV please refer to the application note titled
“Configuring Delta39K/Quantum38K.”
The CY3LV Series CPLD boot PROMs allow the user to pro-
gram the reset polarity as either RESET/OE or
RESET/OE.Cypress’s SRAM based CPLDs (Delta39K and
Quantum38K) require the RESET pin to be programmed ac-
tive-High, i.e. as RESET/OE. CY3LV boot PROMs are
shipped from the factory with the reset polarity programmed
active-High. This polarity can be verified using industry stan-
dard programmers or Cypress’s CYDH2200E boot PROM pro-
gramming kit.
Setup in Figure 1 also represents the interface between all
other devices in Delta39K/Quantum38K families and CY3LV
boot PROMs.
Note: Every time the boot PROM is reprogrammed, care
should be taken to select the reset polarity to be “HIGH” pro-
grammer software.
Cascading CY3LV CPLD boot PROMs
Programming Mode
For future CPLDs requiring larger configuration memories,
cascaded CPLD boot PROMs provide additional memory.
The programming mode is entered by bringing SER_EN LOW.
In this mode the chip can be programmed by the two-wire se-
rial bus. The programming is done at VCC (3.3V nominal) sup-
ply only. The CY3LV parts are read/write at 3.3V nominal.
As the last bit from the first boot PROM is read, the clock signal
to the boot PROM asserts its CEO output LOW and disables
its DATA line driver. The second boot PROM recognizes the
Low level on its CE input and enables its DATA output.
Standby Mode
After configuration is complete, the address counters of all
cascaded boot PROMs are reset if the RESET/OE on each
boot PROM is driven to its active (HIGH) level.
The CY3LV enters a low-power standby mode whenever CE
is asserted High. In this mode, the boot PROM consumes less
than 0.5 mA of current at 3.3V with CMOS level inputs. The
output remains in a high-impedance state regardless of the
state of the OE input.
Document #: 38-03002 Rev. *A
Page 3 of 9
PRELIMINARY
CY3LV512/010
.
Table 1. Pin Configurations
20-pin
PLCC
Name
I/O
Description
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bidirectional pin for
programming.
4
5
CLK
I
I
Clock input. Used to increment the internal address and bit counter for reading and program-
ming.
WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during CPLD loading
operations.
6
RESET /
OE
I
RESET/Output Enable input (when SER_EN is HIGH). A LOW level on both the CE and
RESET/OE inputs enables the data output driver. A HIGH level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. Delta39K/Quantum38K CPLDs require this pin to be programmed as
RESET/OE hence this document describes the pin as RESET/OE.
7
8
WP2
CE
I
I
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during CPLD loading
operations.
Chip Enable input. Used for device selection. A LOW level on both CE and OE enables the
data output driver. A HIGH level on CE disables both the address and bit counters and forces
the device into a low-power standby mode. Note that this pin will not enable/disable the device
in the two-wire Serial Programming Mode (i.e., when SER_EN is LOW).
10
14
GND
CEO
Ground pin. A 0.1 µF decoupling capacitor between VCC and GND is recommended
O
Chip Enable Output. This signal is asserted LOW on the clock cycle following the last bit read
from the memory. It will stay LOW as long as CE and OE are both LOW. It will then follow CE
until OE goes HIGH. Thereafter, CEO will stay HIGH until the entire EEPROM is read again.
A2
I
O
I
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is LOW).
15
17
20
READY
SER_EN
VCC
Open collector reset state indicator. Driven LOW during power-up reset, released when
power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used).
Serial enable must be held High during CPLD loading operations. Bringing SER_EN LOW
enables the two-wire Serial Programming Mode.
+3.3V power supply pin.
Pin Configurations
CLK
WP1
4
5
6
7
8
18 NC
17 SER_EN
16 NC
RESET/OE
WP2
15 READY
14 CEO (A2)
CE
Document #: 38-03002 Rev. *A
Page 4 of 9
PRELIMINARY
CY3LV512/010
Voltage on Any Pin
Maximum Ratings
with Respect to Ground......................... –0.1V to VCC + 0.5V
Supply Voltage (VCC)......................................–0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16in.) ...........260°C
ESD (RZAP = 1.5K, CZAP = 100 pF) ............................ 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Temperature...............................–55°C to +125°C
Storage Temperature .................................–65°C to +150°C
Operating Range [1]
Range
Commercial
Ambient Temperature
0°C to + 70°C
Junction Temperature
0°C to + 90°C
CY3LV512/010 (VCC
)
3.3V ± 0.3V
Industrial
Military
–40°C to + 85°C
–55°C to + 125°C
–40°C to + 125°C
–55°C to + 130°C
3.3V ± 0.3V
3.3V ± 0.3V
3.3V Device Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Min,
Max,
Unit
High-level input voltage
Low-level input voltage
2.0
VCC
V
VIL
0
0.8
0.4
0.4
V
V
Commercial
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level output voltage (IOH = –2.5 mA)
Low-level output voltage (IOL = +3 mA)
High-level output voltage (IOH = –2 mA)
Low-level output voltage (IOL = +3 mA)
High-level output voltage (IOH = –2 mA)
Low-level output voltage (IOL = +2.5 mA)
Supply current, active mode
2.4
V
2.4
2.4
V
Industrial
Military
V
V
0.4
5
V
mA
µA
µA
µA
Input or output leakage current (VIN = VCC or GND)
Supply current, standby mode
–10
10
Commercial
100
100
ICCS
Industrial/Military
Document #: 38-03002 Rev. *A
Page 5 of 9
PRELIMINARY
CY3LV512/010
.
Switching Characteristics for CY3LV512/010 (3.3V) Over the Operating Range
Commercial
Industrial
Parameter
Description
Min.
Max.
50
Min.
Max.
Unit
ns
[2]
TOE
OE to Data Delay
CE to Data Delay
CLK to Data Delay
55
60
60
[2]
TCE
55
ns
[2]
TCAC
55
ns
TOH
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
0
0
ns
[3]
TDF
50
50
ns
TLC
CLK Low Time
25
25
30
0
25
25
35
0
ns
THC
CLK High Time
ns
TSCE
THCE
THOE
FMAX
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time from CLK (to guarantee proper counting)
OE High Time (guarantees counter is reset)
MAX Input Clock Frequency
ns
ns
25
15
25
10
ns
MHz
Switching Characteristics for CY3LV512/010 (3.3V) when Cascading Over the Operating Range
Commercial
Min. Max.
Industrial
Parameter
Description
CLK to Data Float Delay
Min.
Max.
Unit
ns
[3]
tCDF
50
50
35
35
50
55
40
35
[2]
tOCK
CLK to CEO Delay
ns
[2]
tOCE
CE to CEO Delay
ns
[2]
tOOE
RESET/OE to CEO Delay
MAX Input Clock Frequency
ns
FMAX
12.5
10
MHz
3.3V Ordering Information
Package
Name
Operating
Range
Memory Size
Ordering Code
Package Type
1M
CY3LV010-10JC
CY3LV010-10JI
CY3LV512-10JC
CY3LV512-10JI
20J
20J
20J
20J
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
Commercial
Industrial
512K
Commercial
Industrial
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
Document #: 38-03002 Rev. *A
Page 6 of 9
PRELIMINARY
CY3LV512/010
AC Characteristics
AC Characteristics when Cascading
Document #: 38-03002 Rev. *A
Page 7 of 9
PRELIMINARY
CY3LV512/010
Package Diagrams: 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
Document #: 38-03002 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY3LV512/010
Document Title: CY3LV512/010 512K/1 Mbit CPLD BOOT EEPROM DATASHEET (Preliminary)
Document Number: 38-03002
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
106080
122216
Description of Change
08/07/01
12/28/02
RN
New Data Sheet
Power up requirements added to Operating Range Information
*A
RBI
Document #: 38-03002 Rev. *A
Page 9 of 9
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