CY62127DV18L-55ZI [CYPRESS]
1M (64K x 16) Static RAM; 1M ( 64K ×16 )静态RAM型号: | CY62127DV18L-55ZI |
厂家: | CYPRESS |
描述: | 1M (64K x 16) Static RAM |
文件: | 总13页 (文件大小:217K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
1M (64K x 16) Static RAM
BLE are HIGH. The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected Chip En-
able 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH) or during a write oper-
ation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2)
HIGH and WE LOW).
Features
• Very high speed: 55 ns
• Voltage range: 1.65V to 1.95V
• Ultra-low active power
— Typical active current: 0.5 mA @ f = 1 MHz
— Typical active current: 2.5 mA @ f = fMAX
• Ultra-low standby power
• EasymemoryexpansionwithCE1, CE2 andOE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
• Packages offered in a 48-ball FBGA and a 44-pin TSOP
Type II
Functional Description[1]
Reading from the device is accomplished by taking Chip En-
able 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from mem-
ory will appear on I/O8 to I/O15. See the truth table at the back
of this data sheet for a complete description of read and write
modes.
The CY62127DV18 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The device can be put into standby mode reducing power con-
sumption by more than 99% when deselected Chip Enable 1
(CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and
Logic Block Diagram
DATA IN DRIVERS
A10
A 9
A 8
A 7
A 6
A 5
A 4
A 3
A 2
64K × 16
RAM ARRAY
2048 x 32 x 16
I/O0–I/O7
I/O8–I/O15
A 1
A 0
COLUMN DECODER
BHE
WE
CE
2
CE
1
OE
BLE
Po we r-d o wn
Circ uit
CE
2
BHE
BLE
CE
1
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05226 Rev. **
Revised September 24, 2002
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Pin Configuration[2]
TSOP II (Forwa rd )
FBGA (Top Vie w)
Top Vie w
1
2
3
4
5
6
44
1
A4
A3
A2
A1
A0
CE 1
I/O1
I/O2
I/O3
I/O4
VCC
A5
A6
A7
OE
BHE
BLE
43
42
41
40
39
38
2
3
4
5
6
A
A
A
2
BLE OE
I/O
CE 2
0
A
B
C
1
A
A
4
BHE
CE 1 I/O
3
0
8
I/O16
I/O15
I/O14
I/O13
7
A
A
6
I/O9 I/O
I/O
I/O
10
5
1
2
37
36
35
34
33
8
9
VC C
V
A
7
I/O
I/O
3
DNU
DNU
D
E
F
10
11
12
13
S S
11
V
SS
V
VCC
I/O12
I/O11
I/O10
I/O9
CE2
A8
A9
A10
A11
VS S
SS
V
CC
I/O
I/O
4
DNU
12
32
I/O5
I/O6
I/O7
I/O8
31
30
29
28
14
15
16
I/O
A
A
I/O
5
I/O14
I/O
13
14
15
6
WE 17
A
A
DNU
G
H
I/O
WE I/O7
18
27
26
25
A15
12
13
15
19
A14
A13
A12
20
21
22
A
A
A
A
DNU
11
DNU
9
10
8
24
23
DNU
NU
Note:
2. DNU pins are to be connected to VSS or left open.
Document #: 38-05226 Rev. **
Page 2 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
DC Input Voltage[3] ................................ −0.2V to VCC + 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Storage Temperature .................................–65°C to +150°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Latch-up Current .................................................... > 200 mA
Supply Voltage to Ground Potential
Operating Range
.........................................................−0.2V to VCCMAX + 0.2V
DC Voltage Applied to Outputs
in High-Z State[3]....................................−0.2V to VCC + 0.2V
Ambient
Range
Temperature (TA)
VCC
Industrial
−40°C to +85°C
1.65V to 1.95V
Product Portfolio
Power Dissipation
f = fMAX
Operating, Icc (mA)
V
CC Range(V)
f = 1 MHz
Standby, ISB2 (µA)
Speed
(ns)
Product
Min.
Typ.[4]
Max.
Typ.[4]
Max.
Typ.[4]
Max.
Typ.[4]
Max.
CY62127DV18L
CY62127DV18LL
1.65
1.8
1.95
55
55
0.5
1
2.5
5
5
0.5
3
2
2.5
0.5
Notes:
3. VIL(min.) = -2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 38-05226 Rev. **
Page 3 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
DC Electrical Characteristics (Over the Operating Range)
CY62127DV18-55
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min.
Typ.[4]
Max.
Unit
V
IOH = −0.1 mA
VCC = 1.65V
VCC = 1.65V
1.4
VOL
IOL = 0.1 mA
0.2
V
VIH
1.4
VCC
0.2
+
V
VIL
IIX
Input LOW Voltage
–0.2
–1
0.4
+1
+1
5
V
Input Leakage Current
Output Leakage Current
GND < VI < VCC
µA
µA
mA
IOZ
ICC
GND < VO < VCC, Output Disabled
–1
VCC Operating Supply Cur- f = fMAX = 1/tRC
rent
Vcc=1.95V, IOUT
= 0mA, CMOS
level
2.5
0.5
f = 1 MHz
1
ISB1
Automatic CE Power-down CE1 > VCC − 0.2V, CE2 < 0.2V,
L
0.5
0.5
3
2
µA
µA
Current − CMOS Inputs
VIN > VCC − 0.2V, VIN < 0.2V, f =
fMAX (Address and Data Only), f
= 0 (OE, WE, BHE and BLE)
LL
ISB2
Automatic CE Power-down CE1 > VCC − 0.2V, CE2 < 0.2V,
L
0.5
0.5
3
2
Current − CMOS Inputs
VIN > VCC − 0.2V or VIN < 0.2V, f
LL
= 0, VCC=1.95V
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
6
8
pF
pF
COUT
Thermal Resistance
Parameter
Description
Test Conditions
BGA
Unit
θJA
Thermal Resistance (Junction to
Ambient)[5]
Still Air, soldered on a 3 x 4.5 inch, two-layer
printed circuit board
55
C/W
θJC
Thermal Resistance (Junction to
Case)[5]
16
C/W
Note:
5. Tested initially and after any design or proces changes that may affect these parameters.
Document #: 38-05226 Rev. **
Page 4 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC Typ
90%
90%
UTPUT
10%
10%
GND
R2
CL = 30 p F
Rise Tim e :
1 V/ ns
Fa ll Tim e :
1 V/ ns
INCLUDING
JIG AND
SCOPE
Eq uiva le nt to :
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Pa ra m e te rs
1.8V
1350 0
1080 0
6000
UNIT
Ω
R 1
R 2
Ω
R TH
VTH
Ω
0.80
V
Data Retention Characteristics
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.[4]
Max.
1.95
1
Unit
V
1
VCC = 1V, CE1 > VCC − 0.2V, CE2 <
0.2V, VIN > VCC − 0.2V or VIN < 0.2V
L
µA
LL
TBD
[5]
tCDR
Chip Deselect to Data Reten-
tion Time
0
ns
ns
[6]
tR
Operation Recovery Time
tRC
Data Retention Waveform[7]
DATA RETENTION MODE
VCC(m in.)
tR
VDR > 1.0V
V
CC
VCC(m in.)
tCDR
CE1 o r
.
BHE BLE
o r
CE
2
Notes:
6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
.
7. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05226 Rev. **
Page 5 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
[8]
Switching Characteristics (Over the Operating Range)
CY62127DV18-55
Parameter
Read Cycle
tRC
Description
Min.
Max.
Unit
Read Cycle Time
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
tOHA
Data Hold from Address Change
CE1 LOW or CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[9]
OE HIGH to High-Z[9,11]
CE1 LOW or CE2 HIGH to Low-Z[9]
CE1 HIGH or CE2 LOW to High-Z[9,11]
CE1 LOW or CE2 HIGH to Power-up
CE1 HIGH or CE2 LOW to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low-Z[9]
10
tACE
55
25
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
20
20
tPD
55
55
tDBE
[10]
tLZBE
5
tHZBE
Write Cycle[12]
tWC
BLE/BHE HIGH to High-Z[9,11]
20
Write Cycle Time
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW or CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
tPWE
tBW
40
45
25
0
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9,11]
WE HIGH to Low-Z[9]
tSD
tHD
tHZWE
tLZWE
20
10
Notes:
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
10. If both byte enables are toggled together, this value is 10 ns.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate a
Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the Write.
Document #: 38-05226 Rev. **
Page 6 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
ATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
t RC
CE
1
t PD
tHZCE
CE
2
tACE
BHE
/
BLE
t DBE
t HZBE
t LZBE
OE
t HZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
ICC
ISB
tPU
V
CC
SUPPLY
CURRENT
50%
50%
Notes:
13. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH
14. WE is HIGH for Read cycle.
.
15. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05226 Rev. **
Page 7 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled) [12, 16, 17, 18]
t WC
ADDRESS
tSCE
CE
1
CE
2
tAW
tHA
t SA
t PWE
WE
tBW
BHE/BLE
OE
tSD
DATA
tHD
ATA I/ O
VALID
DON’T CARE
IN
tHZOE
Write Cycle No. 2 (CE1 or CE2 Controlled) [12, 16, 17, 18]
tWC
ADDRESS
t SCE
CE
CE
1
2
t SA
tAW
t HA
t PWE
WE
tBW
BHE /BLE
OE
tSD
t HD
VALID
DATA I/ O
DATA
IN
DON’T CARE
tHZOE
Notes:
16. Data I/O is high-impedance if OE = VIH
17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
.
18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05226 Rev. **
Page 8 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tSD
tHD
DON’T CARE
DATA I/ O
DATAIN VALID
tLZWE
tHZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17]
t WC
ADDRESS
CE 1
CE 2
t SCE
t AW
t HA
tBW
BHE/ BLE
WE
t SA
t PWE
t SD
DATA
t HD
DATA I/ O
DON’T CARE
VALID
IN
Document #: 38-05226 Rev. **
Page 9 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inp ut / Outp uts
Hig h Z
Mod e
Powe r
De se le c t/ Po we r-d o wn
De se le c t/ Po we r-d o wn
De se le c t/ Po we r-d o wn
Re a d
Sta nd b y(I SB
Sta nd b y(I SB
Sta nd b y(I SB
)
)
)
X
L
X
X
X
X
Hig h Z
X
X
X
X
H
H
Hig h Z
L
H
H
L
L
L
Da ta Out(I/ O0
Da ta Out(I/ O0
Hig h Z (I/ O8
Hig h Z (I/ O0
Da ta Out(I/ O8
–
I/ O15)
Ac tive(I CC
)
)
L
H
H
L
H
L
–
–
I/ O7);
I/ O15)
Re a d
Ac tive(I CC
L
H
H
L
L
H
–
–
I/ O7);
I/ O15)
Re a d
Ac tive(I CC
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
L
H
H
L
L
L
L
Hig h Z
Hig h Z
Hig h Z
Outp ut Disa b le d
Outp ut Disa b le d
Outp ut Disa b le d
Write
Ac tive(I CC
Ac tive(I CC
Ac tive(I CC
Ac tive(I CC
Ac tive(I CC
)
)
)
)
)
Da ta In (I/ O0
Da ta In (I/ O0
Hig h Z (I/ O8
Hig h Z (I/ O0
Da ta In (I/ O8
–
I/ O15)
L
–
–
I/ O7);
I/ O15)
Write
L
H
L
X
L
H
–
–
I/ O7);
I/ O15)
Write
Ac tive(I CC
)
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY62127DV18L-55BVI
CY62127DV18LL-55BVI
CY62127DV18L-55ZI
CY62127DV18LL-55ZI
Name
BV48A
BV48A
Z44
Package Type
55
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
44-lead TSOP Type II
Industrial
Z44
44-lead TSOP Type II
Document #: 38-05226 Rev. **
Page 10 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Package Diagrams
48-ball VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
Document #: 38-05226 Rev. **
Page 11 of 13
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
44-pin TSOP II Z44
51-85087-A
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05226 Rev. **
Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document History Page
Document Title: CY62127DV18 MoBL2® 1M (64K x 16) Static RAM
Document Number: 38-05226
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
118006
10/01/02
CDY
New Data Sheet
Document #: 38-05226 Rev. **
Page 13 of 13
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