CY62127DV30_09 [CYPRESS]
1-Mb (64K x 16) Static RAM; 1 MB （ 64K ×16 ）静态RAM
| 型号： | CY62127DV30_09 |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mb (64K x 16) Static RAM |
| 文件： | 总11页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62127DV30
1-Mb (64K x 16) Static RAM
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O0 through I/O15) are placed in a high-impedance state
when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH) or during a write operation (CE
LOW and WE LOW).
Features
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62127BV
• Ultra-low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A15).
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Available in Pb-Free and non Pb-Free 48-ball FBGA and
a 44-lead TSOP Type II packages
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
Functional Description[1]
The CY62127DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
description of read and write modes
.
Logic Block Diagram
DATA IN DRIVERS
10
A10
A9
A8
A7
A6
A5
A4
A3
A2
64K x 16
RAM Array
2048 x 512
I/O0–I/O7
I/O8–I/O15
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
Power -Down
Circuit
BHE
BLE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05229 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 19, 2006
[+] Feedback
CY62127DV30
Product Portfolio
Power Dissipation
Operating, ICC (mA)
VCC Range (V)
Min. Typ. Max.
f = 1 MHz
f = fMAX
Max.
13
Standby ISB2 (µA)
Speed
(ns)
Product
Typ[4]
Max.
1.5
Typ.[4]
6.5
Range
Ind’l
Ind’l
Ind’l
Auto
Ind’l
Ind’l
Ind’l
Typ.[4]
Max.
CY62127DV30L
CY62127DV30LL
CY62127DV30L
2.2
3.0
3.6
45
45
55
0.85
0.85
0.85
1.5
5
4
1.5
6.5
13
1.5
2.2
3.0
3.6
1.5
5
10
1.5
5
1.5
15
4
2.2
2.2
3.0
3.0
CY62127DV30LL
CY62127DV30L
CY62127DV30LL
3.6
3.6
55
70
70
0.85
0.85
0.85
1.5
1.5
1.5
5
5
5
10
10
10
1.5
1.5
5
1.5
4
Pin Configurations[2, 3]
FBGA (Top View)
TSOP II (Forward)
Top View
1
2
4
3
5
6
44
1
A
A
5
4
A
A
2
A
NC
I/O
OE
BLE
0
1
A
B
C
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
A
A
I/O BHE
8
OE
A
CE
I/O
4
3
0
1
BHE
BLE
I/O
A
0
CE
A
A
6
I/O I/O
I/O
2
5
10
1
9
I/O
7
0
15
37
36
35
34
33
I/O
I/O
8
I/O
I/O
1
2
14
13
12
9
VCC
VSS
NC
A
7
V
I/O
I/O
3
D
E
F
SS
11
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
DNU NC
V
CC
I/O
I/O
V
V
12
4
CC
32
I/O
I/O
I/O
4
5
6
7
11
10
31
30
29
28
I/O
I/O
I/O
14
15
16
A
A
15
I/O
I/O
5
I/O
I/O
6
14
13
14
I/O
9
8
I/O
WE 17
NC
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
18
27
26
25
A
A
8
15
19
A
A
9
14
A
20
21
22
A
11
A
A
A
13
A
10
NC
NC
10
9
11
8
A
A
24
23
12
NC
DNU
Notes:
2. NC pins are not connected to the die.
3. Pin #23 of TSOP II and E3 ball of FBGA are DNU, which have to be left floating or tied to Vss to ensure proper application. (Expansion Pins on FBGA Package:
E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
CC
, T = 25°C.
A
CC(typ)
Document #: 38-05229 Rev. *H
Page 2 of 11
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CY62127DV30
DC Input Voltage[5] ................................ −0.3V to VCC + 0.3V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
......................................................................... −0.3V to 3.9V
[6]
Range
Industrial
Automotive
Ambient Temperature (TA)
–40°C to +85°C
VCC
2.2V to 3.6V
2.2V to 3.6V
DC Voltage Applied to Outputs
in High-Z State[5] ....................................−0.3V to VCC + 0.3V
–40°C to +125°C
DC Electrical Characteristics (Over the Operating Range)
–45
–55
–70
Parameter Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Min Typ.[4] Max. Unit
VOH
VOL
VIH
Output HIGH 2.2 < VCC < 2.7 IOH = −0.1 mA 2.0
2.0
2.4
2.0
2.4
V
V
V
Voltage
2.7 < VCC < 3.6 IOH = −1.0 mA 2.4
Output LOW
Voltage
2.2 < VCC < 2.7 IOL = 0.1 mA
2.7 < VCC < 3.6 IOL = 2.1 mA
2.2 < VCC < 2.7
0.4
0.4
0.4
0.4
0.4
0.4
Input HIGH
Voltage
1.8
2.2
VCC 1.8
+ 0.3
VCC 1.8
+ 0.3
VCC
+ 0.3
2.7 < VCC < 3.6
VCC 2.2
+ 0.3
VCC 2.2
+ 0.3
VCC
+ 0.3
VIL
Input LOW
Voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
−0.3
−0.3
0.6 −0.3
0.8 −0.3
0.6 −0.3
0.8 −0.3
0.6
0.8
V
IIX
Input Leakage GND < VI < VCC
Current
Ind’l −1
Auto
+1
−1
−4
−1
−4
+1
+4
+1
+4
−1
+1 µA
µA
IOZ
Output
GND < VO < VCC, Output Ind’l −1
Disabled
+1
−1
+1 µA
µA
Leakage
Current
Auto
ICC
VCC Operating f = fMAX = 1/tRC VCC = 3.6V,
6.5
13
5
10
5
10 mA
Supply Current
IOUT = 0 mA,
CMOS level
f = 1 MHz
0.85 1.5
0.85 1.5
0.85 1.5
ISB1
Automatic CE CE > VCC − 0.2V,
L
Ind’l
1.5
5
1.5
1.5
1.5
5
15
4
1.5
5
µA
µA
Power-down
Current—
VIN > VCC − 0.2V, VIN
Auto
< 0.2V,
CMOS Inputs f = fMAX (Address and LL
1.5
4
1.5
4
Data Only),
f = 0 (OE, WE, BHE
and BLE)
ISB2
Automatic CE CE > VCC − 0.2V,
L
Ind’l
1.5
1.5
5
4
1.5
1.5
1.5
5
15
4
1.5
1.5
5
4
Power-down
Current—
V
IN > VCC − 0.2V or
Auto
VIN < 0.2V,
CMOS Inputs f = 0, VCC = 3.6V
LL
Capacitance[7]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
8
8
COUT
pF
Notes:
5. V
= −2.0V for pulse durations less than 20 ns., V
= Vcc+0.75V for pulse durations less than 20 ns.
IH(max.)
IL(min.)
6. Full device operation requires linear ramp of V from 0V to V
7. Tested initially and after any design or proces changes that may affect these parameters.
& V must be stable at V
for 500 µs.
CC
CC(min)
CC
CC(min)
Document #: 38-05229 Rev. *H
Page 3 of 11
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CY62127DV30
Thermal Resistance[7]
Parameter
Description
Test Conditions
FBGA
55
TSOP II
76
Unit
°C/W
°C/W
θJA
θJC
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
Thermal Resistance (Junction to Case)
12
11
AC Test Loads and Waveforms[8]
R1
VCC
ALL INPUT PULSES
90%
10%
VCC
OUTPUT
90%
10%
R2
GND
Rise Time = 1 V/ns
50 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.5V (2.2V - 2.7V)
16600
3.0V (2.7V - 3.6V)
Unit
Ω
R1
R2
1103
1554
645
15400
Ω
RTH
VTH
8000
Ω
1.20
1.75
V
Data Retention Characteristics
Parameter
VDR
Description
Conditions
Min.
Typ.[4]
Max.
Unit
V
VCC for Data Retention
Data Retention Current
1.5
ICCDR
VCC=1.5V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
L
L
Ind’l
4
10
3
µA
Auto
LL Ind’l
[7]
tCDR
Chip Deselect to Data
Retention Time
0
ns
[9]
tR
Operation Recovery Time
200
µs
Data Retention Waveform[10]
DATA RETENTION MODE
V
V
CC(min.)
VDR > 1.5V
VCC
CC(min.)
tCDR
tR
CEor
.
BHE B
LE
Notes:
8. Test condition for the 45-ns part is a load capacitance of 30 pF.
9. Full device operation requires linear V ramp from V to V > 200 µs.
CC(min.)
CC
DR
.
10. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both.
Document #: 38-05229 Rev. *H
Page 4 of 11
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CY62127DV30
Switching Characteristics (Over the Operating Range)[11]
CY62127DV30-45 [8] CY62127DV30-55 CY62127DV30-70
Parameter
Read Cycle
tRC
Description
Min.
45
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
55
70
tOHA
Data Hold from Address Change
CE LOW to Data Valid
10
10
10
tACE
45
25
55
25
70
35
tDOE
OE LOW to Data Valid
OE LOW to Low Z[12]
OE HIGH to High Z[12,14]
CE LOW to Low Z[12]
CE HIGH to High Z[12,14]
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
5
10
0
15
20
20
20
25
25
CE LOW to Power-up
tPD
CE HIGH to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z[12]
BLE/BHE HIGH to High-Z[12,14]
45
45
55
55
70
70
tDBE
[13]
tLZBE
5
5
5
tHZBE
15
20
25
Write Cycle[15]
tWC
tSCE
tAW
Write Cycle Time
45
40
40
0
55
40
40
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
tPWE
tBW
tSD
35
40
25
0
40
40
25
0
50
60
30
0
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[12,14]
WE HIGH to Low Z[12]
tHD
tHZWE
15
20
25
tLZWE
10
10
5
Notes:
11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the
CC(typ.)
CC(typ.)
specified I
.
OL
12. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
given device.
13. If both byte enables are toggled together, this value is 10 ns.
14. t , t , t , and t transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
15. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any
IL
IL
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05229 Rev. *H
Page 5 of 11
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CY62127DV30
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[16,17]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[16,17,18]
Write Cycle No. 1 (WE Controlled)[14, 15, 19, 20, 21]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
tHD
DATA I/O
DATA VALID
DON'T CARE
IN
tHZOE
Notes:
16. Device is continuously selected. OE, CE = V , BHE, BLE = V
.
IL
IL
17. WE is HIGH for Read cycle.
18. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
19. Data I/O is high-impedance if OE = V
.
IH
20. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
21. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05229 Rev. *H
Page 6 of 11
[+] Feedback
CY62127DV30
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[14, 15, 19, 20, 21]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
AW
HA
t
PWE
WE
t
BW
BHE/ BLE
OE
t
t
SD
HD
VALID
DATA I/O
DATA
DON'T CARE
IN
t
HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[20, 21]
tWC
ADDRESS
CE
tSCE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA VALID
tHD
DATA I/O
DON'T CARE
IN
tLZWE
tHZWE
Document #: 38-05229 Rev. *H
Page 7 of 11
[+] Feedback
CY62127DV30
Switching Waveforms (continued)
Write Cycle No. 4 (BHE-/BLE-controlled, OE LOW)[20, 21]
tWC
ADDRESS
CE
tSCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
DON'T CARE
DATA I/O
VALID
DATA
IN
Truth Table
CE
H
X
L
WE OE BHE BLE
I/O0–I/O7
High Z
I/O8–I/O15
High Z
Mode
Power
X
X
H
H
H
H
H
H
L
X
X
L
X
H
L
X
H
L
Deselect/Power-down
Deselect/Power-down
Read All bits
Standby (ISB
Standby (ISB
)
)
High Z
High Z
Data Out
Data Out
High Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
)
)
L
L
H
L
L
Read Lower Byte Only
Read Upper Byte Only
Output Disabled
Data Out
High Z
High Z
High Z
High Z
L
L
H
L
Data Out
High Z
L
H
H
H
X
X
X
L
High Z
L
H
L
L
Output Disabled
L
H
Output Disabled
High Z
Data In
High Z
Data In
L
L
Write
L
L
H
Data In
Data In
High Z
L
H
L
Write Lower Byte Only
Write Upper Byte Only
L
L
L
Document #: 38-05229 Rev. *H
Page 8 of 11
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CY62127DV30
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62127DV30LL-45BVXI
CY62127DV30LL-45ZXI
CY62127DV30LL-55BVI
CY62127DV30LL-55BVXI
CY62127DV30LL-55ZI
CY62127DV30L-55ZXI
CY62127DV30LL-55ZXI
CY62127DV30L-55BVXE
CY62127DV30L-55ZSXE
CY62127DV30L-70BVI
CY62127DV30LL-70BVXI
CY62127DV30L-70ZI
51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
51-85087 44-lead TSOP Type II (Pb-Free)
Industrial
55
51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
51-85087 44-lead TSOP Type II
Industrial
51-85087 44-lead TSOP Type II (Pb-Free)
51-85087 44-lead TSOP Type II (Pb-Free)
51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
51-85087 44-lead TSOP Type II (Pb-Free)
Automotive
Industrial
70
51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
51-85150 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-Free)
51-85087 44-lead TSOP Type II
CY62127DV30LL-70ZXI
51-85087 44-lead TSOP Type II (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts
Package Diagrams
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05ꢀ(48X
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
51-85150-*D
SEATING PLANE
C
Document #: 38-05229 Rev. *H
Page 9 of 11
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CY62127DV30
Package Diagrams (continued)
44-lead TSOP II (51-85087)
51-85087-*A
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05229 Rev. *H
Page 10 of 11
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62127DV30
Document History Page
Document Title: CY62127DV30 MoBL® 1-Mb (64K x 16) Static RAM
Document Number: 38-05229
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
117690
127311
08/27/02
06/13/03
JUI
New Data Sheet
*A
MPR
Changed From Advanced Status to Preliminary
Changed Isb2 to 5 µA (L), 4 µA (LL)
Changed Iccdr to 4 µA (L), 3 µA (LL)
Changed Cin from 6 pF to 8 pF
*B
128341
07/22/03
JUI
Changed from Preliminary to Final
Add 70-ns speed, updated ordering information
*C
*D
129000
316039
08/29/03
See ECN
CDY
PCI
Changed Icc 1 MHz typ from 0.5 mA to 0.85 mA
Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote # 8 on page #4
Added Lead-Free Package ordering information on page# 9
Changed 44-lead TSOP-II package name from Z44 to ZS44
*E
*F
346982
369955
See ECN
See ECN
AJU
SYT
Added 56-pin QFN package
Added Temperature Ranges in the Features Section on Page # 1
Added Automotive Specs for IIX,IOZ,ISB1and ISB2 in the Product portfolio on
Page #2 and the DC Electrical Characteristics table on Page# 4
Added Automotive spec for ICCDR in the Data Retention Characteristics table
on Page# 5
Added Pb-Free Automotive parts for 55 ns Speed bin
*G
*H
457685
470383
See ECN
See ECN
NXR
NXR
Removed 56-pin QFN package from product offering
Updated ordering Information Table
Changed pin #23 of TSOP II from NC to DNU and updated footnote #2
Document #: 38-05229 Rev. *H
Page 11 of 11
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