CY62128BLL-70SCT [CYPRESS]
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, SOIC-32;
| 型号： | CY62128BLL-70SCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, SOIC-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62128B
MoBL®
1-Mbit (128K x 8) Static RAM
Features
Functional Description[1]
• Temperature Ranges
The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE1),
an active HIGH Chip Enable (CE2), an active LOW Output
Enable (OE), and three-state drivers. This device has an
automatic power-down feature that reduces power
consumption by more than 75% when deselected.
—Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• 4.5V–5.5V operation
• CMOS for optimum speed/power
Writing to the device is accomplished by taking Chip Enable
One (CE1) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
• Low active power
(70 ns, LL version, Commercial, Industrial)
— 82.5 mW (max.) (15 mA)
• Low standby power
(70 ns, LL version, Commercial, Industrial)
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
— 110 µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
Logic Block Diagram
I/O
0
INPUT BUFFER
I/O
I/O
1
2
A
A
A
0
1
2
A
A
A
A
A
A
3
4
5
6
7
8
I/O
I/O
I/O
3
4
5
512x256x8
ARRAY
I/O
I/O
6
7
POWER
DOWN
COLUMN
DECODER
CE
CE
1
2
WE
OE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05300 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 7, 2005
CY62128B
MoBL®
Product Portfolio
Power Dissipation
Operating, ICC
(mA)
Standby, ISB2
VCC Range (V)
Typ.[2]
(µA)
Speed
(ns)
Product
CY62128BLL Industrial
Industrial
Min.
Max.
Typ.[2]
Max.
20
Typ.[2]
Max.
15
4.5
5.0
5.5
55
70
70
7.5
6
2.5
15
2.5
15
Automotive
6
25
2.5
25
Pin Configurations
Top View
SOIC
VCC
NC
32
1
A
31
30
16
A
2
3
4
15
A
14
CE
2
A
12
29
28
WE
A
13
5
A
A
A
7
6
5
27
26
6
A
8
A
9
7
25
24
23
22
21
A
A
3
8
9
10
11
12
13
A
4
11
OE
A
A
2
10
A
CE
1
I/O
I/O
6
I/O
5
I/O
I/O
1
A
7
0
I/O
0
20
19
I/O
1
14
15
16
I/O
2
gGnNcD
18
17
4
3
GN
G
A
A
3
4
5
16
15
14
13
12
11
10
9
A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
25
26
24
23
OE
10
11
9
8
A11
A9
1
2
32
31
OE
A
A
A
2
A
A
A10
27
28
29
30
31
32
1
A
1
A
22
21
20
19
18
17
16
15
14
13
12
11
10
9
CE
I/O
A6
A
0
3
A8
30
29
28
27
26
2255
24
1
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
A
13
4
7
A13
7
6
5
4
3
A
I/O
0
WE
I/O
I/O
I/O
I/O
5
12
WE
CE2
A15
CE
2
A
A
I/O
1
A14
I/O
6
STSOP
Reverse TSOP I
Top View
(not to scale)
15
7
TSOP I
Top View
(not to scale)
2
16
Top View
V
NC
GND
CC
8
VCC
NC
(not to scale)
NC
GND
V
I/O
3
8
7
6
5
4
3
CC
9
A
I/O
2
I/O
2
16
14
12
A
4
A16
23 I/O2
22 I/O1
21 I/O0
20 A0
15
10
11
12
13
14
15
16
I/O
1
A
3
I/O
5
CE
A14
A12
A7
2
A
I/O
0
4
I/O
6
WE
A
A
0
5
7
I/O
7
A
13
A
1
A
6
6
CE
A
8
A
A1
19
A6
A5
A4
1
A
2
7
A
A
5
18 A2
17 A3
10
31
9
2
A
3
8
A
4
A
OE
32
1
11
Pin Definitions
Input
A0-A16. Address Inputs
I/O0-I/O7. Data lines. Used as input or output lines depending on operation
Input/Output
Input/Control
WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ
is conducted.
Input/Control
Input/Control
Input/Control
CE1. Chip Enable 1, Active LOW.
CE2. Chip Enable 2, Active HIGH.
OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins
Ground
GND. Ground for the device
Power Supply
VCC. Power supply for the device
Note:
2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production
variations as measured at V = 5.0V, T = 25°C, and t = 70 ns.
CC
A
AA
Document #: 38-05300 Rev. *C
Page 2 of 11
CY62128B
MoBL®
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.....................................................> 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature (TA)[4]
0°C to +70°C
VCC
DC Voltage Applied to Outputs
5V ± 10%
5V ± 10%
5V ± 10%
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
–40°C to +85°C
–40°C to +125°C
DC Input Voltage[3].................................–0.5V to VCC + 0.5V
Automotive
Electrical Characteristics Over the Operating Range
CY62128B-55
CY62128B-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
Output HIGH Voltage VCC = Min., IOH = –1.0 mA
2.4
2.2
2.4
2.2
V
V
V
VOL
Output LOW Voltage
Input HIGH Voltage
VCC = Min., IOL = 2.1 mA
0.4
0.4
VIH
VCC
VCC
+ 0.3
+ 0.3
VIL
IIX
Input LOW Voltage[3]
Input Load Current
–0.3
–1
0.8 –0.3
0.8
+1
V
GND ≤ VI ≤ VCC
+1
+1
–1
µA
Automotive
Automotive
–10
–1
+10
+1
µA
µA
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC
,
–1
Output Disabled
–10
+10
IOS
ICC
Output Short Circuit
Current[5]
VCC = Max., VOUT = GND
–300
20
–300 mA
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Industrial,
Commercial
7.5
0.1
6
15
mA
Automotive
6
25
1
mA
mA
ISB1
Automatic CE
Max. VCC
,
Industrial
2
0.1
Power-down Current
—TTL Inputs
CE1 ≥ VIH
Commercial
or CE2 < VIL,
VIN ≥ VIH or
Automotive
0.1
2
mA
VIN ≤ VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC
CE1 ≥ VCC – 0.3V, Commercial
or CE2 ≤ 0.3V,
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f = 0
,
Industrial
2.5
15
2.5
2.5
15
25
µA
µA
Automotive
Notes:
3.
4.
V
A
(min.) = –2.0V for pulse durations of less than 20 ns.
is the “Instant On” case temperature.
IL
T
5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05300 Rev. *C
Page 3 of 11
CY62128B
MoBL®
Thermal Resistance[6]
Parameter
Description
Test Conditions
32 SOIC 32 TSOP 32 STSOP 32 RTSOP Unit
ΘJA
Thermal Resistance Test conditions follow standard test 66.17
(Junction to Ambient) methods and procedures for
measuring thermal impedance, per
97.44
105.14
97.44
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
30.87
26.05
14.09
26.05
°C/W
EIA / JESD51.
Capacitance[6]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
CC = 5.0V
9
9
pF
pF
V
COUT
AC Test Loads and Waveforms
R1 1800Ω
ALL INPUT PULSES
90%
R1 1800
Ω
5V
5V
VCC
90%
OUTPUT
OUTPUT
10%
10%
R2
990
R2
990Ω
100 pF
GND
5 pF
Ω
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Rise TIme:
1 V/ns
Fall TIme:
1 V/ns
(b)
(a)
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
639Ω
1.77V
Data Retention Waveform
DATA RETENTION MODE
VCC, min.
tR
> 2 V
VDR
VCC, min.
tCDR
VCC
CE
or
1
CE
2
Data Retention Characteristics (Over the Operating Range for “LL” version only)
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.
Max. Unit
2.0
V
ICCDR
VCC = VDR = 2.0V, CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V, VIN ≥ VCC – 0.3V or, VIN
0.3V
1.5
15
µA
≤
tCDR
Chip Deselect to Data Retention
Time
0
ns
ns
tR
Operation Recovery Time
70
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05300 Rev. *C
Page 4 of 11
CY62128B
MoBL®
Switching Characteristics[7] Over the Operating Range
62128B-55
62128B-70
Parameter
READ CYCLE
tRC
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
55
5
70
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
OE LOW to Data Valid
55
20
70
35
tDOE
tLZOE
OE LOW to Low Z
OE HIGH to High Z[7, 9]
0
5
0
0
5
0
tHZOE
tLZCE
tHZCE
tPU
20
20
55
25
25
70
CE1 LOW to Low Z, CE2 HIGH to Low Z[9]
CE1 HIGH to High Z, CE2 LOW to High Z[8, 9]
CE1 LOW to Power-up, CE2 HIGH to Power-up
CE1 HIGH to Power-down, CE2 LOW to Power-down
tPD
WRITE CYCLE[10]
tWC
tSCE
tAW
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
45
25
0
50
30
0
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z[9]
tHD
tLZWE
tHZWE
5
5
WE LOW to High Z[8, 9]
20
25
Switching Waveforms
Read Cycle No.1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 100-pF load capacitance.
OL OH
8.
t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
9. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
10. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH, and WE LOW. CE and WE must be LOW and CE HIGH to initiate a write,
1
2
1
2
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
11. No input may exceed V + 0.5V.
CC
12. Device is continuously selected. OE, CE = V , CE = V .
IH
1
IL
2
13. WE is HIGH for read cycle.
Document #: 38-05300 Rev. *C
Page 5 of 11
CY62128B
MoBL®
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Write Cycle No. 1 (CE1 or CE2 Controlled)[15, 16]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes:
14. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.
1
2
15. Data I/O is high impedance if OE = V
.
IH
16. If CE goes HIGH or CE goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
1
2
Document #: 38-05300 Rev. *C
Page 6 of 11
CY62128B
MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
17
NOTE
t
HZOE
Write Cycle No.3 (WE Controlled, OE LOW)[15, 16]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATAI/O
DATA VALID
t
t
LZWE
HZWE
Note:
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05300 Rev. *C
Page 7 of 11
CY62128B
MoBL®
Truth Table
CE1
H
CE2
OE
X
WE
X
I/O0–I/O7
High Z
Mode
Power
X
L
Power-down
Power-down
Read
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
X
X
X
High Z
)
L
H
H
H
L
H
Data Out
Data In
High Z
)
L
X
L
Write
)
L
H
H
Selected, Outputs Disabled
)
Ordering Information
Speed (ns)
Ordering Code
CY62128BLL-55SI
CY62128BLL-55SXI
CY62128BLL-55SC
CY62128BLL-55SXC
CY62128BLL-55ZI
CY62128BLL-55ZXI
CY62128BLL-55ZAI
CY62128BLL-55ZAXI
CY62128BLL-55ZRI
CY62128BLL-70SI
CY62128BLL-70SXI
CY62128BLL-70SC
CY62128BLL-70SXC
CY62128BLL-70SE
CY62128BLL-70SXE
CY62128BLL-70ZI
CY62128BLL-70ZC
CY62128BLL-70ZE
CY62128BLL-70ZXE
CY62128BLL-70ZAI
CY62128BLL-70ZAXI
CY62128BLL-70ZAE
CY62128BLL-70ZAXE
CY62128BLL-70ZRXE
Package Name
Package Type
Operating Range
Industrial
55
S34
S34
32-Lead 450-Mil SOIC
32-Lead 450-Mil SOIC (Pb-Free)
32-Lead 450-Mil SOIC
Industrial
S34
Commercial
Commercial
Industrial
S34
32-Lead 450-Mil SOIC (Pb-Free)
32-Lead TSOP Type I
Z32
Z32
32-Lead TSOP Type I (Pb-Free)
32-Lead STSOP Type I
Industrial
ZA32
ZA32
ZR32
S34
Industrial
32-Lead STSOP Type I (Pb-Free)
32-Lead Reverse TSOP Type I
32-Lead 450-Mil SOIC I
Industrial
Industrial
70
Industrial
S34
32-Lead 450-Mil SOIC I (Pb-Free)
32-Lead 450-Mil SOIC I
Industrial
S34
Commercial
Commercial
Automotive
Automotive
Industrial
S34
32-Lead 450-Mil SOIC I (Pb-Free)
32-Lead 450-Mil SOIC I
S34
S34
32-Lead 450-Mil SOIC I (Pb-Free)
32-Lead TSOP Type I
Z32
Z32
32-Lead TSOP Type I
Commercial
Automotive
Automotive
Industrial
Z32
32-Lead TSOP Type I
Z32
32-Lead TSOP Type I (Pb-Free)
32-Lead STSOP Type I
ZA32
ZA32
ZA32
ZA32
ZR32
32-Lead STSOP Type I (Pb-Free)
32-Lead STSOP Type I
Industrial
Automotive
Automotive
Automotive
32-Lead STSOP Type I (Pb-Free)
32-Lead Reverse TSOP Type I (Pb-Free)
Document #: 38-05300 Rev. *C
Page 8 of 11
CY62128B
MoBL®
Package Diagrams
32-Lead (450 MIL) Molded SOIC S34
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.047[1.193]
0.063[1.600]
0.004[0.102]
MIN.
0.050[1.270]
BSC.
0.023[0.584]
0.039[0.990]
0.014[0.355]
0.020[0.508]
SEATING PLANE
51-85081-*B
32-Lead Thin Small Outline Package Type I (8x20 mm) Z32
51-85056-*D
Document #: 38-05300 Rev. *C
Page 9 of 11
CY62128B
MoBL®
Package Diagrams (continued)
32-Lead Shrunk Thin Small Outline Package (8x13.4 mm) ZA32
51-85094-*D
32-Lead Reverse Thin Small Outline Package ZR32
51-85089-*C
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05300 Rev. *C
Page 10 of 11
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62128B
MoBL®
Document History Page
Document Title: CY62128B MoBL® 1-Mbit (128K x 8) Static RAM
Document Number: 38-05300
Issue
Date
Orig. of
Change
REV. ECN NO.
Description of Change
**
116566
126601
06/20/02
06/09/03
DSG
JUI
Changed from Spec number: 38-00524 to 38-05300
*A
Changed CE to CE1 and added CE2 ≤ 0.3V in Data Retention Characteristics table
Removed these part numbers from Ordering Information table:
CY62128BLL-55ZC, CY62128BLL-55ZAC, CY62128BLL-55ZRC,
CY62128BLL-70ZAC, CY62128BLL-70ZRI, CY62128BLL-70ZRC
*B
*C
239134
334398
See ECN
See ECN
AJU
SYT
Added Thermal Resistance table
Added Automotive product information
Added Pb-Free part numbers to the Ordering info on Page #8
Document #: 38-05300 Rev. *C
Page 11 of 11
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