CY62128ELL-45SXIT [CYPRESS]
Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 0.450 INCH, ROHS COMPLIANT, PLASTIC, SOIC-32;
| 型号： | CY62128ELL-45SXIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX8, 45ns, CMOS, PDSO32, 0.450 INCH, ROHS COMPLIANT, PLASTIC, SOIC-32 |
| 文件： | 总11页 (文件大小：948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62128E MoBL®
1-Mbit (128K x 8) Static RAM
Features
Functional Description[1]
The CY62128E is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE1 HIGH
or CE2 LOW). The eight input and output pins (IO0 through
IO7) are placed in a high impedance state when the device is
deselected (CE1 HIGH or CE2 LOW), the outputs are disabled
(OE HIGH), or a write operation is in progress (CE1 LOW and
CE2 HIGH and WE LOW)
• Very high speed: 45 ns
• Temperature ranges
— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automotive-E: –40°C to +125°C
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62128B
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 4 µA (Industrial)
• Ultra low active power
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO0 through IO7) is then written into the location
specified on the address pins (A0 through A16).
— Typical active current: 1.3 mA @ f = 1 MHz
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appears on
the IO pins.
• Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC,
and 32-pin TSOP I packages
Logic Block Diagram
IO
0
INPUT BUFFER
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO
1
IO
2
128K x 8
ARRAY
IO
3
IO
IO
IO
IO
4
5
6
7
A
A
A
9
10
11
CE
CE
1
2
POWER
DOWN
COLUMN DECODER
WE
OE
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05485 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 07, 2007
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CY62128E MoBL®
Pin Configuration[2]
A11
A9
A8
1
2
32
31
OE
A10
CE1
IO7
IO6
IO5
IO4
IO3
GND
IO2
IO1
IO0
A0
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A13
32-Pin SOIC
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
Top View
TSOP I
Top View
(not to scale)
9
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
IO7
IO6
IO5
IO4
IO3
1
32
NC
A16
10
11
12
13
14
15
16
2
3
31
30
29
28
27
26
25
24
23
22
A14
A12
A7
4
A1
A2
A3
5
A6
6
A5
A4
A3
A2
A1
A0
IO0
IO1
IO2
VSS
7
8
9
10
A
A
A
8
24
OE
11
25
26
23
A
9
10
11
12
13
14
15
16
22
21
20
19
18
17
16
15
14
13
12
11
10
9
CE
26
7
1
21
20
19
18
17
28
29
30
31
32
1
2
3
4
5
6
7
8
A
IO
7
13
WE
CE
IO
IO
6
5
2
A
STSOP
Top View
(not to scale)
15
IO
IO
4
3
V
CC
NC
GND
A
IO
16
2
IO
1
A
14
A
IO
12
0
A
A
6
A
A
A
0
7
A
1
A
2
5
4
A
3
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1MHz f = fmax
Speed
(ns)
Product
Range
VCC Range (V)
Standby ISB2 (µA)
Min
4.5
4.5
Typ[3]
5.0
Max
5.5
Typ[3]
Max
2
Typ[3]
Max
16
Typ[3]
Max
4
CY62128ELL Ind’l/Auto-A
45 [4]
55
1.3
1.3
11
11
1
1
CY62128ELL
Auto-E
5.0
5.5
4
35
30
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
CC
CC(typ)
A
4. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (t , t
) and 25 ns (t
) are guaranteed.
AA ACE
DOE
Document #: 38-05485 Rev. *E
Page 2 of 11
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CY62128E MoBL®
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage........................................... > 2001V
(MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch up Current..................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
[7]
Device
Range
VCC
Supply Voltage to Ground
Potential...............................–0.5V to 6.0V (VCC(max) + 0.5V)
Temperature
CY62128ELL Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V
DC Voltage Applied to Outputs
in High-Z State[5, 6]...............–0.5V to 6.0V (VCC(max) + 0.5V)
Auto-E
–40°C to +125°C
DC Input Voltage[5, 6] ...........–0.5V to 6.0V (VCC(max) + 0.5V)
Electrical Characteristics (Over the Operating Range)
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Parameter
Description
Test Conditions
IOH = –1 mA
IOL = 2.1 mA
Unit
Min Typ[3]
Max
Min Typ[3]
Max
VOH
Output HIGH
Voltage
2.4
2.4
V
VOL
Output LOW
Voltage
0.4
0.4
V
VIH
VIL
IIX
Input HIGH Voltage VCC = 4.5V to 5.5V
Input LOW voltage VCC = 4.5V to 5.5V
2.2
–0.5
–1
VCC + 0.5 2.2
VCC + 0.5
0.8
V
V
0.8
+1
–0.5
–4
Input Leakage
Current
GND < VI < VCC
+4
µA
IOZ
ICC
Output Leakage
Current
GND <VO <VCC,Output Disabled –1
+1
–4
+4
µA
VCC Operating
Supply Current
f = fmax = 1/tRC VCC = VCC(max)
11
16
2
11
35
4
mA
IOUT = 0 mA
f = 1 MHz
1.3
1.3
CMOS levels
[8]
ISB2
Automatic CE
Power down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V,
1
4
1
30
µA
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
Capacitance (For all Packages) [9]
Parameter Description
Test Conditions
Max
10
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
CC = VCC(typ)
pF
pF
V
COUT
10
Notes
5.
6.
V
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
= V + 0.75V for pulse durations less than 20 ns.
IH(max)
CC
7. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
8. Only chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
1
2
SB2 CCDR
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05485 Rev. *E
Page 3 of 11
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CY62128E MoBL®
Thermal Resistance[9]
SOIC
Package
STSOP
Package
TSOP
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient) two-layer printed circuit board
Still Air, soldered on a 3 × 4.5 inch,
48.67
25.86
32.56
33.01
3.42
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
3.59
°C/W
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
VCC
3.0V
GND
OUTPUT
90%
10%
10%
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
Equivalent to:
THEVENIN EQUIVALENT
SCOPE
RTH
OUTPUT
V
Parameters
Value
1800
990
Unit
Ω
R1
R2
Ω
RTH
VTH
639
Ω
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min Typ[3] Max Unit
VDR
VCC for Data Retention
2
V
[8]
ICCDR
Data Retention Current VCC=VDR, CE1 > VCC − 0.2V or CE2 < 0.2V, Ind’l/Auto-A
IN > VCC - 0.2V or VIN < 0.2V
4
µA
µA
ns
V
Auto-E
30
[9]
tCDR
Chip Deselect to Data
Retention Time
0
[10]
tR
Operation Recovery
Time
tRC
ns
Data Retention Waveform[11]
DATA RETENTION MODE
> 2.0V
VCC(min)
VCC(min)
V
VCC
CE
DR
t
t
R
CDR
Notes
10. Full device AC operation requires linear V ramp from V to V
> 100 µs or stable at V
2
> 100 µs.
CC
DR
CC(min)
CC(min)
11. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
1
2
Document #: 38-05485 Rev. *E
Page 4 of 11
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CY62128E MoBL®
Switching Characteristics (Over the Operating Range)[12]
45 ns (Ind’l/Auto-A)
55 ns (Auto-E)
Unit
Parameter
Description
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
55
tOHA
tACE
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
10
10
45
22
55
25
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Low-Z[13]
5
10
0
5
10
0
OE HIGH to High-Z[13, 14]
18
18
45
20
20
55
CE1 LOW and CE2 HIGH to Low-Z[13]
CE1 HIGH or CE2 LOW to High-Z[13, 14]
CE1 LOW and CE2 HIGH to Power Up
CE1 HIGH or CE2 LOW to Power Down
tPD
Write Cycle[15]
tWC
Write Cycle Time
45
35
35
55
ns
ns
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
40
40
tAW
tHA
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
0
0
ns
ns
ns
ns
ns
ns
ns
0
0
tSA
tPWE
tSD
35
25
0
40
25
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z[13, 14]
WE HIGH to Low-Z[13]
tHD
tHZWE
tLZWE
18
20
10
10
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” on page 4.
OL OH
13. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
14. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
15. The internal Write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can
IL
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05485 Rev. *E
Page 5 of 11
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CY62128E MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [16, 17]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [11, 17, 18]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
t
V
CC
PU
50%
SUPPLY
CURRENT
50%
ISB
Write Cycle No. 1 (WE Controlled) [11, 15, 19, 20]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
21
DATA IO
NOTE
DATA VALID
t
HZOE
Notes:
16. The device is continuously selected. OE, CE = V , CE = V
.
1
IL
2
IH
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
19. Data IO is high impedance if OE = V
.
IH
20. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
21. During this period, the IOs are in output state and input signals must not be applied.
Document #: 38-05485 Rev. *E
Page 6 of 11
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CY62128E MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 Controlled) [11, 15, 19, 20]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IO
DATA VALID
Write Cycle No. 3 (WE Controlled, OE LOW) [11, 20]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
21
NOTE
DATA VALID
DATA IO
t
t
LZWE
HZWE
Truth Table
CE1
H
CE2
WE
X
OE
X
Inputs/Outputs
High-Z
Mode
Power
X
L
Deselect/Power down
Deselect/Power down
Read
Standby (ISB
)
)
X
X
X
High-Z
Data Out
Data In
High-Z
Standby (ISB
L
H
H
H
H
L
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
L
X
Write
L
H
H
Selected, Outputs Disabled
Document #: 38-05485 Rev. *E
Page 7 of 11
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CY62128E MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62128ELL-45SXI
CY62128ELL-45ZAXI
CY62128ELL-45ZXI
CY62128ELL-45SXA
CY62128ELL-45ZXA
CY62128ELL-55SXE
CY62128ELL-55ZAXE
51-85081 32-pin 450-Mil SOIC (Pb-free)
51-85094 32-pin STSOP (Pb-free)
Industrial
51-85056 32-pin TSOP Type I (Pb-free)
51-85081 32-pin 450-Mil SOIC (Pb-free)
51-85094 32-pin TSOP Type I (Pb-free)
51-85081 32-pin 450-Mil SOIC (Pb-free)
51-85094 32-pin STSOP (Pb-free)
45
55
Automotive-A
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.047[1.193]
0.063[1.600]
0.004[0.102]
0.050[1.270]
BSC.
0.023[0.584]
0.039[0.990]
MIN.
0.014[0.355]
0.020[0.508]
SEATING PLANE
51-85081-*B
Document #: 38-05485 Rev. *E
Page 8 of 11
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CY62128E MoBL®
Package Diagrams (continued)
Figure 2. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094
51-85094-*D
Document #: 38-05485 Rev. *E
Page 9 of 11
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CY62128E MoBL®
Package Diagrams (continued)
Figure 3. 32-pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056
51-85056-*D
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05485 Rev. *E
Page 10 of 11
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62128E MoBL®
Document History Page
Document Title: CY62128E MoBL® 1-Mbit (128K x 8) Static RAM
Document Number: 38-05485
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
203120
299472
See ECN
See ECN
AJU
New data sheet
*A
SYT Converted from Advance Information to Preliminary
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns, respectively
Changed tDOE from 15 ns to 18 ns for 35 ns speed bin
Changed tHZOE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns
speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
respectively
Changed tSCE from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins,
respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
respectively
Added Pb-free package information
Added footnote #9
Changed operating range for SOIC package from Commercial to Industrial
Modified signal transition time from 5 ns to 3 ns in footnote #11
Changed max of ISB1, ISB2 and ICCDR from 1.0 µA to 1.5 µA
*B
461631
See ECN
NXR Converted from Preliminary to Final
Included Automotive Range and 55 ns speed bin
Removed 35 ns speed bin
Removed “L” version of CY62128E
Removed Reverse TSOP I package from Product offering
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz
Removed ISB1 DC Specs from Electrical characteristics table
Changed ISB2 (max) from 1.5 µA to 4 µA
Changed ISB2 (Typ) from 0.5 µA to 1 µA
Changed ICCDR (max) from 1.5 µA to 4 µA
Changed the AC Test load Capacitance value from 100 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information Table
*C
*D
*E
464721
563144
See ECN
See ECN
NXR Updated the Block Diagram on page # 1
AJU
Added footnote 4 on page 2
1024520 See ECN
VKN Added Automotive-A information
Converted Automotive-E specs to final
Added footnote #9 related to ISB2 and ICCDR
Updated Ordering Information table
Document #: 38-05485 Rev. *E
Page 11 of 11
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