CY62128VL-70ZCT [CYPRESS]
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, TSOP1-32;
| 型号： | CY62128VL-70ZCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, TSOP1-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
amily
CY62128V Family
128K x 8 Static RAM
LOW Output Enable (OE) and three-state drivers. These de-
vices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Features
• Low voltage range:
— 2.7V–3.6V (CY62128V)
— 2.3V–2.7V (CY62128V25)
Writing to the device is accomplished by taking Chip Enable
one (CE ) and Write Enable (WE) inputs LOW and the Chip
— 1.6V–2.0V (CY62128V18)
1
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Enable two (CE ) input HIGH. Data on the eight I/O pins (I/O
2
0
through I/O ) is then written into the location specified on the
7
address pins (A through A ).
0
16
Reading from the device is accomplished by taking Chip En-
able one (CE ) and Output Enable (OE) LOW while forcing
1
Write Enable (WE) and Chip Enable two (CE ) HIGH. Under
2
Functional Description
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The CY62128V family is composed of three high-performance
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
The eight input/output pins (I/O through I/O ) are placed in a
0
7
high-impedance state when the device is deselected (CE
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or
2
Enable (CE ), an active HIGH Chip Enable (CE ), an active
1
2
during a write operation (CE LOW, CE HIGH, and WE LOW).
1
2
Logic Block Diagram
Pin
Configurations
Top View
SOIC
V
NC
32
31
30
1
CC
A
16
A
14
A
12
A
15
2
3
4
CE
2
29
28
WE
5
A
A
A
A
7
13
27
26
A
6
6
8
A
5
7
9
I/O0
I/O1
I/O2
25
24
23
22
21
A
A
3
INPUT BUFFER
8
9
10
11
12
13
4
A
11
OE
A
0
A
A
10
2
A
1
A
1
CE
1
I/O
7
A
2
A
0
I/O
0
I/O
1
I/O
2
I/O
6
A
3
20
19
A
4
I/O
I/O3
I/O4
I/O5
I/O6
5
4
3
14
15
16
512x256x 8
ARRAY
A
5
I/O
I/O
18
17
A
62128V-2
6
GND
A
7
A
8
POWER
DOWN
COLUMN
DECODER
CE
1
CE
WE
2
I/O7
62128V-1
OE
A
A
A
A
A
A
A
A
WE
CE
A
1
2
4
5
A
3
32
31
11
OE
16
15
14
13
12
11
10
9
8
7
6
5
4
3
17
A
A
9
8
18
19
20
21
22
23
24
25
26
27
28
29
30
2
10
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
1
CE
I/O
I/O
I/O
6
7
1
A
13
0
7
6
5
A
A
I/O
0
I/O
I/O
2
GND
I/O
I/O
4
I/O
I/O
6
I/O
CE
1
12
14
TSOP I
2
1
TSOP I / STSOP
Top View
(not to scale)
A
15
I/O
I/O
16
4
3
Reverse Pinout
V
NC
CC
CC
Top View
V
NC
A
A
A
A
A
6
A
A
4
9
GND
3
(not to scale)
I/O
A
10
11
12
13
14
15
16
16
2
15
I/O
1
CE
WE
5
14
12
2
I/O
0
A
0
A
7
7
13
A
A
A
9
1
8
A
A
2
10
31
32
2
1
5
A
A
OE
3
11
62128V-4
62128V-3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 27, 2000
CY62128V Family
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
V
CC
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)........................................... –0.5V to +4.6V
1.6V to 3.6V
1.6V to 3.6V
DC Voltage Applied to Outputs
–40°C to +85°C
[1]
in High Z State ....................................–0.5V to V + 0.5V
CC
[1]
DC Input Voltage .................................–0.5V to V + 0.5V
CC
Product Portfolio
Power Dissipation (Commercial)
Operating (I Standby (I )
SB2
V
Range
)
CC
CC
[2]
[2]
[2]
Product
CY62128V
Min.
2.7V
2.3V
1.6V
Typ.
Max.
3.6V
2.7V
2.0V
Speed
55, 70 ns
100 ns
Typ.
Maximum
40 mA
Typ.
Maximum
3.0V
2.5V
1.8V
20 mA
15 mA
10 mA
0.4 µA
0.3 µA
0.3 µA
100 µA (XL = 10 µA)
50 µA (LL = 12 µA)
30 µA (LL = 10 µA)
CY62128V25
CY62128V18
20 mA
200 ns
15 mA
Electrical Characteristics Over the Operating Range
CY62128V-55/70
[2]
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = –1.0 mA
Min.
2.4
Typ.
Max.
Unit
V
V
V
V
OH
CC
CC
OH
V
= Min., I = 2.1 mA
0.4
V
OL
OL
V
2
V
V
IH
CC
+0.5V
V
Input LOW Voltage
Input Load Current
Output Leakage Current
–0.5
–1
0.8
+1
+1
40
40
50
V
IL
I
I
I
GND < V < V
CC
±1
±1
20
20
23
µA
µA
mA
IX
I
GND < V < V , Output Disabled
–1
OZ
CC
O
CC
V
Operating Supply
V
= Max.,
= 0 mA,
Com’l,
70 ns
L
CC
CC
Current
I
OUT
LL, XL
LL
f = f
= 1/t
MAX
RC
Ind’l,
55 ns
Ind’l,
70 ns
L
20
20
15
15
17
40
40
LL
I
Automatic CE
Max. V , CE > V , Com’l,
L
300
300
350
µA
SB1
CC
IH
Power-Down Current—
TTL Inputs
V
V
> V or
70 ns
IN
IN
IH
LL, XL
< V , f = f
IL
MAX
Coml, LL
55 ns
Ind’l
L
15
15
300
300
LL
Notes:
1. IL (min.) = –2.0V for pulse durations of less than 20 ns.
V
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C.
2
CY62128V Family
Electrical Characteristics Over the Operating Range
CY62128V-55/70
[2]
Parameter
Description
Automatic CE
Power-Down Current—
CMOS Inputs
Test Conditions
Min.
Typ.
0.4
Max.
100
15
Unit
µA
µA
µA
µA
µA
I
Max. V
,
CC
Com’l
L
SB2
CE > V – 0.3V
> V – 0.3V
IN CC
or V < 0.3V, f = 0
CC
LL
XL
L
V
10
IN
Ind’l
100
30
LL
Electrical Characteristics Over the Operating Range
CY62128V25-100
CY62128V18-200
[2]
[2]
Parameter
Description
Test Conditions
= Min., I = –0.1 mA
Min. Typ.
Max. Min. Typ.
Max. Unit
V
Output HIGH Voltage
V
V
2.4
0.8*
V
OH
CC
CC
OH
V
CC
V
Output LOW Voltage
Input HIGH Voltage
= Min., I = 0.1 mA
0.4
0.2
V
V
OL
OL
V
2
V
0.7*
V
CC
IH
CC
+0.5
V
+0.3
CC
V
Input LOW Voltage
Input Load Current
–0.5
0.8
–0.5
0.3*
V
IL
V
CC
I
I
GND < V < V
CC
–1
–1
±1
±1
+1
+1
–1
–1
±0.1
±0.1
+1
µA
µA
IX
I
Output Leakage Current GND < V < V , Output
+1
OZ
O
CC
Disabled
I
I
I
V
Operating Supply
V
= Max.,
= 0 mA,
L
15
15
20
10
5
15
mA
CC
CC
CC
Current
I
OUT
LL
f = f
= 1/t
MAX
RC
Automatic CE
Power-Down Current—
TTL Inputs
Max. V , CE > V ,
V
V
L
300
100
µA
SB1
SB2
CC
IH
> V or
IN
IN
IH
LL
< V , f = f
IL
MAX
Automatic CE
Power-Down Current—
CMOS Inputs
Max. V
CE > V – 0.3V
V
,
L
0.4
50
12
0.4
30
10
µA
µA
CC
CC
LL
> V – 0.3V
CC
IN
or V < 0.3V, f = 0
IN
Indust’l Temp Range LL
24
20
µA
Capacitance[3]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
6
8
pF
pF
IN
A
V
= 3.0V
CC
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
3
CY62128V Family
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
90%
OUTPUT
1.8V
GND
90%
10%
10%
R2
50 pF
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
62128V–5
62128V–6
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
3.3V
1213
1378
645
2.5V
1.8V
Unit
Ohms
Ohms
Ohms
Volts
R1
R2
15909
4487
10800
4154
R
V
3500
3000
TH
TH
1.75V
0.55V
0.50V
Data Retention Characteristics (Over the Operating Range)
[4]
[2]
Parameter
Description
for Data Retention
CC
Conditions
Min.
Typ.
Max.
Unit
V
V
V
1.6
DR
I
Data Retention Current
Com’l
Ind’l
L
V
= 2V
CC
0.4
10
10
µA
µA
CCDR
CE > V – 0.3V,
CC
LL,
XL
V
V
> V – 0.3V or
IN
IN
CC
< 0.3V
L
No input may exceed
V
20
20
µA
µA
ns
+0.3V
CC
LL
[3]
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
CDR
t
ns
R
RC
Data Retention Waveform
DATA RETENTION MODE
> 1.6 V
1.8V
1.8V
V
V
CC
DR
t
t
R
CDR
CE
C62128V–7
Note:
4. No input may exceed VCC+0.3V.
4
CY62128V Family
Data Retention Current Graph (for “L” version only)
CURRENT
DATA RETENTION
vs. SUPPLY VOLTAGE
80
70
60
50
40
T
=25 C
°
A
30
20
10
0
SUPPLY VOLTAGE (V)
[5]
Switching Characteristics Over the Operating Range
62128V-55 62128V-70 62128V25-100 62128V18-200
Parameter
Description
Min. Max. Min. Max. Min.
Max.
Min.
200
10
Max. Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
55
5
70
10
100
10
ns
RC
Address to Data Valid
55
70
100
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
Data Hold from Address Change
CE LOW to Data Valid
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
55
20
70
35
100
75
200
125
OE LOW to Data Valid
[6]
OE LOW to Low Z
10
10
0
10
10
0
10
10
0
10
10
0
[6, 7]
OE HIGH to High Z
20
20
55
25
25
70
50
50
75
75
[6]
CE LOW to Low Z
[6, 7]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
100
200
PD
[8, 9]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
55
45
45
0
70
60
60
0
100
100
100
0
200
190
190
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
0
SA
45
25
0
55
30
0
90
60
0
125
100
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[6, 7]
WE LOW to High Z
20
25
50
100
HZWE
[6]
WE HIGH to Low Z
5
5
10
15
LZWE
5. Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE signals must be LOW and CE2 HIGH to initiate a
write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
5
CY62128V Family
Switching Waveforms
[10, 11]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62128V–8
[11, 12]
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
62128V-9
[13,14]
Write Cycle No. 1 (CE or CE Controlled)
1
2
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
62128V-10
Notes:
10. Device is continuously selected. OE, CE = VIL, CE2=VIH
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. Data I/O is high impedance if OE = VIH
.
.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
6
CY62128V Family
Switching Waveforms (continued)
[13, 14]
WC
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE
15
t
HZOE
62128V-11
Note:
15. During this period, the I/Os are in output state and input signals should not be applied.
Truth Table
CE
H
X
CE
X
OE
X
WE
X
I/O –I/O
7
Mode
Power
1
2
0
High Z
Power-Down
Power-Down
Read
Standby (I
Standby (I
)
SB
L
X
X
High Z
)
SB
L
H
L
H
Data Out
Data In
High Z
Active (I
Active (I
Active (I
)
CC
L
H
X
L
Write
)
CC
L
H
H
H
Selected, Outputs Disabled
)
CC
7
CY62128V Family
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
32-Lead STSOP Type 1
55
CY62128VLL-55ZAI
CY62128VL-70SC
ZA32
S34
Industrial
70
32-Lead 450-Mil SOIC
Commercial
CY62128VLL-70SC
CY62128VL-70ZC
S34
Z32
32-Lead TSOP Type 1
CY62128VLL-70ZC
Z32
CY62128VXL-70ZC
CY62128VL-70ZAC
CY62128VLL-70ZAC
CY62128VL-70ZRC
CY62128VLL-70ZRC
CY62128VL-70SI
Z32
ZA32
ZA32
ZR32
ZR32
S34
32-Lead STSOP Type 1
32-Lead Reverse TSOP 1
32-Lead 450-Mil SOIC
32-Lead TSOP Type 1
32-Lead STSOP Type 1
32-Lead Reverse TSOP 1
32-Lead 450-Mil SOIC
32-Lead TSOP Type 1
32-Lead STSOP Type 1
32-Lead Reverse TSOP 1
32-Lead 450-Mil SOIC
32-Lead TSOP Type 1
32-Lead STSOP Type 1
32-Lead Reverse TSOP 1
32-Lead 450-Mil SOIC
32-Lead TSOP Type 1
32-Lead STSOP Type 1
32-Lead Reverse TSOP 1
70
Industrial
CY62128VLL-70SI
S34
CY62128VL-70ZI
Z32
CY62128VLL-70ZI
Z32
CY62128VL-70ZAI
ZA32
ZA32
ZR32
ZR32
S34
CY62128VLL-70ZAI
CY62128VL-70ZRI
CY62128VLL-70ZRI
CY62128V25L-100SC
CY62128V25LL-100SC
CY62128V25L-100ZC
CY62128V25LL-100ZC
CY62128V25L-100ZAC
CY62128V25LL-100ZAC
CY62128V25L-100ZRC
CY62128V25LL-100ZRC
CY62128V25L-100SI
CY62128V25LL-100SI
CY62128V25L-100ZI
CY62128V25LL-100ZI
CY62128V25L-100ZAI
CY62128V25LL-100ZAI
CY62128V25L-100ZRI
CY62128V25LL-100ZRI
CY62128V18L-200SC
CY62128V18LL-200SC
CY62128V18L-200ZC
CY62128V18LL-200ZC
CY62128V18L-200ZAC
CY62128V18LL-200ZAC
CY62128V18L-200ZRC
CY62128V18LL-200ZRC
100
100
200
Commercial
S34
Z32
Z32
ZA32
ZA32
ZR32
ZR32
S34
Industrial
S34
Z32
Z32
ZA32
ZA32
ZR32
ZR32
S34
Commercial
S34
Z32
Z32
ZA32
ZA32
ZR32
ZR32
8
CY62128V Family
Ordering Information (continued)
Speed
(ns)
Package
Operating
Range
Ordering Code
CY62128V18L-200SI
CY62128V18LL-200SI
CY62128V18L-200ZI
CY62128V18LL-200ZI
CY62128V18L-200ZAI
CY62128V18LL-200ZAI
CY62128V18L-200ZRI
CY62128V18LL-200ZRI
Name
Package Type
32-Lead 450-Mil SOIC
200
S34
Industrial
S34
Z32
32-Lead TSOP Type 1
32-Lead STSOP Type 1
32-Lead Reverse TSOP 1
Z32
ZA32
ZA32
ZR32
ZR32
Document #: 38-00547-B
Package Diagrams
32-Lead (450 MIL) Molded SOIC S34
51-85081-A
9
CY62128V Family
Package Diagrams (continued)
32-Lead Thin Small Outline Package Z32
51-85056-C
10
CY62128V Family
Package Diagrams (continued)
32-Lead Shrunk Thin Small Outline Package ZA32
51-85094-B
11
CY62128V Family
Package Diagrams (continued)
32-Lead Reverse Thin Small Outline Package ZR32
51-85089-B
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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