CY62136FV30LL-45BVXI [CYPRESS]
2-Mbit (128K x 16) Static RAM; 2兆位（ 128K ×16 ）静态RAM
| 型号： | CY62136FV30LL-45BVXI |
| 厂家： | 
CYPRESS |
| 描述： | 2-Mbit (128K x 16) Static RAM |
| 文件： | 总12页 (文件大小：509K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62136FV30 MoBL®
2-Mbit (128K x 16) Static RAM
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE HIGH). The input and
output pins (IO0 through IO15) are placed in a high impedance
state when:
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive: –40°C to +125°C
■ Deselected (CE HIGH)
■ Wide voltage range: 2.20V–3.60V
■ Outputs are disabled (OE HIGH)
■ Pin compatible with CY62136V, CY62136CV30/CV33, and
CY62136EV30
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Ultra low standby power
■ Write operation is active (CE LOW and WE LOW)
❐ Typical standby current: 1µA
❐ Maximum standby current: 5 µA (Industrial)
■ Ultra low active power
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A16). If Byte High
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■ Easy memory expansion with CE, and OE features
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15
)
■ Automatic power down when deselected
■ CMOS for optimum speed and power
is written into the location specified on the address pins (A0
through A16).
■ Available in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Functional Description
The CY62136FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
128K x 16
RAM Array
IO0–IO7
IO8–IO15
A2
A1
A0
BHE
WE
CE
COLUMN DECODER
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-08402 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 03, 2007
CY62136FV30 MoBL®
Product Portfolio
Power Dissipation
VCC Range (V)
Operating ICC (mA)
f = 1MHz f = fmax
Speed
(ns)
Standby ISB2
(mA)
Product
Range
Min
Typ [1]
3.0
Max
Typ [1]
Max
2.5
3
Typ [1]
Max
18
Typ [1]
Max
5
CY62136FV30LL
Industrial
2.2
2.2
3.6
3.6
45
55
1.6
2
13
15
1
1
Automotive
3.0
25
20
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [2, 3]
Figure 2. 44-Pin TSOP II [2]
A
A
A
A
A
7
OE
BHE
BLE
IO
15
IO
IO
13
IO
1
2
3
4
5
6
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
5
6
A
A
A
2
1
A0
A1
A2
NC
A
B
C
OE
BLE
0
A4
A6
A7
A3
A5
IO8 BHE
CE
IO1
IO3
IO0
IO2
CE
IO
0
IO10
IO11
IO
1
IO9
VSS
VCC
14
IO
9
2
IO
3
10
11
12
13
14
15
16
12
VCC
D
E
F
NC
V
V
SS
CC
V
V
CC
IO
IO
SS
A16 IO4 VSS
IO12 NC
A14
IO
4
5
6
7
11
10
IO
IO
IO
IO
IO
A15
IO5
WE
IO6
IO7
NC
IO14 IO13
9
8
NC
WE 17
A12 A13
IO15
NC
NC
A8
G
H
A
A
A
A
A
18
19
20
21
A
8
16
15
14
13
A
9
A
A
A9
A10 A11
10
11
12 22
NC
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ)
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Document Number: 001-08402 Rev. *D
Page 2 of 12
CY62136FV30 MoBL®
DC Input Voltage [4, 5].......... –0.3V to 3.9V (VCC(max) + 0.3V)
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage ......................................... > 2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................ –65°C to + 150°C
Latch up Current .................................................... > 200 mA
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Operating Range
Supply Voltage to Ground
Potential ............................. –0.3V to 3.9V (VCC(max) + 0.3V)
Ambient
Temperature
[6]
Device
Range
VCC
DC Voltage Applied to Outputs
CY62136FV30LL Industrial –40°C to +85°C 2.2V to 3.6V
Automotive –40°C to +125°C
in High Z State [4, 5].............. –0.3V to 3.9V (VCC(max) + 0.3V)
Electrical Characteristics
Over the Operating Range
45 ns (Industrial)
55 ns (Automotive)
Parameter
Description
Test Conditions
Min Typ[1]
Max
Min Typ[1]
Max
Unit
V
VOH
Output HIGH Voltage
2.2 < VCC < 2.7
IOH = –0.1 mA
IOH = –1.0 mA
IOL = 0.1 mA
IOL = 2.1mA
2.0
2.4
2.0
2.4
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
2.2 < VCC < 2.7
2.7 < VCC < 3.6
V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.4
0.4
0.4
0.4
V
V
1.8
2.2
VCC + 0.3 1.8
VCC + 0.3 2.2
VCC + 0.3
VCC + 0.3
0.6
V
V
–0.3
–0.3
–1
0.6
0.8
+1
–0.3
–0.3
–4
V
0.8
V
IIX
Input Leakage Current GND < VI < VCC
+4
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
–4
+4
ICC
VCC Operating Supply f = fmax = 1/tRC
VCC = VCCmax
IOUT = 0 mA
CMOS Levels
13
18
15
2
25
3
mA
Current
f = 1 MHz
1.6
2.5
ISB1
Automatic CE Power
DownCurrent—CMOS VIN > VCC – 0.2V, VIN < 0.2V,
Inputs
CE > VCC – 0.2V,
1
1
5
5
1
20
µA
f = fmax (Address and Data Only),
f = 0 (OE, WE, BHE, and BLE), VCC = 3.60V
[7]
ISB2
Automatic CE Power
CE > VCC – 0.2V,
1
20
µA
DownCurrent—CMOS VIN > VCC – 0.2V or VIN < 0.2V,
Inputs f = 0, VCC = 3.60V
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max
Unit
pF
10
10
COUT
pF
Notes
4.
5.
V
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
=V +0.75V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
7. Only chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the I
/ I
specification. Other inputs can be left floating.
SB2 CCDR
Document Number: 001-08402 Rev. *D
Page 3 of 12
CY62136FV30 MoBL®
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
VFBGA
TSOP II
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
two layer printed circuit board
75
77
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
10
13
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
VCC
OUTPUT
VCC
90%
10%
GND
Rise Time = 1 V/ns
R2
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.5V (2.2V to 2.7V)
3.0V (2.7V to 3.6V)
Unit
Ω
R1
R2
16667
15385
8000
1.20
1103
1554
645
Ω
RTH
VTH
Ω
1.75
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VCC for Data Retention
Data Retention Current
Conditions
Min
Typ [1]
Max
Unit
VDR
1.5
V
[7]
ICCDR
VCC = 1.5V, CE > VCC - 0.2V,
IN > VCC - 0.2V or VIN < 0.2V
Industrial
4
µA
V
Automotive
12
[8]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[9]
tR
tRC
Data Retention Waveform
Figure 4. Data Retention Waveform [10]
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 1.5V
VCC
t
t
R
CDR
CE or
BHE.BLE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V ramp from V to V > 100 µs or stable at V > 100 µs.
CC(min)
CC
DR
CC(min)
10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 001-08402 Rev. *D
Page 4 of 12
CY62136FV30 MoBL®
Switching Characteristics
Over the Operating Range [11, 12]
45 ns (Industrial)
55 ns (Automotive)
Parameter
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
45
10
55
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
45
55
tOHA
Data Hold from Address Change
tACE
45
22
55
25
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
OE LOW to Low Z [13]
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
OE HIGH to High Z [13, 14]
CE LOW to Low Z [13]
18
18
20
20
CE HIGH to High Z [13, 14]
CE LOW to Power Up
tPD
45
22
55
25
CE HIGH to Power Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z [13]
BLE/BHE HIGH to High Z [13, 14]
tDBE
tLZBE
tHZBE
Write Cycle [15]
5
10
18
20
tWC
tSCE
tAW
Write Cycle Time
45
35
35
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
tHA
tSA
0
0
tPWE
tBW
35
35
25
0
40
40
25
0
WE Pulse Width
BLE/BHE LOW to Write End
Data Setup to Write End
tSD
tHD
Data Hold From Write End
WE LOW to High Z [13, 14]
WE HIGH to Low Z [13]
tHZWE
tLZWE
18
20
10
10
Notes
11. Test conditions for all parameters, other than tri-state parameters, assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” on page 4.
CC(typ)
OL OH
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
13. At any given temperature and voltage condition, t
device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any given
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
14. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
15. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals are ACTIVE to initiate a write and any of these
IL
IL
signals can terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
Document Number: 001-08402 Rev. *D
Page 5 of 12
CY62136FV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle No.1: Address Transition Controlled. [16, 17]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Figure 6. Read Cycle No. 2: OE Controlled [17, 18]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
16. The device is continuously selected. OE, CE = V , BHE and/or BLE = V .
IL
IL
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-08402 Rev. *D
Page 6 of 12
CY62136FV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No 1: WE Controlled [15, 19, 20]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 21
DATAIN
DATA IO
t
HZOE
Figure 8. Write Cycle 2: CE Controlled [15, 19, 20]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA IO
NOTE 21
t
HZOE
Notes
19. Data IO is high impedance if OE = V
.
IH
20. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
21. During this period, the IOs are in output state. Do not apply input signals.
Document Number: 001-08402 Rev. *D
Page 7 of 12
CY62136FV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle 3: WE controlled, OE LOW [20]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA IO
NOTE 21
DATAIN
t
LZWE
t
HZWE
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW [20]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 21
DATAIN
DATA IO
tLZWE
Document Number: 001-08402 Rev. *D
Page 8 of 12
CY62136FV30 MoBL®
Truth Table
CE WE OE BHE BLE
Inputs or Outputs
High Z
Mode
Deselect or Power Down
Deselect or Power Down
Read
Power
H
X
L
X
X
H
H
X
X
L
X
H
L
X
H
L
Standby (ISB
)
)
High Z
Standby (ISB
Data Out (IO0–IO15
)
Active (ICC
)
)
L
L
H
L
Data Out (IO0–IO7);
IO8–IO15 in High Z
Read
Active (ICC
L
H
L
L
H
Data Out (IO8–IO15);
IO0–IO7 in High Z
Read
Active (ICC
)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (IO0–IO15)
L
H
Data In (IO0–IO7);
IO8–IO15 in High Z
Write
L
L
X
L
H
Data In (IO8–IO15);
IO0–IO7 in High Z
Write
Active (ICC
)
Document Number: 001-08402 Rev. *D
Page 9 of 12
CY62136FV30 MoBL®
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62136FV30LL-45BVXI
CY62136FV30LL-45ZSXI
CY62136FV30LL-55ZSXE
45
51-85150 48-Ball VFBGA (Pb-Free)
51-85087 44-Pin TSOP II (Pb-Free)
51-85087 44-Pin TSOP II (Pb-Free)
Industrial
55
Automotive
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
SEATING PLANE
C
51-85150-*D
Document Number: 001-08402 Rev. *D
Page 10 of 12
CY62136FV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-Pin TSOP II
51-85087-*A
Document Number: 001-08402 Rev. *D
Page 11 of 12
CY62136FV30 MoBL®
Document History Page
Document Title: CY62136FV30 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 001-08402
Issue
Date
Orig. of
Change
REV. ECN NO.
Description of Change
New datasheet
**
467351 See ECN
797956 See ECN
NXR
VKN
*A
Converted from preliminary to final
Changed ISB1(typ) and ISB1(max) specification from 0.5 µA to 1.0 µA and
2.5 µA to 5.0 µA, respectively
Changed ISB2(typ) and ISB2(max) specification from 0.5 µA to 1.0 µA and
2.5 µA to 5.0 µA, respectively
Changed ICCDR(typ) and ICCDR(max) specification from 0.5 µA to 1.0 µA and
2.5 µA to 4.0 µA, respectively
Changed ICC(max) specification from 2.25 µA to 2.5 µA
*B
869500 See ECN
901800 See ECN
VKN
VKN
Added Automotive information
Updated Ordering information table
Added footnote 12 related to tACE
*C
*D
Added footnote 9 related to ISB2 and ICCDR
Made footnote 13 applicable to AC parameters from tACE
1371124 See ECN VKN/AESA Converted Automotive information from preliminary to final
Changed IIX min spec from –1 µA to –4 µA and IIX max spec from +1 µA to +4 µA
Changed IOZ min spec from –1 µA to –4 µA and IOZ max spec from +1 µA to +4 µA
Changed tDBE spec from 55 ns to 25 ns for automotive part
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-08402 Rev. *D
Revised August 03, 2007
Page 12 of 12
MoBLis aregisteredtrademarkandMoreBatteryLifeisatrademarkofCypress Semiconductor. Allproductandcompanynamesmentionedin thisdocument are thetrademarks of their respective holders.
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