CY62138CV25LL-70BVIT [CYPRESS]
Standard SRAM, 256KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36;
| 型号： | CY62138CV25LL-70BVIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36 |
| 文件： | 总12页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
2M (256K x 8) Static RAM
bits. This device features advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
Life™ (MoBL®) in portable applications. The device also has
an automatic power-down feature that significantly reduces
power consumption by 80% when addresses are not toggling.
The device can be put into standby mode reducing power
consumption by more than 99% when deselected (CE1 HIGH
or CE2 LOW).
Features
• Very high speed: 55 ns and 70 ns
• Voltage range:
— CY62138CV25: 2.2V–2.7V
— CY62138CV30: 2.7V–3.3V
— CY62138CV33: 3.0V–3.6V
Writing to the device is accomplished by taking Chip Enable 1
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is
then written into the location specified on the address pins (A0
through A17).
— CY62138CV: 2.7V–3.6V
• Pin-compatible with CY62138V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1 MHz
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable 2 (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
— Typical active current: 5.5 mA @ f = fmax (70-ns
speed)
• Low standby power
• Easy memory expansion with CE1, CE2, and OE
features
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH and WE LOW).
See the truth table at the back of this data sheet for a complete
description of read and write modes.
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 36-ball FBGA
Functional Description[1]
The CY62138CV25/30/33 and CY62138CV are high-perfor-
mance CMOS static RAMs organized as 256K words by eight
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
Data in Drivers
A
0
A
1
A
2
3
4
A
A
A
5
A
256K x 8
ARRAY
6
A
7
A
8
A
9
A
10
A
11
6
7
POWER
DOWN
CE
CE
COLUMN
DECODER
1
2
I/O
WE
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05200 Rev. *D
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised September 20, 2002
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
[2, 3]
FBGA (Top View)
1
2
4
Pin
3
5
6
Configuration
A
A
A
A
CE
A
6
A
B
C
3
8
1
2
0
A
I/O
WE
A
I/O
0
A
4
4
7
2
DNU
A
I/O
I/O
1
5
5
V
V
SS
CC
D
E
F
V
CC
V
SS
NC
CE
A
17
I/O
I/O
2
6
A
G
H
I/O
OE
A
A
I/O
1
16
7
15
3
A
A
A
13
A
A
14
12
11
10
9
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current ................................................... > 200 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................55°C to +125°C
Ambient
Range Temperature TA
Product
VCC
CY62138CV25 Industrial –40°C to +85°C 2.2V to 2.7V
Supply Voltage to Ground Potential ... –0.5V VCCMAX + 0.5V
CY62138CV30
CY62138CV33
CY62138CV
2.7V to 3.3V
3.0V to 3.6V
2.7V to 3.6V
DC Voltage Applied to Outputs
in High-Z State[4] .....................................0.5V to VCC + 0.3V
DC Input Voltage[4].................................–0.5V to VCC + 0.3V
Output Current into Outputs (LOW) ............................20 mA
Product Portfolio
Power Dissipation
Operating, ICC (mA) Standby, ISB2 (µA)
f = 1 MHz f = fmax
Typ.[5] Max. Typ.[5] Max. Typ.[5]
VCC Range (V)
Speed
Product
Min.
Typ.[5]
Max.
(ns)
55
70
55
70
55
70
70
Max.
CY62138CV25LL
2.2
2.5
2.7
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3
3
3
3
3
3
3
7
15
12
15
12
15
12
12
2
2
5
5
10
5.5
7
CY62138CV30LL
CY62138CV33LL
2.7
3.0
2.7
3.0
3.3
3.3
3.3
3.6
3.6
10
15
15
5.5
7
5.5
5.5
CY62138CVLL
Notes:
2. NC pins are not connected to the die.
3. C3 (DNU) can be left as NC or VSS to ensure proper application.
4. VIL(min.) = –2.0V for pulse durations less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05200 Rev. *D
Page 2 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Electrical Characteristics Over the Operating Range
CY62138CV25-55
CY62138CV25-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[5] Max. Min. Typ.[5] Max. Unit
Output HIGH Voltage IOH = –0.1 mA
Output LOW Voltage IOL = 0.1 mA
Input HIGH Voltage
VCC = 2.2V
VCC = 2.2V
2.0
1.8
2.0
V
V
V
VOL
0.4
0.4
VIH
VCC
+
1.8
VCC +
0.3V
0.3V
0.6
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
0.6 –0.3
V
Input Leakage Current GND < VI < VCC
+1
+1
–1
–1
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
ICC
VCC Operating Supply f = fMAX = 1/tRC
VCC = 2.7V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
Current
f = 1 MHz
1.5
ISB1
Automatic CE
Power-down Current
— CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
IN > VCC – 0.2V or VIN < 0.2V, f =
max (Address and Data Only), f = 0
2
10
2
10
µA
V
f
(OE, WE)
ISB2
Automatic CE
CE1 > VCC – 0.2V or CE2 < 0.2V
Power-down Current VIN > VCC − 0.2VorVIN < 0.2V,f=0,VCC
— CMOS Inputs
= 2.7V
CY62138CV30-55
CY62138CV30-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[5] Max. Min. Typ.[5] Max. Unit
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 2.7V
VCC = 2.7V
2.4
2.2
2.4
2.2
V
V
V
VOL
0.4
0.4
VIH
VCC
+
VCC +
0.3V
0.3V
0.8
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8 –0.3
V
Input Leakage Current GND < VI < VCC
+1
+1
–1
–1
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
ICC
VCC Operating Supply f = fMAX = 1/tRC
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
Current
f = 1 MHz
1.5
ISB1
Automatic CE
Power-down Current
— CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
IN > VCC – 0.2V or VIN < 0.2V, f =
max (Address and Data Only), f = 0
2
10
2
10
µA
V
f
(OE, WE)
ISB2
Automatic CE
Power-down Current > VCC − 0.2V or VIN < 0.2V, f = 0,
CE1 > VCC – 0.2V or CE2 < 0.2V, VIN
— CMOS Inputs VCC=3.3V
Document #: 38-05200 Rev. *D
Page 3 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Electrical Characteristics Over the Operating Range
CY62138CV33-70
CY62138CV-70
CY62138CV33-55
Parameter
Description
Test Conditions
Min. Typ.[5] Max. Min. Typ.[5] Max. Unit
VOH
Output HIGH Voltage IOH = –1.0 mA
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 3.0V
VCC = 2.7V
VCC = 3.0V
VCC = 2.7V
2.4
2.4
2.4
V
V
V
V
V
VOL
VIH
0.4
0.4
0.4
2.2
VCC
+
2.2
VCC +
0.3V
0.3V
0.8
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8 –0.3
V
Input Leakage Current GND < VI < VCC
+1
+1
–1
–1
µA
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
ICC
VCC Operating Supply f = fMAX = 1/tRC
VCC = 3.6V
IOUT = 0 mA
CMOS Levels
7
15
3
5.5
1.5
12
3
mA
Current
f = 1 MHz
1.5
ISB1
Automatic CE
Power-downCurrent—
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
5
15
5
15
µA
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE)
ISB2
Automatic CE
Power-downCurrent— VIN > VCC − 0.2V or VIN < 0.2V,
CE1 > VCC – 0.2V or CE2 < 0.2V
CMOS Inputs f = 0, VCC = 3.6V
Capacitance[6]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz, VCC = VCC(typ.)
6
8
pF
pF
COUT
Thermal Resistance
Parameter
Description
Test Conditions
BGA
Unit
ΘJA
Thermal Resistance[6]
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
55
°C/W
ΘJC
Thermal Resistance[6]
(Junction to Case)
16
°C/W
AC Test Loads and Waveforms
R1
V
CC
ALL INPUT PULSES
OUTPUT
V
Typ
CC
90%
10%
90%
10%
R2
30 pF
GND
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05200 Rev. *D
Page 4 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Parameters
2.5V
16600
15400
8000
1.20
3.0V
1105
1550
645
3.3V
1216
1374
645
Unit
Ω
R1
R2
Ω
RTH
VTH
Ω
1.75
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
Conditions
Min.
Typ.[5]
Max.
VCC(max.)
6
Unit
V
VCC for Data Retention
Data Retention Current
1.5
VCC = 1.5V
CE1 > VCC – 0.2V or CE2 < 0.2V
1
µA
VIN > VCC − 0.2V or VIN < 0.2V
[6]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[7]
tR
Operation Recovery Time
tRC
Data Retention Waveform
DATA RETENTION MODE
> 1.5 V
V
V
V
CC
V
CC(min.)
CC(min.)
DR
t
t
R
CDR
CE
1
or
CE
2
Switching Characteristics Over the Operating Range[8]
55 ns
70 ns
Parameter
Read Cycle
Description
Min.
55
Max.
Min.
70
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[9]
OE HIGH to High-Z[9, 10]
CE1 LOW and CE2 HIGH to Low-Z[9]
CE1 HIGH or CE2 LOW to High-Z[9, 10]
CE1 LOW and CE2 HIGH to Power-up
CE1 HIGH or CE2 LOW to Power-down
10
10
tACE
55
25
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
20
20
55
25
25
70
tPD
Write Cycle[11]
tWC
Write Cycle Time
55
45
70
60
ns
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
Notes:
7. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05200 Rev. *D
Page 5 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Switching Characteristics Over the Operating Range[8] (continued)
55 ns
70 ns
Parameter
Description
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Min.
45
0
Max.
Min.
60
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tAW
tHA
tSA
0
0
tPWE
tSD
40
25
0
45
30
0
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9, 10]
WE HIGH to Low-Z[9]
tHD
tHZWE
tLZWE
20
25
10
10
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
12. Device is continuously selected. OE, CE1 = VIL, CE2=VIH
.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05200 Rev. *D
Page 6 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[11, 15, 17]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA
VALID
DATA I/O
IN
NOTE 16
t
HZOE
[11, 15, 17]
Write Cycle No. 2 (CE1 or CE2 Controlled)
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
t
HA
AW
t
PWE
WE
OE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Notes:
15. Data I/O is high impedance if OE = VIH
.
16. During this period, the I/Os are in output state and input signals should not be applied.
17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state.
Document #: 38-05200 Rev. *D
Page 7 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW) [17]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATAI/O
DATA VALID
IN
t
t
LZWE
HZWE
Document #: 38-05200 Rev. *D
Page 8 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C)
Operating Current vs. Supply Voltage
14.0
12.0
14.0
12.0
14.0
12.0
14.0
12.0
10.0
10.0
10.0
10.0
MoBL
MoBL
MoBL
MoBL
(f = f
55 ns)
,
(f = f
55 ns)
,
(f = f
55 ns)
,
8.0
6.0
max
8.0
6.0
4.0
(f = f
,
max
max
8.0
6.0
4.0
max
8.0
6.0
4.0
55 ns)
(f = f
,
max
(f = f
,
(f = f
70 ns)
,
max
max
(f = f
70 ns)
,
max
70 ns)
70 ns)
4.0
2.0
0.0
2.0
0.0
2.0
0.0
2.0
0.0
(f = 1MHz)
(f = 1MHz)
3.6
(f = 1MHz)
2.7
(f = 1MHz)
3.0
3.6
2.7
3.3
3.3
3.0
3.3
SUPPLY VOLTAGE (V)
2.7
2.2
2.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
10.0
12.0
12.0
MoBL
MoBL
10.0
8.0
10.0
8.0
10.0
8.0
MoBL
MoBL
8.0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.0
2.2
2.7
2.7
2.5
3.3
3.6
3.0
3.3
3.6
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
50
40
30
60
60
60
MoBL
MoBL
MoBL
MoBL
50
40
30
50
40
30
50
40
30
20
20
20
20
10
0
10
0
10
0
10
0
3.6
3.0
3.3
2.2
2.5
3.0
2.7
3.6
2.7
3.3
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Truth Table
CE1
H
CE2
X
WE
X
OE
X
Inputs/Outputs
Mode
Power
High-Z
Deselect/Power-down
Standby (ISB
Standby (ISB
Active (ICC
)
X
L
X
X
High-Z
Deselect/Power-down
Read
)
L
H
H
L
Data Out (I/O0-I/O7)
High-Z
)
L
H
H
H
X
Output Disabled
Write
Active (Icc)
Active (Icc)
L
H
L
Data in (I/O0-I/O7)
Document #: 38-05200 Rev. *D
Page 9 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Ordering Information
Speed
(ns)
Voltage
Range (V)
Package
Name
Operating
Range
Ordering Code
Package Type
70
CY62138CV25LL-70BAI
CY62138CV25LL-70BVI
CY62138CV30LL-70BAI
CY62138CV30LL-70BVI
CY62138CV33LL-70BAI
CY62138CV33LL-70BVI
CY62138CVLL-70BAI
CY62138CVLL-70BVI
CY62138CV25LL-55BAI
CY62138CV25LL-55BVI
CY62138CV30LL-55BAI
CY62138CV30LL-55BVI
CY62138CV33LL-55BAI
CY62138CV33LL-55BVI
2.2–2.7
2.2–2.7
2.7–3.3
2.7–3.3
3.0–3.6
3.0–3.6
2.7–3.6
2.7–3.6
2.2–2.7
2.2–2.7
2.7–3.3
2.7–3.3
3.0–3.6
3.0–3.6
BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Industrial
55
Package Diagrams
36-ball FBGA (7 x 7 x 1.2 mm) BA36A
51-85099-*C
Document #: 38-05200 Rev. *D
Page 10 of 12
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Package Diagrams (continued)
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
51-85149-*A
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05200 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
®
®
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Document History Page
Document Title: CY62138CV25/30/33 MoBL®/CY62138CV MoBL® 2M (256K x 8) Static RAM
Document Number: 38-05200
REV.
ECN NO. Issue Date Orig. of
Change
Description of Change
**
112381
114024
02/19/02
04/25/02
GAV
JUI
New Data Sheet (advance information)
*A
Added BV package diagram
Changed from Advance Information to Preliminary
*B
*C
117062
118123
07/12/02
09/09/02
MGN
MGN
Added Second Chip Enable
Changed from Preliminary to Final
Added new part number: CY62138CV with wider voltage (2.7V – 3.6V)
For TAA = 55 ns, improved tPWE min. from 45 ns to 40 ns
For TAA = 70 ns, improved tPWE min. from 60 ns to 45 ns
For TAA = 70 ns, improved tLZWE min. from 5 ns to 10 ns
*D
118760
09/23/02
MGN
Improved Typ. ICC spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns).
Improved Max ICC spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns).
For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns.
Changed upper spec. for Supply Voltage to Ground Potential to VCCMAX
0.5V.
+
Changed upper spec for DC Voltage Applied to Ouputs in High-Z State and
DC Input Voltage to VCC + 0.3V.
Document #: 38-05200 Rev. *D
Page 12 of 12
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