CY62138FV30LL-45ZXIT [CYPRESS]
Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 20 MM, 1 MM HEIGHT, LEAD FREE, TSOP1-32;
| 型号： | CY62138FV30LL-45ZXIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX8, 45ns, CMOS, PDSO32, 8 X 20 MM, 1 MM HEIGHT, LEAD FREE, TSOP1-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62138FV30 MoBL®
2-Mbit (256 K × 8) Static RAM
2-Mbit (256
K × 8) Static RAM
Features
Functional Description
■ Very high-speed: 45 ns
The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Place the device into standby mode reducing
power consumption when deselected (CE1 HIGH or CE2 LOW).
■ Temperature ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Pin compatible with CY62138CV25/30/33
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A17).
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 5 A
■ Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
■ Easy memory expansion with CE1, CE2, and OE Features
■ Automatic power down when deselected
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
■ Complementary metal oxide semiconductor (CMOS) for
Optimum speed and power
■ Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin
SOIC, 32-pin TSOP I and 32-pin STSOP packages
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-08029 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 12, 2014
CY62138FV30 MoBL®
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................17
Document Conventions .................................................17
Units of Measure .......................................................17
Document History Page .................................................18
Sales, Solutions, and Legal Information ......................20
Worldwide Sales and Design Support .......................20
Products ....................................................................20
PSoC® Solutions ......................................................20
Cypress Developer Community .................................20
Technical Support .....................................................20
Document Number: 001-08029 Rev. *N
Page 2 of 20
CY62138FV30 MoBL®
Pin Configurations
Figure 1. 36-ball VFBGA (Top View) [1]
Figure 2. 32-pin SOIC/TSOP II (Top View)
1
2
4
3
5
6
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
A17
A16
A14
A12
A7
1
2
32
31
30
29
28
27
26
25
24
23
22
A
A
A8
I/O
A1
A2
CE2
A0
6
A
B
C
3
3
4
5
A
I/O
WE
NC
A7
4
0
4
A6
6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
7
A
I/O
I/O
1
8
9
10
5
5
V
CC
V
SS
D
E
F
11
12
13
14
15
16
CE1
21
20
19
18
17
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
V
CC
NC
A
17
I/O
I/O
6
2
CE1
A
G
H
I/O
OE
A15
I/O
16
7
3
A
A
A
A
A9
A14
12
11
13
10
Figure 3. 32-pin TSOP I (Top View)
Figure 4. 32-pin STSOP (Top View)
A
A
A
24
23
22
OE
11
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
25
26
1
2
32
31
OE
A10
A
9
8
10
CE
26
7
3
4
5
6
7
8
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
28
29
30
31
32
1
2
3
4
5
6
7
8
A
21
20
19
18
17
16
15
14
13
12
11
10
9
I/O
I/O
I/O
13
7
6
5
WE
CE
2
A
STSOP
Top View
(not to scale)
15
I/O
I/O
TSOP I
Top View
(not to scale)
4
3
V
CC
A
A
GND
17
16
9
I/O
2
10
11
12
13
14
15
16
I/O
1
A
A
14
12
I/O
0
A
A
A
A
A
0
7
A
1
6
A1
A2
A3
A
2
5
4
A
3
Product Portfolio
Power Dissipation
VCC Range (V)
Operating ICC (mA)
f = 1 MHz f = fmax
Speed
(ns)
Standby ISB2
Product
Range
(A)
Min
2.2
Typ [2] Max
3.0 3.6
Typ [2] Max Typ [2] Max Typ [2] Max
CY62138FV30LL
Industrial /
Automotive-A
45
1.6
2.5
13
18
1
5
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ.)
Document Number: 001-08029 Rev. *N
Page 3 of 20
CY62138FV30 MoBL®
DC input voltage [3, 4] .....................................–0.3 V to 3.9 V
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch-up current ....................................................> 200 mA
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Operating Range
Supply voltage to ground
potential .........................................................–0.3 V to 3.9 V
Ambient
[5]
Product
Range
VCC
Temperature
DC voltage applied to outputs
in High Z State [3, 4] ........................................–0.3 V to 3.9 V
CY62138FV30LL Industrial /
Automotive-A
–40 °C to
+85 °C
2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
45 ns (Industrial / Automotive-A)
Parameter
VOH
Description
Test Conditions
IOH = –0.1 mA
Unit
Min
2.0
2.4
–
Typ [6]
Max
Output HIGH voltage
–
–
–
V
V
IOH = –1.0 mA, VCC > 2.70 V
IOL = 0.1 mA
–
VOL
VIH
VIL
Output LOW voltage
Input HIGH voltage
Input LOW voltage
–
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
VCC = 2.2 V to 2.7 V
–
0.4
V
1.8
2.2
–0.3
–0.3
–0.3
–1
–
VCC + 0.3 V
V
VCC= 2.7 V to 3.6 V
–
VCC + 0.3 V
V
VCC = 2.2 V to 2.7 V For BGA package
VCC= 2.7 V to 3.6 V
–
0.6
0.8
0.6
+1
V
–
V
VCC = 2.2 V to 3.6 V For other packages
GND < VI < VCC
–
V
IIX
Input leakage current
Output leakage current
–
A
A
mA
IOZ
ICC
GND < VO < VCC, output disabled
–1
–
+1
VCC Operating supply current f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
OUT = 0 mA,
CMOS levels
,
–
13
1.6
18
I
–
2.5
[7]
ISB1
Automatic CE Power-down
current–CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
IN > VCC – 0.2 V, VIN < 0.2 V,
–
–
1
1
5
5
A
A
V
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = 3.60 V
[7]
ISB2
Automatic CE Power-down
current–CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
3.
4.
V
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
5. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ.)
7. Chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
Document Number: 001-08029 Rev. *N
Page 4 of 20
CY62138FV30 MoBL®
Capacitance
Parameter[8]
Description
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ.)
Max
10
Unit
pF
CIN
Input Capacitance
Output Capacitance
COUT
10
pF
Thermal Resistance
32-pin
SOIC
36-ball
32-pin
32-pin
STSOP
32-pin
TSOP I
Parameter[8]
Description
Test Conditions
Unit
VFBGA TSOP II
JA
Thermal resistance
(Junction to Ambient) inch, two layer printed circuit
Still air, soldered on a 3 × 4.5
44.53
38.49
17.66
44.16
11.97
59.72
15.38
50.19
14.59
C/W
board
JC
Thermal resistance
(Junction to Case)
24.05
C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
90%
10%
90%
10%
R2
GND
Rise Time = 1 V/ns
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameter
2.5 V (2.2 V to 2.7 V)
3.0 V (2.7 V to 3.6 V)
Unit
R1
R2
16667
15385
8000
1.20
1103
1554
645
V
RTH
VTH
1.75
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-08029 Rev. *N
Page 5 of 20
CY62138FV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VCC for data retention
Data retention current
Conditions
Min
1.5
–
Typ [9]
Max
–
Unit
V
VDR
–
1
[10]
ICCDR
VCC = 1.5 V, CE1 > VCC 0.2 V
or CE2 < 0.2 V, VIN > VCC 0.2 V
or VIN < 0.2 V
Industrial /
Automotive-A
4
A
[11]
tCDR
Chip deselect to data
retention time
0
–
–
–
–
ns
ns
[12]
tR
Operation recovery time
45
Data Retention Waveform
Figure 6. Data Retention Waveform [13]
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 1.5 V
VCC
CE
t
t
R
CDR
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ.)
10. Chip enables (CE and CE ) must be at CMOS level to meet the I
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device AC operation requires linear V ramp from V to V > 100 s or stable at V > 100 s.
CC(min)
CC
DR
CC(min)
13. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
Document Number: 001-08029 Rev. *N
Page 6 of 20
CY62138FV30 MoBL®
Switching Characteristics
Over the Operating Range
45 ns (Industrial/
Automotive-A)
Parameter [14, 15]
Description
Unit
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
Data hold from address change
tOHA
10
–
tACE
45
22
–
CE1 LOW and CE2 HIGH to data valid
OE LOW to
tDOE
–
data valid
tLZOE
OE LOW to Low Z [16]
5
tHZOE
OE HIGH to High Z [16, 17]
–
18
–
CE1 LOW and CE2 HIGH to Low Z [16]
CE1 HIGH or CE2 LOW to High Z [16, 17]
CE1 LOW and CE2 HIGH to Power-up
CE1 HIGH or CE2 LOW to Power-down
tLZCE
10
–
tHZCE
18
–
tPU
0
tPD
–
45
Write Cycle [18, 19]
tWC
Write cycle time
45
35
35
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW and CE2 HIGH to write end
Address setup to
–
write end
tHA
Address hold from
–
write end
tSA
Address setup to Write Start
WE pulse Width
0
–
tPWE
tSD
35
25
0
–
Data setup to
–
write end
tHD
Data hold from
–
write end
tHZWE
tLZWE
WE LOW to High Z [16, 17]
WE HIGH to Low Z [16]
–
18
–
10
Notes
14. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described
in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Notes is no longer applicable. It is available
for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
15. Test conditions for all parameters other than tristate parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
, and output loading of the specified I /I as shown in the AC Test Loads and Waveforms on page 5.
CC(typ)
OL OH
16. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t for any given device.
LZWE
HZCE
LZCE HZOE
LZOE
HZWE
17. t
, t
, and t
transitions are measured when the output enters a high impedance state.
HZOE HZCE
HZWE
18. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these signals
1
IL
2
IH
can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
19. .The minimum write pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be the sum of t
and t
HZWE
SD.
Document Number: 001-08029 Rev. *N
Page 7 of 20
CY62138FV30 MoBL®
Switching Waveforms
Figure 7. Read Cycle 1 (Address Transition Controlled) [20, 21]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 8. Read Cycle No. 2 (OE Controlled) [21, 22, 23]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
ISB
t
V
PU
CC
50%
SUPPLY
CURRENT
50%
Figure 9. Write Cycle No. 1 (WE Controlled) [23, 24, 25, 26]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
27
DATA I/O
NOTE
DATA VALID
t
HZOE
Notes
20. The device is continuously selected. OE, CE = V , CE = V .
1
IL
2
IH
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
23. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
24. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
25. Data I/O is high impedance if OE = V
.
IH
26. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
1
2
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-08029 Rev. *N
Page 8 of 20
CY62138FV30 MoBL®
Switching Waveforms (continued)
Figure 10. Write Cycle No. 2 (CE1 or CE2 Controlled) [28, 29, 30, 31]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Figure 11. Write Cycle No. 3 (WE Controlled, OE LOW) [28, 31, 33]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
32
NOTE
DATA VALID
DATA I/O
t
t
LZWE
HZWE
Notes
28. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.
1
2
1
2
1
2
29. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
1
IL
2
IH
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
30. Data I/O is high impedance if OE = V
.
IH
31. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains iin high impedance state.
1
2
32. During this period, the I/Os are in output state. Do not apply input signals.
33. The minimum write pulse width for Write Cycle No. 2 (WE controlled, OE LOW) should be the sum of t
and t
SD
HZWE
Document Number: 001-08029 Rev. *N
Page 9 of 20
CY62138FV30 MoBL®
Truth Table
CE1
CE2
X[34]
WE
X
OE
X
Inputs/Outputs
Mode
Power
H
High Z
High Z
Deselect/Power-down
Deselect/Power-down
Read
Standby (ISB
)
)
X[34]
L
L
X
X
Standby (ISB
H
H
L
Data out
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
H
H
X
Output disabled
Write
L
H
L
Data in
Note
34. The ‘X’ (Don’t care) state for the Chip enables (CE and CE ) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
1
2
pins is not permitted.
Document Number: 001-08029 Rev. *N
Page 10 of 20
CY62138FV30 MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62138FV30LL-45BVXI
CY62138FV30LL-45ZAXI
CY62138FV30LL-45ZXI
CY62138FV30LL-45SXI
CY62138FV30LL-45ZAXA
51-85149 36-ball VFBGA (Pb-free)
51-85094 32-pin STSOP (Pb-free)
51-85056 32-pin TSOP I (Pb-free)
51-85081 32-pin SOIC (Pb-free)
51-85094 32-pin STSOP (Pb-free)
Industrial
Automotive-A
Ordering Code Definitions
X
X
F V30
- 45 XX
LL
3
CY 621
8
Temperature Grade: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = BV or ZS or ZA or Z or S
BV = 36-ball VFBGA
ZS= 32-pin TSOP II
ZA = 32-pin STSOP
Z = 32-pin TSOP I
S = 32-pin SOIC
Speed Grade: 45 ns
LL = Low Power
Voltage Range: 3 V Typical
F = Process Technology 90 nm
Buswidth = × 8
Density = 2-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-08029 Rev. *N
Page 11 of 20
CY62138FV30 MoBL®
Package Diagrams
Figure 12. 36-ball VFBGA (6 × 8 × 1.0 mm) BV36A Package Outline, 51-85149
51-85149 *E
Document Number: 001-08029 Rev. *N
Page 12 of 20
CY62138FV30 MoBL®
Package Diagrams (continued)
Figure 13. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
51-85095 *B
Document Number: 001-08029 Rev. *N
Page 13 of 20
CY62138FV30 MoBL®
Package Diagrams (continued)
Figure 14. 32-pin Molded SOIC (450 Mil) S32.45/SZ32.45 Package Outline, 51-85081
51-85081 *E
Document Number: 001-08029 Rev. *N
Page 14 of 20
CY62138FV30 MoBL®
Package Diagrams (continued)
Figure 15. 32-pin TSOP I (8 × 20 ×1.0 mm) Z32R Package Outline, 51-85056
51-85056 *G
Document Number: 001-08029 Rev. *N
Page 15 of 20
CY62138FV30 MoBL®
Package Diagrams (continued)
Figure 16. 32-pin STSOP (8 × 13.4 × 1.2 mm) ZA32 Package Outline, 51-85094
51-85094 *G
Document Number: 001-08029 Rev. *N
Page 16 of 20
CY62138FV30 MoBL®
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BGA
Ball Grid Array
Unit of Measure
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
°C
MHz
A
s
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
OE
Output Enable
SOIC
SRAM
STSOP
TSOP
VFBGA
WE
Small-Outline Integrated Circuit
Static Random Access Memory
Small Thin Small Outline Package
Thin Small Outline Package
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-08029 Rev. *N
Page 17 of 20
CY62138FV30 MoBL®
Document History Page
Document Title: CY62138FV30 MoBL®, 2-Mbit (256 K × 8) Static RAM
Document Number: 001-08029
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
463660
467351
See ECN
See ECN
NXR
NXR
New data sheet.
*A
Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages
Changed ball A3 from NC to CE2 in 36-ball FBGA pin out
*B
566724
See ECN
NXR
VKN
Converted from Preliminary to Final
Corrected typo in 32 pin TSOP II pin configuration diagram on page #2
(changed pin 24 from CE1to OE and pin 22 from CE to CE1)
Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz
Changed the ISB2(typ) value from 0.5 A to 1 A
Changed the ISB2(max) value from 2.5 A to 5 A
Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from
2.5 A to 4 A
*C
797956
See ECN
Added 32-pin SOIC package
Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on
Electrical characteristics table
*D
*E
*F
809101
940341
2769239
See ECN
See ECN
09/25/09
VKN
VKN
Corrected typo in the Ordering Information table
Added footnote #7 related to ISB2 and ICCDR
Included Automotive-A information
VKN /
AESA
*G
3055119
10/12/2010
RAME
Updated and converted all tablenotes into Footnote
Added Ordering Code Definitions.
Updated All Package Diagrams.
Added Acronyms and Units of Measure table
Updated data sheet as per new template.
*H
*I
3061313
3078557
10/15/2010
11/04/2010
RAME
RAME
Minor changes: Corrected “IO” to “I/O”
Corrected 55 C to -55C in Ambient Temperature with Power applied in
Maximum Ratings Section
*J
3235744
04/20/2011
RAME
Removed the note “For best practice recommendations, refer to the Cypress
application Note “System Design Guidelines” at http://www.cypress.com “ in
page 1 and its reference in Functional Description.
Updated Package Diagrams.
*K
*L
3285093
3845087
06/16/2011
12/18/2012
RAME
TAVA
Updated in new template.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85149 – Changed revision from *D to *E.
spec 51-85081 – Changed revision from *C to *E.
*M
4099045
08/19/2013
VINI
Updated Switching Characteristics:
Added Note 14 and referred the same note in “Parameter” column.
Updated in new template.
Document Number: 001-08029 Rev. *N
Page 18 of 20
CY62138FV30 MoBL®
Document History Page (continued)
Document Title: CY62138FV30 MoBL®, 2-Mbit (256 K × 8) Static RAM
Document Number: 001-08029
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
Updated Switching Characteristics:
*N
4377056
05/12/2014
MEMJ
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 33 and referred the same note in Figure 11.
Updated Package Diagrams:
spec 51-85056 – Changed revision from *F to *G.
spec 51-85094 – Changed revision from *F to *G.
Completing Sunset Review.
Document Number: 001-08029 Rev. *N
Page 19 of 20
CY62138FV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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Automotive
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cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Community | Forums | Blogs | Video | Training
Technical Support
Memory
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/support
PSoC
Touch Sensing
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Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2006-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-08029 Rev. *N
Revised May 12, 2014
Page 20 of 20
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