CY62146E_11 [CYPRESS]
4-Mbit (256K x 16) Static RAM; 4兆位（ 256K ×16 ）静态RAM
| 型号： | CY62146E_11 |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (256K x 16) Static RAM |
| 文件： | 总14页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62146E MoBL
4-Mbit (256K x 16) Static RAM
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH) or during a write operation (CE LOW and WE LOW).
Features
■ Very high speed: 45 ns
■ Wide voltage range: 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Table for a complete description
of read and write modes.
■ Available in Pb-free 44-pin thin small outline package (TSOP)
II package
Functional Description
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life (MoBL) in portable
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-07970 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 20, 2011
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CY62146E MoBL
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................4
Thermal Resistance ..........................................................4
Data Retention Characteristics .......................................5
Switching Characteristics ................................................6
Switching Waveforms ......................................................7
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagram ............................................................11
Acronyms ........................................................................12
Document Conventions .................................................12
Units of Measure .......................................................12
Document History Page .................................................13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC Solutions .........................................................14
Document Number: 001-07970 Rev. *G
Page 2 of 14
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CY62146E MoBL
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View) [1]
A
A
A
A
A
A
A
A
7
OE
BHE
BLE
I/O
15
I/O
I/O
13
I/O
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
2
1
0
5
6
CE
I/O
I/O
I/O
I/O
0
1
2
3
14
9
10
11
12
13
14
15
16
12
V
V
SS
CC
V
SS
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
4
11
10
5
6
7
9
8
WE 17
NC
A
A
A
A
A
A
18
19
20
17
16
15
8
A
9
A
10
A
11
A
12
14 21
13 22
Product Portfolio
Power Dissipation
Operating ICC, (mA)
f = 1 MHz f = fmax
Typ [2]
Max
2.5
VCC Range (V)
Speed
(ns)
Standby, ISB2
Product
Range
(A)
Min
Typ[2]
Max
Typ [2]
Max
Typ [2]
Max
CY62146ELL
Ind’l/Auto-A
4.5
5.0
5.5
45
2
15
20
1
7
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document Number: 001-07970 Rev. *G
Page 3 of 14
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CY62146E MoBL
Output current into outputs (LOW) .............................. 20 mA
Maximum Ratings
Static discharge voltage............................................>2001 V
(MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch-up current ......................................................>200 mA
Storage temperature................................. –65 °C to +150 °C
Operating Range
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Ambient
Temperature
[5]
Device
Range
VCC
Supply voltage to ground potential .................–0.5 V to 6.0 V
CY62146ELL
Industrial/ –40 °C to +85 °C 4.5 V–5.5 V
Auto-A
DC voltage applied to outputs
in high Z state [3, 4] ...........................................–0.5 V to 6.0 V
DC input voltage [3, 4] .......................................–0.5 V to 6.0 V
Electrical Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
Parameter
VOH
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Test Conditions
Min
2.4
–
Typ[6]
Max
Unit
V
IOH = –1.0 mA
IOL = 2.1 mA
–
–
–
0.4
VOL
VIH
VIL
IIX
V
4.5 < VCC < 5.5
4.5 < VCC < 5.5
GND < VI < VCC
2.2
–0.5
–1
–1
–
–
VCC + 0.5
0.8
V
–
V
Input leakage current
–
+1
A
A
mA
IOZ
ICC
Output leakage current GND < VO < VCC, output disabled
–
+1
VCC operating supply
current
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA, CMOS levels
15
2
20
–
2.5
[7]
ISB2
Automatic CE power
down current — CMOS
inputs
–
1
7
A
CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
V
=
f = 0, VCC
CC(max)
Capacitance
Parameter[8]
Description
Test Conditions
Max
Unit
CIN
Input capacitance
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
10
10
pF
pF
COUT
Output capacitance
Thermal Resistance
Parameter[8]
Description
Test Conditions
TSOP II
Unit
JA
Thermal resistance
(Junction to ambient)
Still Air, soldered on a 3 × 4.5 inch, two layer
printed circuit board
77
C/W
JC
Thermal resistance
(Junction to case)
13
C/W
Notes
3. V (min) = –2.0 V for pulse durations less than 20 ns for I < 30 mA.
IL
4.
V (max) = V + 0.75 V for pulse durations less than 20 ns.
IH CC
5. Full Device AC operation assumes a minimum of 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
7. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/ I
spec. Other inputs are left floating.
SB2 CCDR
8. Tested initially after any design or process changes that may affect these parameters.
Document Number: 001-07970 Rev. *G
Page 4 of 14
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CY62146E MoBL
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
VCC
OUTPUT
VCC
90%
10%
GND
Fall Time = 1 V/ns
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
5.0 V
THÉVENIN EQUIVALENT
RTH
VTH
Parameters
Unit
R1
R2
1800
990
RTH
VTH
639
1.77
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VCC for data retention
Data retention current
Conditions
Min
2
Typ[9]
Max
–
Unit
V
VDR
–
1
[10]
VCC = 2 V, CE > VCC – 0.2 V,
–
7
A
ICCDR
VIN > VCC – 0.2 V or VIN < 0.2 V
[11]
tCDR
Chip deselect to data
retention time
0
–
–
–
–
ns
ns
[12]
tR
Operation recovery time
45
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 2.0 V
VCC
t
t
R
CDR
CE
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
10. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
11. Tested initially and after any design or process changes that may affect these parameters.
/ I
spec. Other inputs are left floating.
SB2 CCDR
12. Full device operation requires linear V ramp from V to V
> 100 s or stable at V > 100 s.
CC
DR
CC(min)
CC(min)
Document Number: 001-07970 Rev. *G
Page 5 of 14
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CY62146E MoBL
Switching Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
Parameter[13, 14]
Description
Unit
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
CE LOW to data valid
10
–
tACE
45
22
–
–
tDOE
OE LOW to data valid
OE LOW to LOW Z[15]
OE HIGH to High Z[15, 16]
CE LOW to Low Z[15]
CE HIGH to High Z[15, 16]
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
–
18
–
10
–
18
–
CE LOW to power-up
0
–
–
tPD
CE HIGH to power-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z[15]
BLE/BHE HIGH to HIGH Z[15, 16]
45
22
–
tDBE
tLZBE
tHZBE
Write Cycle [17]
tWC
5
–
18
Write cycle time
45
–
–
–
–
–
–
–
–
–
ns
tSCE
tAW
tHA
tSA
CE LOW to write end
35
35
ns
ns
Address setup to write end
Address hold from write end
Address setup to write start
0
0
ns
ns
tPWE
tBW
tSD
WE pulse width
35
35
25
0
ns
ns
ns
ns
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
tHD
WE LOW to High Z[15, 16]
WE HIGH to Low Z[15]
18
–
ns
ns
–
tHZWE
tLZWE
10
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of 1.5 V, input pulse
levels of 0 to 3 V, and output loading of the specified I /I as shown in AC Test Loads and Waveforms on page 5.
OL OH
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
16. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
17. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of these
IL
IL
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document Number: 001-07970 Rev. *G
Page 6 of 14
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CY62146E MoBL
Switching Waveforms
Figure 4. Read Cycle No.1: Address Transition Controlled[18, 19]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2: OE Controlled [19, 20]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
18. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V
.
IL
IL
19. WE is HIGH for read cycle.
20. Address valid before or similar to CE, BHE, BLE transition LOW.
Document Number: 001-07970 Rev. *G
Page 7 of 14
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CY62146E MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle No 1: WE Controlled [21, 22, 23]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 24
DATAIN
DATA I/O
t
HZOE
Figure 7. Write Cycle 2: CE Controlled [21, 22, 23]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 24
t
HZOE
Notes
21. WE is HIGH for read cycle.
22. Data I/O is high impedance if OE = V
.
IH
23. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
24. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-07970 Rev. *G
Page 8 of 14
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CY62146E MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle 3: WE controlled, OE LOW [25]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA I/O
NOTE 26
DATAIN
t
LZWE
t
HZWE
Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [25]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 26
DATAIN
DATA I/O
tLZWE
Notes
25. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
26. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-07970 Rev. *G
Page 9 of 14
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CY62146E MoBL
Truth Table
CE[27]
WE
X
OE
X
BHE
X[27]
H
BLE
X[27] High Z
Inputs/Outputs
Mode
Deselect/power down
Output disabled
Read
Power
H
L
L
L
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
X
X
H
L
L
High Z
Data out (I/O0–I/O15
)
H
L
L
)
)
H
L
H
Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data in (I/O0–I/O15
)
)
L
H
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Note
27. Chip enable (CE) and byte enables (BHE and BLE) must be at CMOS levels (not floating) to meet the I
/ I
spec. Intermediate voltage levels on these pins is
SB2 CCDR
not permitted.
Document Number: 001-07970 Rev. *G
Page 10 of 14
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CY62146E MoBL
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
45
CY62146ELL-45ZSXI
CY62146ELL-45ZSXA
51-85087 44-pin thin small outline package II (Pb-free)
51-85087 44-pin thin small outline package II (Pb-free)
Industrial
Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
E
45 ZSX
X
LL
-
4
621
CY
6
Temperature Range: I = Industrial, A = Automotive-A
Package type = 44-pin TSOP II (Pb-free)
Speed Grade
Separator
Low Power
E = Process Technology 90 nm
Buswidth = ×16
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Package Diagram
Figure 10. 44-Pin TSOP II, 51-85087
PIN 1 I.D.
22
1
Z
Z
Z
Z
Z
X
AA
EJECTOR MARK
(OPTIONAL)
23
44
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
BOTTOM VIEW
TOP VIEW
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
BASE PLANE
10.262 (0.404)
10.058 (0.396)
0.10 (.004)
0°-5°
0.210 (0.0083)
0.120 (0.0047)
18.517 (0.729)
18.313 (0.721)
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
DIMENSION IN MM (INCH)
MAX
MIN.
51-85087-*C
Document Number: 001-07970 Rev. *G
Page 11 of 14
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CY62146E MoBL
Acronyms
Acronym
CMOS
I/O
Description
complementary metal oxide semiconductor
input/output
SRAM
static random access memory
thin small outline package
TSOP
Document Conventions
Units of Measure
Symbol
Unit of Measure
ns
V
nano seconds
volts
µA
mA
pF
°C
W
micro amperes
milli amperes
pico Farad
degree Celsius
watts
Document Number: 001-07970 Rev. *G
Page 12 of 14
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CY62146E MoBL
Document History Page
Document Title: CY62146E MoBL 4-Mbit (256K x 16) Static RAM
Document Number: 001-07970
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
463213
684343
See ECN
See ECN
NXR
New Data Sheet
*A
VKN
Added Preliminary Automotive-A Information
Updated Ordering Information Table
*B
925501
See ECN
VKN
Added footnote #8 related to ISB2 and ICCDR
Added footnote #13 related AC timing parameters
*C
*D
1045260
2073548
See ECN
VKN
Converted Automotive-A specs from preliminary to final
See ECN VKN/AESA Corrected typo in the Data Retention Waveform and removed its irrelevant
footnote
*E
2943752
06/03/2010
VKN
Added Contents
Added footnote related to chip enable in Truth Table
Updated Package Diagram
Added Sales, Solutions, and Legal Information
*F
3109050
3149059
12/13/2010
01/20/2011
PRAS
RAME
Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
*G
Updated as per latest template
Corrected Errors in Ordering Code Definitions
Added Acronyms and Units of Measure table
Document Number: 001-07970 Rev. *G
Page 13 of 14
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CY62146E MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-07970 Rev. *G
Revised January 20, 2011
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MoBLisa registeredtrademark andMoreBattery Life is atrademark of Cypress Semiconductor. Allproduct andcompany names mentionedin this documentare thetrademarks oftheirrespectiveholders.
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