CY62147DV30L [CYPRESS]
4-Mbit (256K x 16) Static RAM; 4兆位（ 256K ×16 ）静态RAM
| 型号： | CY62147DV30L |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (256K x 16) Static RAM |
| 文件： | 总12页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62147DV30
4-Mbit (256K x 16) Static RAM
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O0 through I/O15) are placed in a high-im-
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62147CV25, CY62147CV30, and
CY62147CV33
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
• Packages offered 48-ball BGA and 44-pin TSOPII
• Also available in Lead-Free packages
• Byte power-down feature
Functional Description[1]
The CY62147DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin
TSOPII packages.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
Power -Down
Circuit
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05340 Rev. *D
Revised February 2, 2005
CY62147DV30
Pin Configuration[2, 3, 4]
VFBGA (Top View)
44 TSOP II (Top View)
1
4
2
5
3
6
NC
I/O
44
1
A
A
5
4
A
A
A
43
42
41
40
39
38
37
36
35
34
33
A
A
6
OE
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BLE
0
1
2
A
B
C
3
A
A
2
7
OE
A
1
A
A
I/O BHE
CE
I/O
4
3
0
8
BHE
BLE
A
0
CE
I/O
I/O
A
A
I/O
I/O
2
I/O
0
15
5
6
10
1
9
I/O
I/O
I/O
1
14
13
12
I/O
2
Vcc
Vss
A
V
I/O
I/O
3
A17
D
E
F
SS
7
11
I/O
V
I/O
3
V
SS
CC
V
V
SS
DNU
A
16
V
CC
CC
I/O
I/O
12
4
32
I/O
I/O
I/O
4
5
6
7
11
10
9
8
31
30
29
28
27
26
25
I/O
I/O
I/O
A
A
15
I/O
I/O
I/O
I/O
I/O
I/O
14
13
5
14
6
NC
WE 17
A
A
G
H
I/O
NC
WE
I/O
7
13
12
18
15
A
A17
8
19
A
A
16
9
A
20
21
22
A
15
10
A
A
A
A
NC
NC
10
9
11
8
A
11
A
24
23
14
A
A
12
13
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1MHz f = fmax Standby ISB2 (µA)
Speed
(ns)
Product
VCC Range (V)
Typ.[5]
Min.
2.20V
Max.
3.60
Typ.[5]
Max.
3
Typ.[5]
Max.
20
Typ.[5]
Max.
12
8
CY62147DV30L
CY62147DV30LL
CY62147DV30L
CY62147DV30LL
CY62147DV30L
CY62147DV30LL
3.0
45
55
70
1.5
1.5
1.5
10
2
2.20V
2.20V
3.0
3.0
3.60
3.60
3
3
8
15
15
2
2
12
8
12
8
8
Notes:
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating or tied to V to ensure proper application.
SS
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
CC
, T = 25°C.
A
CC(typ.)
Document #: 38-05340 Rev. *D
Page 2 of 12
CY62147DV30
DC Input Voltage[6,7]......................–0.3V to VCC(MAX) + 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient Tem-
[8]
Supply Voltage to Ground
Device
Range perature (TA)
VCC
Potential......................................–0.3V to + VCC(MAX) + 0.3V
CY62147DV30L Industrial –40°C to +85°C 2.20V to 3.60V
CY62147DV30LL
DC Voltage Applied to Outputs
in High-Z State[6,7]..........................–0.3V to VCC(MAX) + 0.3V
Electrical Characteristics (Over the Operating Range)
CY62147DV30-45 CY62147DV30-55 CY62147DV30-70
Parameter Description
Test Conditions
Min. Typ.[5] Max. Min. Typ.[5] Max. Min. Typ.[5] Max. Unit
VOH
VOL
VIH
OutputHIGH IOH = –0.1 mA VCC = 2.20V
2.0
2.4
2.0
2.4
2.0
2.4
V
V
V
V
V
Voltage
IOH = –1.0 mA VCC = 2.70V
Output LOW IOL = 0.1 mA VCC = 2.20V
0.4
0.4
0.4
0.4
0.4
0.4
Voltage
IOL = 2.1 mA VCC = 2.70V
Input HIGH VCC = 2.2V to 2.7V
1.8
2.2
VCC
+
1.8
2.2
VCC
+
1.8
2.2
VCC +
Voltage
0.3V
0.3V
0.3V
VCC= 2.7V to 3.6V
VCC
+
VCC
+
VCC
+
V
0.3V
0.3V
0.3V
VIL
IIX
Input LOW VCC = 2.2V to 2.7V
–0.3
–0.3
–1
0.6 –0.3
0.8 –0.3
0.6 –0.3
0.8 –0.3
0.6
0.8
+1
V
V
µA
Voltage
VCC= 2.7V to 3.6V
Input
GND < VI < VCC
+1
–1
+1
–1
Leakage
Current
IOZ
Output
GND < VO < VCC, Output
Disabled
–1
+1
–1
+1
–1
+1
µA
Leakage
Current
ICC
VCC
f = fMAX
1/tRC
f = 1 MHz
=
VCC=VCCmax
IOUT = 0 mA
CMOS levels
10
20
3
8
15
3
8
15
3
mA
Operating
Supply
Current
1.5
2
1.5
2
1.5
2
mA
ISB1
Automatic
CE > VCC−0.2V,
L
LL
12
8
12
8
12
8
µA
CE
VIN>VCC–0.2V, VIN<0.2V)
Power-Down f = fMAX (Address and Data
Current — Only),
CMOS
Inputs
f = 0 (OE, WE, BHE and
BLE), VCC = 3.60V
ISB2
Automatic
CE > VCC – 0.2V,
L
LL
2
12
8
2
12
8
2
12
8
µA
CE
V
IN > VCC – 0.2V or
Power-Down VIN < 0.2V,
Current — f = 0, VCC = 3.60V
CMOS
Inputs
Notes:
6. V
7. V
= –2.0V for pulse durations less than 20 ns.
CC
IL(min.)
IH(max)
=V + 0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100-µs ramp time from 0 to V (min) and 200-µs wait time after V stabilization.
CC
CC
Document #: 38-05340 Rev. *D
Page 3 of 12
CY62147DV30
Capacitance (for all packages)[9]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
Max.
10
Unit
pF
CIN
Input Capacitance
Output Capacitance
VCC = VCC(typ)
COUT
10
pF
Thermal Resistance[9]
Parameter
Description
Test Conditions
BGA
TSOP II
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
72
75.13
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
8.86
8.95
°C/W
AC Test Loads and Waveforms[10]
R1
ALL INPUT PULSES
VCC
VCC
GND
90%
90%
OUTPUT
10%
Rise Time = 1 V/ns
10%
Fall Time = 1 V/ns
R2
50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50V
16667
15385
8000
3.0V
1103
1554
645
Unit
Ω
R1
R2
RTH
VTH
Ω
Ω
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min. Typ.[5] Max. Unit
1.5
V
VCC= 1.5V
CE > VCC – 0.2V,
L
LL
9
6
µA
VIN > VCC – 0.2V or VIN < 0.2V
[9]
tCDR
tR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
tRC
ns
ns
[11]
Data Retention Waveform[12]
DATA RETENTION MODE
VCC(min)
VCC(min)
V
> 1.5 V
V
DR
CC
t
t
R
CDR
CE or
BHE.BLE
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Test condition for the 45 ns part is a load capacitance of 30 pF.
11. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC(min.)
CC
DR
CC(min.)
12. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05340 Rev. *D
Page 4 of 12
CY62147DV30
Switching Characteristics Over the Operating Range[13]
45 ns[10]
55 ns
70 ns
Parameter
Read Cycle
tRC
tAA
tOHA
Description
Min.
Max.
Min.
55
Max.
Min.
70
Max.
Unit
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
45
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
55
70
10
10
tACE
tDOE
45
25
55
25
70
35
OE LOW to Data Valid
OE LOW to LOW Z[14]
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[16]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
5
10
0
5
10
0
5
10
0
OE HIGH to High Z[14, 15]
CE LOW to Low Z[14]
15
20
20
20
25
25
CE HIGH to High Z[14, 15]
CE LOW to Power-Up
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z[14]
BLE/BHE HIGH to HIGH Z[14, 15]
45
45
55
55
70
70
10
10
10
15
20
25
Write Cycle Time
CE LOW to Write End
45
40
40
0
55
40
40
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[14, 15]
WE HIGH to Low-Z[14]
0
0
0
35
40
25
0
40
40
25
0
45
60
30
0
tHZWE
tLZWE
15
20
25
10
10
10
Notes:
13. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of V
/2,
CC(typ)
input pulse levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
OL OH
CC(typ.)
14. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
15. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedence state.
HZOE HZCE HZBE
HZWE
16. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any
IL
IL
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
Document #: 38-05340 Rev. *D
Page 5 of 12
CY62147DV30
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[17, 18]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[18, 19]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
50%
50%
CURRENT
I
SB
Notes:
17. The device is continuously selected. OE, CE= V , BHE and/or BLE = V
IL
.
IL
18. WE is HIGH for read cycle.
19. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05340 Rev. *D
Page 6 of 12
CY62147DV30
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[16, 20, 21]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATAIN
DATA I/O
NOTE22
t
HZOE
Write Cycle No. 2 (CE Controlled)[16, 20, 21]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 22
t
HZOE
Notes:
20. Data I/O is high impedance if OE = V
.
IH
21. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance state.
IH
22. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05340 Rev. *D
Page 7 of 12
CY62147DV30
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[21]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
NOTE 22
DATAI/O
DATAIN
t
HZWE
t
LZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[21]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
tHD
t
SD
DATA I/O
DATAIN
NOTE 22
tLZWE
Document #: 38-05340 Rev. *D
Page 8 of 12
CY62147DV30
Truth Table
CE
H
X
L
L
WE
X
X
H
H
OE
X
X
L
L
BHE
X
H
L
H
BLE
X
H
L
L
Inputs/Outputs
High Z
High Z
Mode
Deselect/Power-Down
Deselect/Power-Down
Read
Power
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
)
)
Data Out (I/OO–I/O15
)
)
)
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
H
L
L
H
L
L
High Z
High Z
High Z
Data In (I/OO–I/O15
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Write
)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
Name
Package Type
45
CY62147DV30LL-45BVI
BV48A
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
Industrial
CY62147DV30LL-45BVXI
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62147DV30LL-45ZSXI
CY62147DV30L-55BVI
CY62147DV30L-55BVXI
ZS-44
BV48A
44-pin TSOP II (Pb-free)
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
55
Industrial
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62147DV30LL-55BVI
CY62147DV30LL-55BVXI
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
55
70
CY62147DV30L-55ZSXI
CY62147DV30LL-55ZSXI
CY62147DV30L-70BVI
CY62147DV30L-70BVXI
ZS-44
44-pin TSOP II (Pb-free)
Industrial
Industrial
BV48A
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
CY62147DV30LL-70BVI
CY62147DV30LL-70BVXI
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm)
(Pb-free)
70
CY62147DV30L-70ZSXI
CY62147DV30LL-70ZSXI
ZS-44
44-pin TSOP II (Pb-free)
Industrial
Document #: 38-05340 Rev. *D
Page 9 of 12
CY62147DV30
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
Document #: 38-05340 Rev. *D
Page 10 of 12
CY62147DV30
Package Diagram (continued)
44-Pin TSOP II ZS44
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05340 Rev. *D
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62147DV30
Document History Page
Document Title:CY62147DV30 MoBL® 4-Mbit (256K x 16) Static RAM
Document Number: 38-05340
Orig. of
REV.
**
*A
ECN NO. Issue Date Change
Description of Change
127481
131010
213252
06/17/03
01/23/04
See ECN
HRT
CBD
AJU
New Data Sheet
Change from Advance to Preliminary
Change from Preliminary to Final
*B
Added 70 ns speed bin
Modified footnote 7 to include ramp time and wait time
Modified input and output capacitance values to 10 pF
Modified Thermal Resistance values on page 4
Added “Byte power-down feature” in the features section
Modified Ordering Information for Pb-free parts
*C
*D
257349
316039
See ECN
See ECN
PCI
PCI
Modified ordering information for 70-ns Speed Bin
Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #10 on page #4
Added Pb-free package ordering information on page # 9
Changed 44-lead TSOP-II package name on page 11 from Z44 to ZS44
Standardized Icc values across ‘L’ and ‘LL’ bins
Document #: 38-05340 Rev. *D
Page 12 of 12
相关型号：
CY62147DV30L-55BVXE
256KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
ROCHESTER
CY62147DV30L-55BVXIT
Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
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